In this paper, we propose an efficient method (called DIRIC algorithm) to allocate carrier frequencies so as to minimize intermodulation products in two-level SCPC systems in which Hub station and many Remote stations communicate each other through satellite transponder. We also present a very efficient method to evaluate intermodulation products with substantially reduced CPU time in two-level SCPC systems. We compare and analyze the performance of several frequency allocation methods to extend DELINS-INSDEL algorithm (which is proposed by Okinaka) to two-level SCPC systems. When the proposed algorithm is applied to systems with modulated carrier, it is verified that this algorithm has the same efficiency as the unmodulated carrier. It is also shown heuristically that certain initial assignment algorithms perform better than random assignment.

Connection Admission Control (CAC) is a key part of traffic control and still leaves several challenging problems peculiar to ATM networks. One of these problems is how to assign sufficient bandwidth for any cell arrival process that satisfies the source traffic descriptor values specified by negotiation between the network and a user at the connection setup. Because the source traffic descriptor cannot describe the actual source traffic characteristics completely, it has already been studied extensively that how to estimate sufficient bandwidth under the assumption that the actual traffic parameter values in the source traffic descriptor are equal to the negotiated values. This paper extends the studies in the literature to how to estimate sufficient bandwidth only assuming that the actual values satisfy the negotiated values, that is the actual values is less than or equal to the negotiated values. We show the sufficient condition for negotiated source traffic descriptors ensuring that the cell-loss ratio calculated from the negotiated values is always the upper-bound of the actual cell-loss ratio. Using this condition, we propose a CAC that can guarantee cell-loss ratio objective so far as a user satisfies the source traffic descriptor values.

A scalable and flexible ASIC CIM system distributed on UNIX workstations, ORCHARD , has been developed. It is designed from three viewpoints: (1) cost and TAT reduction in system construction, (2) flexibility in data management for quality control, and (3) precise and quick scheduling and effective lot tracking to control TAT for each lot. The concept of a "virtual machine" is introduced to connect equipment having various protocols to a host system. The virtual machine is automatically generated at an average automatic generation ratio of as high as 89%, which leads to a reduction in cost and TAT in system construction. Data for quality control is managed by changing flexibly the "data processing recipe." This recipe defines screen format, data collected from equipment, and data transfered from various databases. Precise scheduling of lots with various levels of priority is achieved by introducing a priority evaluation function, thereby reducing scheduling time to 1/20 that for manual scheduling.

We propose a nonlocal impact ionization model applicable for the drain region where electric field increases exponentially. It is expressed as a function of an electric field and a characteristic length which is determined by a thickness of gate oxide and a source/drain junction depth. An analytical substrate current model for n-MOSFET is also derived from the new nonlocal impact ionization model. The model well explains the reason why the theoretical characteristic length differs from empirical expressions used in a pseudo two-dimensional model for MOSFET's. The nonlocal impact ionization model implemented in a device simulator demonstrates that the new model can predict substrate current correctly in the framework of drift-diffusion model.

In this paper, we describe a worst-case design optimization approach for statistical design of integrated circuits with a circuit performance model scheme. After formulating worst-case optimization to an unconstrained multi-objective function minimization problem, a new objective function is proposed to find an optimal point. Then, based on an interpolation model scheme of approximating circuit performance, realistic worst-case analysis can be easily done by Monte Carlo based method without increasing much the computational load. The effectiveness of the presented approach is demonstrated by a standard test function and a practical circuit design example.

This paper discusses a CMOS differential-difference amplifier circuit suitable for low voltage operation. A new multiple weighted input transconductor circuit structure is suggested to be use in DDA implementation. The proposed DDA can be employed in several analog/digital systems to improve their parameters. Selected examples of the proposed transconductor/DDA applications are also discussed.

The performance of a nonblocking switch with two kinds of correlated input calls is analyzed. We define two kinds of calls as the waiting call and the immediate call, and assume that the immediate call has the priority over the waiting call. If the traffic density of one kind of calls is larger than maximum throughput, the ratio of the corresponding kind of calls to the total traffic must be restrained in some range. We derive the maximum ratio of the waiting call by using two approximate methods. The effects of traffic densities and transition probabilities of two kinds of calls on the maximum ratio of the waiting call are also considered. It is shown that, if the traffic density of the immediate call is smaller than that of the waiting call, our approximate methods are useful to derive the maximum ratio of the waiting call to the total traffic.

Recently as one of attractive applications in the B-ISDN era, LAN/MAN interconnection through an ATM network has been coming up because burstiness of LAN/MAN data traffic is applicable to distinctive features of cell based ATM network. In order to overcome a difference of the connection mode, i.e., CL packet transfer of LAN/MAN and CO cell transfer of ATM network, a number of interworking and bandwidth allocation mechanisms have been proposed. These methods, however, indicate both merits and drawbacks concerning with CL data transfer quality, network resource efficiency and processing overhead in IWU/CLS and the network, and have been mostly evaluated only for a single IWU model. This paper aims at showing the most appropriate method of LAN/MAN interworking for IWU-IWU or IWU-CLSF connection. In the paper, some interworking issues including a general qualitative assessment are clarified. We then evaluate the selected five interworking methods based on Bandwidth Renegotiation (BR) and VC Establishment (VCE), which are combined with Traffic Enforcement Functions (TEFs) based on policing mechanisms and Cell Loss Control (CLC) scheme. By transient and stationary simulation approach for a single IWU and an IWU-CLS connection model, the most applicable method is indicated as a case study from view points of the communication quality, effective use of the bandwidth and processing load.

In this paper we describe the formal conditions to detect and resolve all kinds of pipeline data hazards and propose a scheduling algorithm for pipelined instruction set processor synthesis. The algorithm deals with multi cycle operations and tries to minimize the pipeline execution cycles under a given hardware configuration with/without hardware interlock. The main feature that makes the proposed algorithm different from existing ones is the algorithm is for estimating the performance in HW/SW partitioning, with capability of handling a module library of different FUs and dealing with multi cycle operations to be implemented in software. Experimental results of application to ASIP HW/SW codesign show that the proposed algorithm is effective and considerable pipeline execution cycle reduction rates can be achieved. The time complexity of the scheduing algorithm is of O(n2) in the worst case, where n is the number of instructions in a given basic block.

In this study we shall put forward a synergetic neural network and investigate the association dynamics. The present neuron model is substantially based on a top down formulation of the dynamic rule of an analog neural network in contrast to the conventional framework. It is proved that a complete association can be assured up to the same number of the embedded patterns as the number of neurons. In practice an association process is carried out for practical images with 256 gray scale levels and 256256 size. In addition, a searching process of the embedded patterns is also realised by means of controlling attraction parameters. Finally a stochastic model for the dynamic process is also proposed as an intermediate model between the association and the searching of the embedded patterns. Finally a stochastic property of the present model is characterized by fractal dimension of the excitation level of a neuron.

The design procedure of a multithreaded processor dedicated to the image generation is described, which can be achieved by means of a high-level synthesis tool PARTHENON. The processor employs a multithreaded architecture which is a novel promising approach to the parallel image generation. This paper puts special stress on the high-level synthesis scheme which can simplify the behavioral description for the structure and control of a complex hardware, and therefore enables the design of a complicated mechanism for a multithreaded processor. Implementation results of the synthesis are also shown to demonstrate the performance of the designed processor. This processor greatly improves the throughput of the image generation so far attained by the conventional approach.

We have done a computer search for solutions of the equation x3y3z3n in the range max (|x|, |y|, |z|) 3414387 and 0 n 1000. We have discovered 21 new integer solutions for n {39, 143, 180, 231, 312, 321, 367, 439, 462, 516, 542, 556, 660, 663, 754, 777, 870}. As a result, there are 52 values of n (except n 4 (mod9)) for which no solutions are found.

This paper describes the fabrication of 0.1 µm gate length CMOS devices and analysis of delay time by circuit simulation. In order to reduce the gate resistance, TiN capped cobalt salicide technology is applied to the fabrication of 0.1 µm CMOS devices. Gate sheet resistance with a 0.1 µm gate is as low as 5 Ω/sq. Propagation delay times of 0.1 µm and 0.15 µm CMOS inverter are 21 ps and 36 ps. Simulated propagation delay time agreed fairly well with experimental results. For gate length over 0.15 µm, intrinsic delay in CMOS devices is the main dalay factor. This suggests that increasing current drivability is the most efficient way to improve propagation delay time. At 0.1 µm, each parasitic component and intrinsic delay have similar contributions on device speed due to the short channel effect. To improve delay time, we used rapid thermal annealing or a high dose LDD structure. With this structure, drain current increases by more than 1.3 times and simulation predicted a delay time of 28 ps is possible with 0.15 µm CMOS inverters.

A noise tolerant auto-correlation associative memory is proposed. An associated energy function is formed by a multiplication of plural Hopfield's energy functions each of which includes single pattern as its energy minimum. An asynchronous optimizing algorithm of the whole energy function is also presented based on the binary neuron model. The advantages of this new associative memory are that the orthogonality relation among patterns does not need to be satisfied and each stored pattern has a large basin of attraction around itself. The computer simulations show a fairly good performance of associative memory for arbitrary pattern vectors which are not orthogonal to each other.

It has become more important to reduce the protocol implementation costs as the functions of protocols have become more abundant. The protocol implementation tools which automatically generate a protocol program from a specification described by an FDT (Formal Description Technique) are very promising. Selecting SDL as a target FDT, we have developed an SDL-based protocol implementation tool which consists of a process scheduler and a compiler. Since the efficient SDL process execution is a key to generating the high-speed program, the scheduler is introduced. It provides the mechanism which executes SDL processes concurrently as light-weight-processes. It optimizes so that as few context switches take places as possible. The compiler converts as many kinds of SDL functions whose behaviors can be determined at compile time into programming language statements as possible. These elaborations are so successful that the tool can generate an efficient program. The OSI Transport protocol class 0 program generated by the compiler can process more than 500 packets per second on a 6MIPS workstation.

Surface-channel PMOSFETs are suitable for use in the quarter micron CMOS devices. For surface-channel PMOSFETs with p+ poly-Si gates, boron penetration and hot-carrier effects were investigated. When the annealing temperature is higher and the gate oxide is thinner, a larger threshold voltage shift was observed for p+ poly-Si PMOSFETs, because of boron penetration. Furthermore, PMOSFETs with BF2-implanted gates cause larger boron penetration than those with Boron-implanted gates. Howerer, the PMOSFET lifetime, determined by hot-carrier reliability, does not depend on the degree of boron penetration. Instead, it depends on doping species, that is, BF2 and Boron. PMOSFETs with BF2-implanted gates have about 100 times longer lifetime than those with Boron-implanted gates. The main reason for the longer lifetime of BF2-doped PMOSFETs is the incorporation of fluorine in the gate oxide of the PMOSFET with the BF2-implanted gate, resulting in the smaller electron trapping in the gate oxide. The maximun allowed supply voltage,based on the hot-carrier reliability, is higher than4V for sub-half micron PMOSFETs with BF2- or Boron-implanted poly Si gates.

Carrier mobility is one of the most fundamental parameters in semiconductor device modeling, and many mobility models have already been reported. Especially for numerical device simulators, many local models which are functions of impurity concentration and electric field at each local point have been studied. However, concerning their dependence on impurity concentration including carrier screening effects, these models suffer parameter fitting procedure because of their empirical formulation. In such models, carrier screening effects to the Coulomb potential of ionized impurity are not sufficiently considered, although we can find some models which treat the effects as only a small perturbation term. According to the simple theory of Brooks and Herring, carrier screening effects should be included in strong combination with impurity concentration terms and cannot be treated as additional perturbations. Although Brooks-Herring theory is successful, it also suffers from overestimation of the mobility values at concentration higher than 1018 cm-3 which causes some other complicated phenomena. Therefore there have been no models which directly use Brooks-Herring formula. But it is true that such screening effects should be considered when carrier concentration differs from impurity concentration as in the inversion layers of MOSFETs. We have developed a new mobility model for its dependence of impurity and carrier concentration based on the theory of Brooks-Herring. Brooks-Herring theory is based on simple physics of screened Coulomb potential, and therefore makes the model to include effects of free carriers without an artifitial formula. For high doping regime, an additional term has been introduced in Brooks-Herring formula to correct the high doping effects. Except for this term, the model should be most appropriate for including the carrier screening effects upto the concentration of 1018 cm-3. The new model is implimented in a device simulator, and is applied to the evaluation of MOSFETs especially for the universal curves of inversion layer mobility. Moreoever, the applications to the depletion-type MOSFET confirm the validity of the screening effects. The purpose of this paper is to propose the new mobility model and to show its validity through these applications to MOSFETs.

The Double-Sided Rugged poly Si (DSR) technology has been developed for high density DRAMs. The DSR technology was achieved using transformation of rugged poly Si caused by ion implantation. The DSR can increase the surface area of the storage electrode, because it has rugged surfaces on both upper and lower sides. The 2-FINs STC (STacked Capacitor cell) with DSR was fabricated in the cell size of 0.72 µm2, and it is confirmed that the DSR can increase the surface area 1.8 times larger than that of smooth poly Si. It is expected that 25 fF/bit is obtained with a 300 nm-thick storage electrode. These effects show that sufficient capacitance for 256 Mb DRAMs is obtained with a low storage electrode. It is confirmed that there is no degradation in C-V and I-V characteristics. Moreover, the DSR needs neither complicated process steps nor special technologies. Therefore, the DSR technology is one of the most suitable methods for 256 Mb DRAMs and beyond.

We give a tutorial on high-level synthesis of VLSI. The evolution of digital system synthesis techniques and the need for higher level design automation tools are first discussed. We then point out essential issues to the successful development and acceptance by the designers of a high-level synthesis system. Techniques that have been proposed for various subtasks of high-level synthesis are surveyed. Possible applications of the high level synthesis in area other than chip design are forecast. Finally, we point out several directions for possible future research.

Over the last decade, research in the automatic synthesis and optimization of combinational logic has matured significantly; more recently, research has focused on sequential logic. Many of the paradigms for combinational logic have been extended and applied in the sequential domain. In addition, promising new directions for future research are being explored. In this paper, we survey some of the results of combinational synthesis and some recent results for sequential synthesis and then use these to view possible avenues for future sequential synthesis research. In particular we look at two related questions: deriving a set of permissible behaviors and using a minimizer to select the best behavior according to some optimization criteria. We examine these two issues in increasingly complex situations starting with a single-output function, and proceeding to a single multiple-output function, a network of single-output functions, a network of multiple-output functions, and then similar questions where function" is replaced by a finite state machine (FSM). We end with a discussion of a network of finite state machines and the problem of deriving the set of permissible FSM's and choosing a representative minimum one.