A dual band 0.18 µm CMOS LC-tank injection locked frequency divider (ILFD) is proposed. The ILFD circuit is realized with a cross-coupled pMOS LC-tank oscillator with an inductor switch for frequency band selection. The self-oscillating VCO is injection-locked by nth-harmonic input to obtain the division factor of n. The division ratio of 1, 2, and 3 has been found for the proposed ILFD. Measurement results show that at the supply voltage of 1.1 V, the free-running frequency is from 2.28(3.09) GHz to 2.78(3.72) GHz for the low- (high-) frequency band. The power consumption of the ILFD core is 3.7 mW (6.2 mW) at low (high) band. The total area including the output buffer and the pads is 0.8410.764 mm2.

This paper highlights seven years of research at the Berkeley Wireless Research Center (BWRC) related to mm-wave electronics. Active and passive device design and layout, circuit approaches, and system architecture for short range mm-wave communication links will be discussed. The design of several key building blocks in a receiver front-end will be highlighted.

A wide range CMOS voltage detector with low current consumption consisting of CMOS inverters operating in both weak inversion and saturation region is proposed. A terminal of power supply for CMOS inverter can be expanded to a signal input terminal. A voltage-detection point and hysteresis characteristics of the proposed circuit can be designed by geometrical factor in MOSFET and an external bias voltage. The core circuit elements are fabricated in standard 0.18 µm CMOS process and measured to confirm the operation. The detectable voltage is from 0.3 V to 1.8 V. The current consumption of voltage detection, standby current, is changed from 65 pA for Vin = 0.3 V to 5.5 µA for Vin = 1.8 V. The thermal characteristics from 250 K to 400 K are also considered. The measured temperature coefficient of the proposed voltage-detector core operating in weak inversion region is 4 ppm/K and that in saturation region is 10 ppm/K. The proposed voltage detector can be implemented with tiny chip area and is expected to an on-chip voltage detector of power supply for mobile application systems.

A reference voltage buffer for a multibit/stage pipelined ADC is described, where a settling boost technique is used to improve the settling response of the pipelined stages. A 12 bit 18 MHz pipelined ADC with the buffer is designed and simulated based on a 0.35 µm CMOS process. According to simulation results, the power consumed by the reference voltage buffer is reduced by 33% compared to that without the settling boost technique.

We fabricated both thin film transistors (TFTs) and diodes using zinc oxide (ZnO) and pentacene, and investigated their basic characteristics. We found that field-effect mobility is influenced by the interface state between the semiconductor and dielectric layers. Furthermore, the complementary metal oxide semiconductor (CMOS) inverter using a p-channel pentacene field-effect transistor (FET) and an n-channel ZnO FET showed a relatively high voltage gain (8-12) by optimizing the device structure. The hybrid complementary inverters described here are expected for application in flexible displays, radio frequency identification cards (RFID) tags, and others.

Leakage power consumption of logic elements has become a serious problem, especially in the sub-100-nanometer process. In this paper, a novel power gating approach by using the controlling value of logic elements is proposed. In the proposed method, sleep signals of the power-gated blocks are extracted completely from the original circuits without any extra logic element. A basic algorithm and a probability-based heuristic algorithm have been developed to implement the basic idea. The steady maximum delay constraint has also been introduced to handle the delay issues. Experiments on the ISCAS'85 benchmarks show that averagely 15-36% of logic elements could be power gated at a time for random input patterns, and 3-31% of elements could be stopped under the steady maximum delay constraints. We also show a power optimization method for AND/OR tree circuits, in which more than 80% of gates can be power-gated.

This paper presents the design of a CMOS RF Power Detector (PD) using 0.18 µm standard CMOS technology. The PD is an improved unbalanced source coupled pair incorporating an output differential amplifier and sink current steering. It realizes an input detectable power range of -30 to -20 dBm over 0.1-1 GHz. Also it shows a maximum data rate of 30 Mbps with 2 pF output loading under OOK modulation. The overall current consumption is 1.9 mA under a 1.5 V supply.

Threshold Inverter Quantization (TIQ) technique has been gaining its importance in high speed flash A/D converters due to its fast data conversion speed. It eliminates the need of resistor ladders for reference voltages generation which requires substantial power consumption. The key to TIQ comparators design is to generate 2n - 1 different sized TIQ comparators for an n-bit A/D converter. This paper presents a highly efficient TIQ comparator design methodology based on an analytical model as well as SPICE simulation experimental model. One can find any sets of TIQ comparators efficiently using the proposed method. A 6-bit TIQ A/D converter has been designed in a 0.18 µm standard CMOS technology using the proposed method, and compared to the previous measured results in order to verify the proposed methodology.

Analog-centric RFCMOS technology has played an important role in motivating the change of technology from conventional discrete device technology or bipolar IC technology to CMOS technology. However it introduces many problems such as poor performance, susceptibility to PVT fluctuation, and cost increase with technology scaling. The most important advantage of CMOS technology compared with legacy RF technology is that CMOS can use more high performance digital circuits for very low cost. In fact, analog-centric RF-CMOS technology has failed the FM/AM tuner business and the digital-centric CMOS technology is becoming attractive for many users. It has many advantages; such as high performance, no external calibration points, high yield, and low cost. From the above facts, digital-centric CMOS technology which utilizes the advantages of digital technology must be the right path for future RF technology. Further investment in this technology is necessary for the advancement of RF technology.

A novel CMOS LC quadrature oscillator (QO) which adopts complementary-coupling circuitry has been proposed. The performance improvement in I/Q phase error and phase noise of the proposed QO, is explained in comparison with conventional QOs. The proposed QO is implemented in 0.18 µm CMOS technology along with conventional QOs. The measurement result of the proposed QO shows -133.5 dBc/Hz of phase noise at 1 MHz offset and 0.6 I/Q phase difference, while oscillating at 1.77 GHz. The proposed QO shows more than 6.5 dB phase noise improvement compared to that of the conventional QOs over the offset frequency range of 10 K-1 MHz, while dissipating 4 mA from 1.4 V supply.

To realize low-power wireless transceivers, it is necessary to improve the performance of frequency synthesizers, which are typically frequency multipliers composed of a phase-locked loop (PLL). However, PLLs generally consume a large amount of power and occupy a large area. To improve the frequency multiplier, we propose a pulse-injection-locked frequency multiplier (PILFM), where a spurious signal is suppressed using a pulse input signal. An injection-locked oscillator (ILO) in a PILFM was fabricated by a 0.18 µm 1P5M CMOS process. The core size is 10.8 µm10.5 µm. The power consumption of the ILO is 9.6 µW at 250 MHz, 255 µW at 2.4 GHz and 1.47 mW at 4.8 GHz. The phase noise is -105 dBc/Hz at a 1 MHz offset.

A silicon lateral photodiode is fabricated by standard 0.18 µm CMOS process, and the optical detection property is characterized. The photodiode has interdigital electrode structure with the electrode width of 0.22 µm and the electrode spacing of 0.6 µm. At 830 nm wavelength, the responsivity is 0.12 A/W at low bias voltage, and is increased to 0.6 A/W due to avalanche amplification. The bandwidth is also enhanced from 12 MHz at low bias voltage to 100 MHz at the bias voltage close to the breakdown voltage.

A differential LC-VCO that adopts a transformer with asymmetric turns-ratio has been proposed. The asymmetric turns-ratio of the transformer leads to the suppression of the AM to FM conversion which is caused by the 1/f noise of the current source transistor. The analysis of the proposed scheme and the improvement in phase noise compare to conventional CMOS LC-VCOs are described. The transformer used in proposed VCO occupies about 430430 µm2 of silicon area while the inductor in compared conventional VCO does 390390 µm2.

Source-drain follower has been designed and implemented for monolithically integrated biosensor array. The circuit acts as a voltage follower, in which a sensing transistor is operated at fixed gate-source and gate-drain voltages. It operates at 10 nW power dissipation. The wide-swing cascode configurations are investigated in constant and non-constant biasing methods. The constant biased cascode source-drain follower has the merit of small cell size. The chip was fabricated using 1.2 µm standard CMOS technology, and a wide range of operation between 1 nW and 100 µW was demonstrated. The accuracy of the voltage follower was 30 mV using minimum sized transistors, due to the variation of threshold voltage. The error in the output except for the threshold voltage mismatch was less than 10 mV. The temperature dependence of the output was 0.11 mV/. To improve the input voltage range and accuracy, non-constant biased cascode source-drain follower is examined. The sensor cell is designed for 10 mV accuracy and the cell size is 105.3µm 81.4 µm in 1.2 µm CMOS design rules. The sensor cell was fabricated and showed that the error in the output except for the threshold voltage mismatch was less than 2 mV in a range of total current between 3 nA and 10 µA and in a temperature range between 30 and 100.

In this paper, a new compensation scheme and a corresponding pass element structure for a CMOS low-dropout regulator (LDO) are presented. The proposed approach effectively alleviates the strict stability constraint on the ESR of the output capacitor. Stability of a CMOS LDO with the conventional compensation requires the effective series resistance (ESR) of the output capacitor in a tunnel-like region. With the proposed design approach, an LDO can be stable using an output capacitor without ESR. A 2.5 V/150 mA LDO has been implemented using a 0.5-µm 1P2M CMOS process. The experimental results illustrate that the proposed LDO is stable with an output capacitor of 0.33 µF and no ESR.

A test structure to analyze asymmetry and orientation dependence of MOSFETs is presented. n-MOSFETs with 8 different channel orientation and three kinds of process conditions were measured and symmetry characteristics of IDsat and IBmax with respect to the interchange of source and drain was examined. Although both IDsat and IBmax have similar channel orientation dependence, IBmax in interchanged S/D measurements shows asymmetrical characteristics, which can be applied to a sensitive method for device asymmetry detection.

Novel low phase noise quadrature voltage-controlled oscillator (QVCO) and quadrature injection locked frequency divider (QILFD) with two coupled Hartley VCOs are proposed and implemented using the standard TSMC 0.18 µm CMOS 1P6M process. The QVCO employs pMOS as the core to reduce the up-conversion of low-frequency device noise to RF phase noise. It uses super-harmonic coupling technique to couple two differential Hartley VCOs and four small-size coupling transistors to set the directivity of quadrature output phases. At the 1.7 V supply voltage, the output phase noise of the QVCO is -124 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 4.12 GHz, and the figure of merit is -185 dBc/Hz. At the supply voltage of 1.7 V, the total power consumption is 13.1 mW. At the supply voltage of 1.5 V, the tuning range of the free-running QILFD is from 2.05 GHz to 2.36 GHz, about 310 MHz, and the locking range of the ILFD is from 3.99 to 5.19 GHz, about 1.20 GHz, at the injection signal power of 0 dBm.

This letter presents a 0.5 V low-voltage op-amp in a standard 0.18 µm CMOS process for switched-capacitor circuits. Unlike other two-stage 0.5 V op-amp architectures, this op-amp consists of CMOS inverters that utilize floating voltage sources and forward body bias for obtaining high-speed operation. And two improved common-mode rejection circuits are well combined to achieve low power and chip area reduction. Simulation results indicate that the op-amp has an open-loop gain of 62 dB, and a high unity gain bandwidth of 56 MHz. The power consumption is only 350 µW.

This paper presents a very wideband active RC polyphase filter (ARCPF). We propose a unit section of the ARCPF, which is an ordinary RCPF followed by opamps with parallel RC feedback. In the proposed unit section, pole and zero can be assigned independently. By using the unit ARCPFs, a very wideband image rejection filter can be realized by cascading the sections, which can greatly reduce the element value spread. To realize this, CMOS inverter based fully differential OTA which can operate under low supply voltage is also presented. This paper describes a six-stage active RC polyphase filter with 1-100 MHz passband in 0.18 µm CMOS technology.

This paper proposes a wide-locking range divide-by-3 frequency divider employing 3D helical inductors fabricated in the 0.18-µm 1P6M CMOS technology. The divider consists of an nMOS cross-coupled LC oscillator and two injection MOSFETs in series with the cross-coupled NMOSFETs, and the LC resonator is composed of two 3D helical inductors and varactors. The aim of using 3D inductor is to reduce chip size. At the supply voltage of 1.2 V, the divider free-running frequency is tunable from 2.1 GHz to 2.6 GHz, and at the incident power of 0 dBm the locking range is about 2.11 GHz (29.16%), from the incident frequency 5.99 GHz to 8.1 GHz. The core power consumption is 4.56 mW. The die area is 0.6640.831 mm2.