In this paper, a 24GHz transformer-coupled VCO is presented for a wide linear tuning range in the 0.13-µm CMOS process. The measured results of the proposed VCO show that the center frequency is 23.5GHz with 7.4% frequency tuning range. The output frequency curve has wide linear tuning region (5.5%) at the middle of the curve. Also, the VCO exhibits good phase noise of -110.23dBc/Hz at an offset frequency of 1 MHz. It has a compact chip size of 430 × 500µm2. The VCO core DC power consumption is 5.4mW at 1.35V VDD.

This paper describes a high-speed, robust, scalable, and low-cost feed-forward time amplifier that uses phase detectors and variable delay lines. The amplifier works by detecting the time difference between two rising input edges with a phase detector and adjusting the delay of the variable delay line accordingly. A test chip was designed and fabricated in 65 nm CMOS. The measured resulting performance indicates that it is possible to amplify time difference while maintaining high-speed operation.

We present a multiband LTE SAW-less CMOS transmitter with source-follower-driven passive mixers, envelope-tracked RF-programmable gain amplifiers (RF-PGAs), and Marchand Baluns. A driver stage for passive mixers is realized by a source follower, which enables a quadrature modulator (QMOD) to achieve low noise performance at a 1.2 V supply and contributes to a small-area and low-power transmitter. An envelope-tracking technique is adopted to improve the linearity of RF-PGAs and obtain a better Evolved Universal Terrestrial Radio Access Adjacent Channel Leakage power Ratio (E-UTRA ACLR). The Marchand balun covers more frequency bands than a transformer and is more suitable for multiband operation. The proposed transmitter, which also includes digital-to-analog converters and a phase-locked loop, is implemented in a 65-nm CMOS process. The implemented transmitter achieves E-UTRA ACLR of less than -42 dBc and RX-band noise of less than -158 dBc/Hz in the frequency range of 700 MHz–2.6 GHz. These performances are good enough for multiband LTE and SAW-less operation.

A novel tunneling field-effect transistor (TFET) featuring the sigma-shape embedded SiGe sources and recessed channel is proposed. The gate facing the source effectively focuses the E-field at the tip of the source and eliminates the gradual turn-on issue of planar TFETs. The fabrication scheme modified from the state-of-the-art 45 nm/32 nm CMOS technology flows provides a unique benefit in the co-integrability and the control of ID-VGS characteristics. The feasibility is verified with TCAD process simulation of the device with 14 nm of the gate dimension. The device simulation shows 5-order change in the drain current with a gate bias change less than 300 mV.

We describe 25-Gb/s error-free transmission over multi-mode fiber (MMF) by using a transmitter based on a 1.3-µm lens-integrated surface-emitting laser (LISEL) and a CMOS laser-diode driver (LDD). It demonstrates 25-Gb/s error-free transmission over 30-m MMF under the overfilled-launch condition and over 150-m MMF with a power penalty less than 1.0 dB under the underfilled-launch condition.

Capacitive feedback VCOs use capacitors that are connected from the output node to the gate of the tail transistor that acts as a current source. Using such feedback results in modulating the current that is used by the oscillator and therefore changes its cyclostationary noise properties which results in a lower output phase noise. This paper presents a mathematical study of capacitive feedback VCOs in terms of stability and phase noise enhancement to confirm stability and to explain the enhancement in phase noise. The derived expression for the phase noise shows an improvement of 4.4 dB is achievable by using capacitive feedback as long as the VCO stays in the current limited region. Measurement results taken from an actual capacitive feedback VCO implemented in a 65 nm CMOS process also agrees with the analysis and simulation results which further validates the given analysis.

The design and measured results of a 120 GHz/140 GHz dual-channel OOK (ON-OFF Keying) receiver are presented in this paper. Because a signal with very wide frequency width is difficult to process in a single-channel receiver, a dual-channel configuration with channel selection is adopted in the proposed receiver. The proposed receiver is fabricated using 65 nm CMOS technology. The measured data rate of 3.0 and 3.6 Gbps, minimum sensitivity of -25.6 and -27.1 dBm, communication distance of 0.30 and 0.38 m are achieved in the 120- and 140-GHz receiver, respectively. The correct channel selection is achieved in the 120-GHz receiver. These results indicate the possibility of the CMOS multiband receiver operating at over 100 GHz for low-power high-speed proximity wireless communication systems.

To reduce the power dissipation of the receiver in accordance with the intensity of the received signal, we developed the first intra-symbol intermittent (ISI) radio-frequency (RF) front end with 0.35-µm CMOS technology. In the demodulation mechanism, the RF output of the low-noise amplifier (LNA) is down-converted to an intermediate frequency (IF) by the mixer, and the LNA and mixer operate synchronously and intermittently within the length of a single symbol. Because the time-averaged power consumption is proportional to the operating time, the demodulation can be performed with low power by making the total operating time short. We experimentally demonstrate that demodulation (BPSK: 9.6 kbps) is properly achieved with the operating-time ratio of 12%. This ISI operation of the RF front end is enabled by a newly devised fast-transition LNA and mixer. A theoretical analysis of aliasing noise reveals that RF ISI operation is more useful than current-control with continuous operation and that an operating-time ratio of 10% is optimal.

This paper presents a model to estimate jitter insertion and accumulation in clock repeaters. We propose expressions to estimate, with low computational effort, both static and dynamic clock jitter insertion in repeaters with different sizes, interconnects and slew-rates. It requires only the pre-characterization of a reference repeater, which can be accomplished with a small number of simulations or measurements. Furthermore, we propose expressions for dynamic jitter accumulation that considers the dual nature of power and ground noise impact on delay. The complete model can be used to replace time-consuming transient noise simulations when evaluating jitter in clock distribution systems, and provide valuable insights regarding the impact of design parameters on jitter. Presented results show that our models can estimate jitter insertion and accumulation with an error within 10% of simulation results, for typical designs, and accurately reflect the impact of changing design parameters.

A laser irradiation experiment for photocurrent induced failure investigations was described. In order to focus a laser beam on a desired transistor, novel test circuit structures using selectively metal-covered transistors were proposed. Photocurrent induced upset failures were successfully observed in fabricated CMOS SRAM test cells. Results were discussed with SPICE simulations.

This paper presents a multi-band WCDMA receiver consisting of a multi-band low noise amplifier (LNA), a multi-band mixer and an inter-stage tunable notch filter. The notch filter is used to suppress Tx leakage, and 0.8–1.5 GHz (66%) of tuning range is achieved. The receiver achieves 33 and 30 dB conversion gain, 6.4 and 8 dB NF, 50 and 35.5 dBm IIP2, and -6 and -4.7 dBm IIP3 at 0.8 and 1.5 GHz, respectively. The power consumption is 121 mW from a 1.8-V power supply. The receiver is implemented in a 0.18-µm CMOS process.

In this paper, a capacitive-cross-coupling common-gate (CCC-CG) LNA using capacitive feedback is proposed to improve the noise figure (NF). In the conventional CCC-CG LNA, the transconductance gm is determined by the input-matching condition while a lager gm is required to improve NF. gm of the proposed LNA can be increased and NF can be improved by using the added capacitive feedback. The analytical calculation shows that the proposed LNA can perform better than the conventional CCC-CG LNA. In the measurement results using a 0.18-µm CMOS technology, the gain is 10.4–13.4 dB, NF is 2.7–2.9 dB at 0.8–1.8 GHz, and IIP3 is -7 dBm at 0.8 GHz. The power consumption is 6.5 mW with a 1.8-V supply.

This paper proposes a low-phase-noise ring-VCO-based frequency multiplier with a new subharmonic direct injection locking technique that only uses a time-delay cell and four MOS transistors. Since the proposed technique behaves as an exclusive OR and can double the reference signal frequency, it increases phase correction points and achieves low phase noise characteristic across the wide output frequency range. The frequency multiplier was fabricated by using 65 nm Si CMOS process. Measured 1-MHz-offset phase noise at 6.34 GHz with reference signals of 528 MHz was -119 dBc/Hz.

A 60 GHz direct conversion transceiver which employs amplitude/phase imbalance cancellation technique is newly proposed. By using the proposed technique, the receive path of the transceiver achieves less than 0.2 dB of amplitude error and less than 3 of phase error at 60 GHz bands over a 10 GHz bandwidth, which relaxes the design accuracy required for baluns used in the transceiver. It also employs a simple and fast calibration algorithm to adjust the locking range of the divide-by-3 injection locked divider in the phase locked loop. Fabricated in 90 nm CMOS technology, the transceiver achieves a low power consumption of 230 mW in transmit mode and 173 mW in receive mode. The output spectrum of 1.76 Gsps π/2-BPSK/QPSK modulation shows the excellent distortion and spurious suppression that meet the IEEE802.11ad draft standard.

In this paper, a wideband CMOS radio frequency (RF) front-end for digital video broadcasting-handheld (DVB-H) receiver is proposed. The RF front-end circuit is composed of a single-ended resistive feedback low noise amplifier (LNA), a single-to-differential amplifier, an I/Q down-conversion mixer with linearized transconductors employing third order intermodulation distortion cancellation, and a divide-by-two circuit with LO buffers. By employing a third order intermodulation (IMD3) cancellation technique and vertical NPN bipolar junction transistor (BJT) switching pair for an I/Q down-conversion mixer, the proposed RF front-end circuit has high linearity and low low-frequency noise performance. It is fabricated in a 0.18 µm deep n-well CMOS technology and draws 12 mA from a 1.8 V supply voltage. It shows a voltage gain of 31 dB, a noise figure (NF) lower than 2.6 dB, and an IIP3 of -8 dBm from 470 MHz to 862 MHz.

This paper presents the design and implementation of 0.9–4.8 GHz CMOS power amplifier (PA) with improved group delay variation and gain flatness at the same time for UWB transmitters. This PA design employs a two-stage cascade common source topology, a resistive shunt feedback technique and inductive peaking to achieve high gain flatness, and good input matching. Based on theoretical analysis, the main design factor for group delay variation is identified. The measurement results indicate that the proposed PA design has an average gain of 10.2 ± 0.8 dB while maintaining a 3-dB bandwidth of 0.57 to 5.8 GHz, an input return loss |S11| less than -4.4 dB, and an output return loss |S22| less than -9.2 dB over the frequency range of interest. The input 1 dB compression point at 2 GHz was -9 dBm while consumes 30 mW power from 1.5 V supply voltage. Moreover, excellent phase linearity (i.e., group delay variation) of ±125 ps was achieved across the whole band.

The design and measured results of a 120-GHz transmitter and receiver chipset are described in this paper. A simple on-off keying (OOK) modulation is adopted for low power consumption. The proposed transmitter and receiver are fabricated using 65-nm CMOS technology. The current consumption of the transmitter and receiver are 19.2 mA and 48.2 mA respectively. A 9-Gbps PRBS is successfully transferred from the transmitter to the receiver with the bit error rate less than 10-9.

A nanowatt-power-level automatic switch that combines a multi-Vth CMOS level converter and an LED as a photodiode has been developed for a sensor application. The level converter is a single-input latch-type multi-Vth CMOS circuit featuring the use of an enhancement-mode nMOSFET and a depletion-mode common-gate nMOSFET as a pair of driver transistors. The ED-CMOS level converter cuts the DC current path; and the LED, which generates a high output voltage under illumination, suppresses the leakage current of the depletion-mode common-gate nMOSFET in the ED-CMOS level converter, resulting in nanowatt-order power dissipation. To verify the effectiveness of the ED-CMOS circuit, a prototype level converter was fabricated on a 0.6-µm CMOS process and used in an automatic switch in a wireless mouse. The switch is composed of two LEDs, a current-mirror circuit, the level converter, and a power switch MOSFET. It senses when a hand grabs or releases the mouse and automatically turns the mouse on or off, respectively. The measured power dissipation of the mouse is 3 nW in the standby mode.

In this letter, we describe a low power current to time converter for wireless sensor networks. The proposed circuit has some advantages of high linearity and wide measurement range. From the evaluation using HSPICE with 0.18 µm CMOS device parameters, the output differential error for the input current variation is approximately 0.1 µs/nA under the condition that the current is varied from 100 nA to 500 nA. The idle power consumption is approximately zero.

An amplitude-redistribution technique – which improves phase-noise performance of millimeter (mm)-wave and quasi mm-wave cross-coupled VCOs by controlling the distribution of voltage swings on the oscillator nodes – is proposed. A 28-GHz VCO, fabricated in 0.13-µm CMOS technology, uses this technique and demonstrates low phase-noise performance of -112.9-dBc/Hz at 1-MHz offset and FOMT of -187.4-dBc/Hz, which is the highest FOMT so far reported in regard to CMOS VCOs operating above 25 GHz.