Quadrant silicon avalanche photodiodes (APDs) were fabricated by standard 0.18µm CMOS process, and were characterized at 405nm wavelength for Blu-ray applications. The size of each APD element is 50×50µm2. The dark current was 10pA at low bias voltage, and low crosstalk of about -80dB between adjacent APD elements was achieved. Although the responsivity is less than 0.1A/W at low bias voltage, the responsivity is enhanced to more than 1A/W at less than 10V bias voltage due to avalanche amplification. The wide bandwidth of 1.5GHz was achieved with the responsivity of more than 1A/W, which is limited by the capacitance of the APD. We believe that the fabricated quadrant APD is a promising photodiode for multi-layer Blu-ray system.

We report good responsivity at the wavelength of 1600nm in a Ge photodetector which had lateral p-i-n structure and butt-joint coupling structure based on conventional normal complementary metal oxide semiconductor processes. We experimentally verified the responsivity of 0.82A/W and 0.71A/W on the best and the worst polarizations, respectively. The butt joint lateral p-i-n structure is found to be polarization independent as compared with vertical ones. Although cut-off frequency was 2.3-2.4GHz at reverse bias 3V, clearly open eye diagram at 10Gbps was obtained with reverse bias over 12V. These results are promising as optical photodetectors to receive long wavelengths downstream signal wavelengths required for next-generation optical access network systems.

This paper presents a 27.5-29.6GHz fractional-N frequency synthesizer using reference and frequency doublers to achieve low in-band and out-of-band phase-noise for 5G mobile communications. A consideration of the baseband carrier recovery circuit helps estimate phase noise requirement for high modulation scheme. The push-push amplifier and 28GHz balun help achieving differential signals with low out-of-band phase noise while consuming low power. A charge pump with gated offset as well as reference doubler help reducing PD noise resulting in low in-band phase noise while sampling loop filter helps reduce spurs. The proposed synthesizer has been implemented in 65nm CMOS technology achieving an in-band and out-of-band phase noise of -78dBc/Hz and -126dBc/Hz, respectively. It consumes only a total power of 33mW. The jitter-power figure-of-merit (FOM) is -231dB which is the highest among the state of the art >20GHz fractional-N PLLs using a low reference clock (<200MHz). The measured reference spurs are less than -80dBc.

A 7GS/s complete-DDFS-solution featuring a two-times interleaved RDAC with 1.2Vpp-diff output swing was fabricated in 65nm CMOS. The frequency tuning and amplitude resolutions are 24-bits and 10-bits respectively. The RDAC includes a mixed-signal, high-speed architecture for random swapping thermometer coding dynamic element matching that improves the narrowband SFDR up to 8dB for output frequencies below 1.85GHz. The proposed techniques enable a 7 GS/s operation with a spurious-free dynamic range better than 32dBc over the full Nyquist bandwidth. The worst case narrowband SFDR is 42dBc. This system consumes 87.9mW/(GS/s) from a 1.2V power supply when the RSTC-DEM method is enabled, resulting in a FoM of 458.9GS/s·2(SFDR/6)/W. A proof-of-concept chip with an active area of only 0.22mm2 was measured in prototypes encapsulated in a 144-pins low profile quad flat package.

Compressed Sensing based CMOS image sensor (CS-CIS) is a new generation of CMOS image sensor that significantly reduces the power consumption. For CS-CIS, the image quality and data volume of output are two important issues to concern. In this paper, we first proposed an algorithm to generate a series of deterministic and ternary matrices, which improves the image quality, reduces the data volume and are compatible with CS-CIS. Proposed matrices are derived from the approximate DCT and trimmed in 2D-zigzag order, thus preserving the energy compaction property as DCT does. Moreover, we proposed matrix row operations adaptive to the proposed matrix to further compress data (measurements) without any image quality loss. At last, a low-cost VLSI architecture of measurements compression with proposed matrix row operations is implemented. Experiment results show our proposed matrix significantly improve the coding efficiency by BD-PSNR increase of 4.2 dB, comparing with the random binary matrix used in the-state-of-art CS-CIS. The proposed matrix row operations for measurement compression further increases the coding efficiency by 0.24 dB BD-PSNR (4.8% BD-rate reduction). The VLSI architecture is only 4.3 K gates in area and 0.3 mW in power consumption.

In this paper, the hardware architecture of a CORDIC-based Arithmetic Processor utilizing both angle recoding (ARD) CORDIC algorithm and scaling-free (SCFE) CORDIC algorithm is proposed and implemented in 180 nm CMOS technology. The arithmetic processor is capable of calculating the sine, cosine, sine hyperbolic, cosine hyperbolic, and multiplication function. The experimental results prove that the design is able to work at 100 MHz frequency and requires 12.96 mW power consumption. In comparison with some previous work, the design can be seen as a good choice for high-throughput low-energy applications.

A current mirror circuit is often used in Gm-cells and current amplifiers in order to obtain high linearity and high accurate current gain. However, it is expected that a threshold voltage mismatch between transistors pair in the current mirror affects these performances in recent scaled technologies. In this paper, negative effects caused by the mismatch in the current mirror are considered and a new calibration technique for the mismatch issues is proposed. In the current mirror without the mismatch, the high-linearity operation is provided by distortion canceling under the condition that the transistors have the same operating points. The threshold voltage mismatch disturbs the cancellation, therefore the distortion is appeared. In order to address the issue, a new calibration technique using a backgating effect is considered. This calibration can reduce the threshold voltage mismatch directly by controlling the body bias voltage with DACs. According to simulation results with Monte Carlo sampling in 65nm CMOS process, owing to the proposed calibration, the worst HD2 and HD3 are improved by 18.4dB and 11.6dB, respectively. In addition, the standard deviation of the current gain is reduced from 399mdB to 34mdB.

A continuous-time (CT) ΔΣ analog-to-digital converter (ADC) is a high resolution, wide-bandwidth ADC. A Gm-C filter is suitable for low power consumption and its frequency characteristics for a loop filter of the ADC. However, in practice, distortion generated in the Gm-C filter degrades the SNDR of the ADC, therefore a high-linearity Gm-cell with low power consumption is needed. A flipped voltage follower (FVF) Gm-cell is also used as a high-linearity Gm-cell, but distortion is caused by variation of drain-source voltage of its input transistors. In this paper, a new high-linearity Gm-cell is proposed for the CT ΔΣ ADC in order to address this problem. A proposed topology is a combination of a FVF and a cascode topology. The inserted transistors in the proposed Gm-cell behave as cascode transistors, therefore the drain-source voltage variation of the input transistor and a PMOS transistor for current source which causes distortion is suppressed. Simulation results show the proposed Gm-cell can realize the same linearity as the conventional Gm-cell with reducing 36% power consumption. A 20MHz-bandwidth CT ΔΣ ADC employing the proposed Gm-cells achieves SNDR of 72.4dB with power consumption of 6.8mW. Active area and FoM of the ADC are, respectively, 250μm × 220μm and 50fJ/conv.-step in 65nm CMOS process.

This letter presents a 12-bit column-parallel hybrid two-step successive approximation register/single-slope analog-to-digital converter (SAR/SS ADC) for CMOS image sensor (CIS). For achieving a high conversion speed, a simple SAR ADC is used in upper 6-bit conversion and a conventional SS ADC is used in lower 6-bit conversion. To reduce the power consumption, a comparator is shared in each column, and a 6-bit ramp generator is shared by all columns. This ADC is designed in SMIC 0.18µm CMOS process. At a clock frequency of 22.7MHz, the conversion time is 3.2µs. The ADC has a DNL of -0.31/+0.38LSB and an INL of -0.86/+0.8LSB. The power consumption of each column ADC is 89µW and the ramp generator is 763µW.

A fully integrated CMOS pulse transceiver with digital beam-formability for mm-wave active imaging is presented. The on-chip pulse transmitter of the transceiver includes an eight-element antenna array connected to eight pulse transmitters and a built-in relative pulse delay calibration system. The receiver employs a non-coherent detection method by using a FET direct-power detection circuit integrated with an antenna. The receiver dipole-patch antenna derives from the transmitter antenna but is modified with an on-chip DC-bias tail by shorting two arms of the dipole. The bandwidth of the receiver antenna with the DC-bias tail is designed to achieve 50.4-GHz in simulation and to cover the bandwidth of transmitter antennas. The output of the receiver antenna is connected to a resistive self-mixer followed by an on-chip low pass filter and then an amplifier stage. The built-in relative pulse delay calibration system is used to align the pulse delays of each transmitter array elements for the purpose of controlling the beam steering towards imaging objects. Both transmitter and receiver chips are fabricated in a 65-nm CMOS technology process. Measured pulse waveform of the receiver after relatively aligning all Tx's pulses is 0.91 mV (peak-peak) and 3-ns duration with a distance of 25mm between Rx and Tx. Beam steering angles are achieved in measurement by changing the digital delay code of antenna elements. Experimental results show that the proposed on-chip transceiver has an ability of digital transmitted-pulse calibration, controlling of beam-steeting, and pulse detection for active imaging applications.

Multiport SRAMs are frequently installed in network and/or telecommunication VLSIs to implement smart functions. This paper presents a high speed and low-power dual-port (i.e., 1W+1R two-port) SRAM macro customized for serial access operations. To reduce the wasted power dissipation due to subthreshold leakage currents, the supply voltage for 10T memory cells is lowered to 1 V and a power switch is prepared for every 64 word drivers. The switch is activated with look-ahead decoder-segment activation logic, so there is no penalty when selecting a wordline. The data I/O circuitry with a new column-based configuration makes it possible to hide the bitline precharge operation with the sensing operation in the read cycle ahead of it; that is, we have successfully reduced the read latency by a half clock cycle, resulting in a pure two-stage pipeline. The SRAM macro installed in a 4K-entry × 33-bit FIFO memory, fabricated with a 0.3-µm fully-depleted-SOI CMOS process, achieved a 500-MHz operation in the typical conditions of 2- and 1-V power supplies, and 25°C. The power consumption during the standby time was less than 1.0 mW, and that at a practical operating frequency of 400 MHz was in a range of 47-57 mW, depending on the bit-stream data pattern.

A 15GHz-band 4-channel transmit/receive RF core-chip is presented for high SHF wide-band massive MIMO in 5G. In order to realize small RF frontend for 5G base stations, both 6bit phase shifters (PS) and 0.25 dB resolution variable gain amplifiers (VGA) are integrated in TX and RX paths of 4-channels on the chip. A PS calibration technique is applied to compensate the error of 6bit PS caused by process variations. A common gate current steering topology with tail current control is used for VGA to enhance the gain control accuracy. The 15GHz-band RF core-chip fabricated in 65 nm CMOS process achieved phase control error of 1.9deg. rms., and amplitude control error of 0.23 dB. rms.

This paper presents a programmable wideband low pass filter (LPF) with Continuous-Time (CT)/Discrete-Time (DT) hybrid architecture. Unlike the conventional DT LPF, the proposed LPF eliminates sample & hold circuits, enabling to expand available bandwidth. The transfer function and the influence of the circuit imperfection are derived from CT/DT hybrid analysis. A prototype has been fabricated in 40 nm CMOS process. The proposed LPF achieves 2.5 GHz bandwidth by wideband equalization, which offers capacitance ratio (Cratio) and clock frequency (fCK) programmability. The proposed LPF occupies only 0.048 mm2 of active area.

In this paper, a 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter (VTC) in 28 nm CMOS is presented. A two-step transition inverter raises the Voltage-to-Time (VT) conversion gain to 100 ps/V which is >10x higher than a conventional current-starved inverter. The number of required inverter stages is reduced to 4 from 64, resulting in 1/8 conversion latency and thus 13.2 dB THD suppression at a 500 MHz full Nyquist frequency. A feedback control of the bias voltage in the two-step transition inverter suppresses PVT variations in the VT conversion gain. A test-chip measurement successfully demonstrates -52.5 dB THD at 500 MHz input frequency without sampling-and-hold circuits. Effective VT conversion range over +/-64 ps time difference is measured with 1.2 Vpp differential input while keeping high linearity of less than +/-0.53 LSB INL/DNL, which results in 1 ps/LSB conversion linearity. The proposed VTC occupies 84 um2 silicon area and consumes 0.18 mW at 1 GS/s.

In this paper, we present sub-1-V CMOS-based electrophoresis method for small-form-factor biomolecule manipulation that is contained in a microchip. This is the first time this type of device has been presented in the literature. By combining CMOS technology with electroless gold plating, the electrode pitch can be reduced and the required input voltage can be decreased to less than 1 V. We fabricated the CMOS electrophoresis chip in a cost-competitive 0.6 µm standard CMOS process. A sample/hold circuit in each cell is used to generate a constant output from an analog input. After forming gold electrodes using an electroless gold plating technique, we were able to manipulate red food coloring with a 0-0.7 V input voltage range. The results shows that the proposed CMOS chip is effective for electrophoresis-based manipulation.

60GHz wireless communication requires analog baseband circuits having a bandwidth of about 1GHz. This paper presents a wide bandwidth current-mode low pass filter technique which involves current amplifiers, resistors and capacitors. The proposed current-mode filter is obtained by replacing an integrator employing an op-amp with another integrator employing a current amplifier. With the low input impedance current amplifier having little variation of the input impedance, the proposed filter is expected to improve linearity and power efficiency. The proposed current amplifier which employs super source follower topology with complementary input is suitable for the filter because of its class AB operation. Although simulation results shows the conventional current amplifier which employs super source follower topology without the complementary input has 12Ω variation and 30Ω input impedance, the proposed current amplifier has 1Ω variation and 21Ω input impedance. A fourth order 1GHz bandwidth filter which involves the proposed current amplifiers is designed in a 65nm CMOS technology. The filter can achieve IIP3 of 1.3dBV and noise of 0.6mVrms with power consumption of 13mW under supply voltage of 1.2V according to simulation results with layout parasitic extraction models. Active area of the filter is 380μm×170μm.

This paper present a 20-GHz differential push-push voltage controlled oscillator (VCO) for 60-GHz frequency synthesizer. The 20-GHz VCO consists of a 10-GHz in-phase injection-coupled QVCO (IPIC-QVCO) with tail-filter and a differential output push-push doubler for 20-GHz output. The VCO fabricated in 65-nm CMOS technology, it achieves tuning range of 3 GHz from 17.5 GHz to 20.4 GHz with a phase noise of -113.8 dBc/Hz at 1 MHz offset. The core oscillator consumes up to 71 mW power and a FoM of -180.2 dBc/Hz is achieved.

In this paper, a nanopower supply-insensitive complementary metal-oxide-semiconductor (CMOS) unit threshold voltage (Vth) extractor circuit is proposed. It meets the contemporary industry demand for portable devices that operate with very low power consumption and small output sensitivity. An α times Vth (αVth) extractor is also described, in which α varies continuously. Both incremental and decremental αVth voltages are obtained. A post-layout simulation results using HSPICE with CMOS 0.18um process show that the proposed unit Vth extractor consumes 265nW of power given a 1.6V power supply. Sensitivity to temperature is 0.022%/°C ranging from 0°C to 100°C. Sensitivity to supply voltage is 0.027%/V.

The equivalent anisotropic material parameters of metal dummy fills in a CMOS chip were extracted through an eigenmode analysis of a unit-cell of a space filled with metal dummies. The validity of the parameters was confirmed by comparing the S-parameters of a parallel-plate waveguide with the metal dummy fills and their effective material properties. The validity of the effective material properties was also confirmed by using them in a simulation of an on-chip dipole antenna.

The mixer is a crucial circuit block in a WiMax system receiver. The performance of a mixer depends on three specifications: conversion gain, linearity and noise figure. Many mixers have been recently proposed for UWB and wideband systems; however, they either cannot achieve the high conversion gain required for a WiMAX system or they are prone to high power consumption. In this paper, a folded mixer with a high conversion gain is designed for a 2-11GHz WiMAX system and it can achieve a 20MHz IF output signal. From the simulation results, the proposed folded mixer achieves a conversion gain of 18.9 to 21.5dB for the full bandwidth. With a 0.2 to 4.4dBm IIP3, the NF is 13.5 to 17.6dB. The folded mixer is designed using TSMC 0.18µm CMOS technology. The core power consumption of the mixer is 11.8mW.