As great advancements have been made in CMOS process technology over the past 20 years, RF CMOS circuits operating in the microwave band have rapidly developed from component circuit levels to multiband/multimode transceiver levels. In the next ten years, it is highly likely that the following devices will be realized: (i) versatile transceivers such as those used in software-defined radios (SDR), cognitive radios (CR), and reconfigurable radios (RR); (ii) systems that operate in the millimeter-wave or terahertz-wave region and achieve high speed and large-capacity data transmission; and (iii) microminiaturized low-power RF communication systems that will be extensively used in our everyday lives. However, classical technology for designing analog RF circuits cannot be used to design circuits for the abovementioned devices since it can be applied only in the case of continuous voltage and continuous time signals; therefore, it is necessary to integrate the design of high-speed digital circuits, which is based on the use of discrete voltages and the discrete time domain, with analog design, in order to both achieve wideband operation and compensate for signal distortions as well as variations in process, power supply voltage, and temperature. Moreover, as it is thought that small integration of the antenna and the interface circuit is indispensable to achieve miniaturized micro RF communication systems, the construction of the integrated design environment with the Micro Electro Mechanical Systems (MEMS) device etc. of the different kind devices becomes more important. In this paper, the history and the current status of the development of RF CMOS circuits are reviewed, and the future status of RF CMOS circuits is predicted.

A CMOS detection procedure for ultra-wideband impulse radio (UWB-IR) communication system, employing Bi-Phase Shift Keying (BPSK) modulation scheme, is presented here. The chip was designed and fabricated in a 180 nm CMOS process and it requires a supply voltage of 1.8 V, with a die area of 0.01 mm2. A train of Gaussian Monocycle Pulses (GMP), modulated by a random data sequence of 1 Gb/s, has been detected successfully by the detector. Ability to process differential data without using conventional blocks like mixer, correlator etc. while consuming a very low power (3.8 pJ/bit for a data rate of 1 Gb/s) is the novelty of this work. The detection scheme employing a simple architecture with a noncoherent detection mechanism is well suited for UWB-IR communication system.

A novel resonant circuit consisting of transformer-based switched variable inductors and switched accumulation MOS (AMOS) varactors is proposed to realize an ultrawide tuning range voltage-controlled-oscillator (VCO). The VCO IC is designed and fabricated using 0.11 µm CMOS technology and fully evaluated on-wafer. The VCO exhibits a frequency tuning range as high as 92.6% spanning from 1.20 GHz to 3.27 GHz at an operation voltage of 1.5 V. The measured phase noise of -120 dBc/Hz at 1 MHz offset from the 3.1 GHz carrier is obtained.

A broadband balanced frequency doubler has been demonstrated in 0.25-µm SOI SiGe BiCMOS technology to operate from 22 GHz to 30 GHz. The measured fundamental frequency suppression of greater than 30 dBc is achieved by an internal low pass LC filter. In addition, a pair of matching circuits in parallel with the LO inputs results in high suppression with low input drive power. Maximum measured conversion gain of -6 dB is obtained at the input drive power as low as -1 dBm. The results presented indicate that the proposed frequency doubler can operate in broadband and achieve high fundamental frequency suppression with low input drive power.

High integration and low power operation of integrated circuits make noise sensitivity high. Therefore, it is important to reduce noise of circuits. A bias-offset transconductor is known as a linear transconductor. It is expected that noise sensitivity of the transconductor becomes higher due to improvement of linearity and reduction of power dissipation. This paper proposes a design method to reduce noise considering high linearity, reduction of power dissipation and small circuit size.

The accuracy of the comparator, which is often determined by its offset, is essential for the resolution of the high performance mixed-signal system. Various design efforts have been made to cancel or calibrate the comparator offset due to many factors like process variations, device thermal noise and input-referred supply noise. However, effective and simple method for offset cancel by applying additional circuits without scarifying the power, speed and area is always challenging. This work explores a dynamic offset control technique that employs charge compensation by timing control. The charge injection and clock feed-through by the latch reset transistor are investigated. A simple method is proposed to generate offset compensation voltage by implementing two source-drain shorted transistors on each regenerative node with timing control signals on their gates. Further analysis for the principle of timing based charge compensation approach for comparator offset control is described. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25 65 µm2 and consumes 380 µW. Circuits for offset control occupies 21% of the areas and 12% of the power consumption of the whole comparator chip.

A Q-enhanced 8th order CMOS active bandpass filter is presented employing a novel two-stage self-calibration technique. The proposed active filter shows the better out-band attenuation performance than other reported CMOS active bandpass filters. The proposed calibration method enables the stable filtering operation affected by neither the input power variation nor the strong interference power. It is fabricated using 65 nm CMOS process. The measured 3 dB bandwidth is 54 MHz at 2.37 GHz. The insertion loss is 2.9 dB and the out-band attenuation is 27.5 dB at 15 MHz offset frequency. The performance of the filter remains unchanged for 5% supply voltage variations.

A design methodology of Random Switching Logic (RSL) using CMOS standard cell libraries is proposed to counter power analysis attacks against cryptographic hardware modules. The original RSL proposed in 2004 requires a unique RSL-gate for random data masking and glitch suppression to prevent secret information leakage through power traces. In contrast, our new methodology enables to use general logic gates supported by standard cell libraries. In order to evaluate its practical performance in hardware size and speed as well as resistance against power analysis attacks, an AES circuit with the RSL technique was implemented as a cryptographic LSI using 130-nm and 90-nm CMOS standard cell library. From the results of attack experiments that used a million traces, we confirmed that the RSL-AES circuit has very high DPA and CPA resistance thanks to the contributions of both the masking function and the glitch suppressing function.

A resistive feedback-based inductive source degeneration ultra-wideband (UWB) CMOS low noise amplifier (LNA) with floating n-well terminals has been proposed. The resistive feedback technique provides wideband input matching with a small amount of noise degradation by reducing the quality factor of the input resonant circuit. In addition, all n-wells terminals of the triple-well RF transistors are connected to the supply voltage through high value resistors in order to reduce unwanted parasitic capacitances, leading to improvement of the RF performance of the proposed LNA. The proposed UWB LNA is implemented in 0.13 µm CMOS technology and all inductors are fully integrated in this work. Measurement results show a power gain of 10 dB from 3 GHz to 6 GHz, a minimum (maximum) noise figure of 2.3 dB (3.8 dB), an input return loss of better than -8 dB, and an input referred IP3 of -7 dBm. The fabricated chip consumes only 5 mA from a 1.5 V supply voltage.

An analytical method to make a trade off between tuning range and differential non-linearity (DNL) for a digitally controlled oscillator (DCO) is proposed. To verify the approach, a 12 bit DCO is designed, implemented in 0.18 µm CMOS technology, and tested. The measured DNL was -0.41 Least Significant Bit (LSB) without degrading other parameters which is the best so far among the reported DCOs.

This paper introduces a new hybrid CMOS-Nano circuit for efficient implementation of spiking neurons and spike-timing dependent plasticity (STDP) rule. In our spiking neural architecture, the STDP rule has been implemented by using neuron circuits which generate two-part spikes and send them in both forward and backward directions along their axons and dendrites, simultaneously. The two-part spikes form STDP windows and also they carry temporal information relating to neuronal activities. However, to reduce power consumption, we take the circuitry of two-part spike generation out of the neuron circuit and use the regular shaped pulses, after the training has been performed. Furthermore, the performance of the rule as spike-timing correlation learning and character recognition in a two layer winner-take-all (WTA) network of integrate-and-fire neurons and memristive synapses is demonstrated as a case example.

The paper demonstrates a novel multiple-valued logic (MVL) design using a three-peak negative differential resistance (NDR) circuit, which is made of several Si-based metal-oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT) devices. Specifically, this three-peak NDR circuit is biased by two switch-controlled current sources. Compared to the traditional MVL circuit made of resonant tunneling diode (RTD), this multiple-peak MOS-HBT-NDR circuit has two major advantages. One is that the fabrication of this circuit can be fully implemented by the standard BiCMOS process without the need for molecular-beam epitaxy system. Another is that we can obtain more logic states than the RTD-based MVL design. In measuring, we can obtain eight logic states at the output according to a sequent control of two current sources on and off in order.

A method to realize the fine frequency-tuning steps using tiny capacitors instead of Metal-Insulator-Metal (MIM) capacitors is proposed for a digitally controlled oscillator (DCO). The tiny capacitors are realized by the coplanar transmission lines which are arranged unsymmetrical in a 6 metal layers (M6) foundry of 0.18 µm CMOS technology. These transmission line based capacitors are designed by using electro-magnetic field simulator, and co-designed by using SPICE simulator. Finally, these capacitors are employed to design 15 bit DCO and fabricated the proposed DCO in 0.18 µm CMOS technology, and tested. The measured phase noise of DCO was -118.3 dBc/Hz (@1 MHz offset frequency), and the oscillating frequency tuned from 4.86 GHz to 5.36 GHz in the minimum frequency-tuning step of 18 kHz.

In this paper, a fully integrated 5 GHz voltage controlled oscillator (VCO) is presented. The VCO is designed with 0.18 µm silicon complementary metal oxide semiconductor (Si-CMOS) process. To achieve low phase noise, a novel varactors pair circuit is proposed to cancel effects of capacitance fluctuation that makes harmonic currents which increase phase noise of VCO. The VCO with the proposed varactor circuit has tuning range from 5.1 GHz to 6.1 GHz (relative value of 17.9%) and phase noise of lower than -110.8 dBc/Hz at 1 MHz offset over the full tuning range. Figure-of-merit-with-tuning-range (FOMT) of the proposed VCO is -182 dBc/Hz.

In this paper we present a study on the design optimization of voltage-controlled oscillators. The phase noise of LC-type oscillators is basically limited by the quality factor of inductors. It has been experimentally shown that higher-Q inductors can be achieved at higher frequencies while the oscillation frequency is limited by parasitic capacitances. In this paper, the minimum transistor size and the degradation of the quality factor caused by a switched-capacitor array are analytically estimated, and the maximum oscillation frequency of VCOs is also derived from an equivalent circuit by considering parasitic capacitances. According to the analytical evaluation, the phase noise of a VCO using a 65 nm CMOS is 2 dB better than that of a 180 nm CMOS.

A direct-conversion receiver integrated with the CMOS subharmonic frequency tripler (SFT) for V-band applications is designed, fabricated and measured using 0.13-µm CMOS technology. The receiver consists of a low-noise amplifier, a down-conversion mixer, an output buffer, and an SFT. A fully differential SFT is introduced to relax the requirements on the design of the frequency synthesizer. Thus, the operational frequency of the frequency synthesizer in the proposed receiver is only 20 GHz. The fabricated receiver has a maximum conversion gain of 19.4 dB, a minimum single-side band noise figure of 10.2 dB, the input-referred 1-dB compression point of -20 dBm and the input third order inter-modulation intercept point of -8.3 dB. It draws only 15.8 mA from a 1.2-V power supply with a total chip area of 0.794 mm0.794 mm. As a result, it is feasible to apply the proposed receiver in low-power wireless transceiver in the V-band applications.

This paper proposes a novel wideband voltage-controlled oscillator (VCO) for multi-band transceivers. The proposed oscillator has a core VCO and a tuning-range extension circuit, which consists of an injection-locked frequency divider (ILFD) and flip flop dividers. The two-stage differential ILFD generates quadrature outputs and realizes two, three, four, and six of divide ratio with very wide output frequency range. The proposed circuit is implemented by using a 90 nm CMOS process, and the chip area is 250200 µm2. The measured result achieves continuous frequency tuning range of 9.3 MHz-to-5.7 GHz (199%) with -210 dBc/Hz of figure-of-merit (FoMT).

In this paper an ultra high speed CNFET Full-Adder cell is presented. This design generates sum and carry-out signals via majority and majority-not gates which are implemented by CNFET buffer, CNFET inverter and input capacitors. Significant improvement in terms of speed and Power-Delay Product (PDP) is achieved.

This paper proposes a de-embedding method for on-chip S-parameter measurements at mm-wave frequency. The proposed method uses only two transmission lines with different length. In the proposed method, a parasitic-component model extracted from two transmission lines can be used for de-embedding for other-type DUTs like transistor, capacitor, inductor, etc. The experimental results show that the error in characteristic impedance between the different-length transmission lines is less than 0.7% above 40 GHz. The extracted pad model is also shown.

We propose a CMOS circuit that can be used as an equivalent to resistors. This circuit uses a simple differential pair with diode-connected MOSFETs and operates as a high-resistance resistor when driven in the subthreshold region of MOSFETs. Its resistance can be controlled in a range of 1-1000 MΩ by adjusting a tail current for the differential pair. The results of device fabrication with a 0.35-µm 2P-4M CMOS process technology is described. The resistance was 13 MΩ for a tail current of 10 nA and 135 MΩ for 1 nA. The chip area was 105 µm110 µm. Our resistor circuit is useful to construct many high-resistance resistors in a small chip area.