Rotate magnetic field can be used for ranging, especially the environment where electronic filed suffers a deep fading and attenuation, such as drilling underground. However, magnetic field is still affected by the ferromagnetic materials, e.g., oil casing pipe. The measurement error is not endurable for single measurement. In this paper, the Geometric Predicted Unscented Kalman Filtering (GP-UKF) algorithm is developed for rotate magnetic ranging system underground. With GP-UKF, the Root Mean Square Error (RMSE) can be suppressed. It is really important in a long range detection by magnetic field, i.e., more than 50 meters.

We consider the computation of r-th roots in finite fields. For the computation of square roots (i.e., the case of r=2), there are two typical methods: the Tonelli-Shanks method [7],[10] and the Cipolla-Lehmer method [3],[5]. The former method can be extended to the case of r-th roots with r prime, which is called the Adleman-Manders-Miller method [1]. In this paper, we generalize the Cipolla-Lehmer method to the case of r-th roots in Fq with r prime satisfying r | q-1, and provide an efficient computational procedure of our method. Furthermore, we implement our method and the Adleman-Manders-Miller method, and compare the results.

This paper proposes a novel approach for implementing an ultra-low-power voltage reference using the structure of self-cascode MOSFET, operating in the subthreshold region with a self-biased body effect. The difference between the two gate-source voltages in the structure enables the voltage reference circuit to produce a low output voltage below the threshold voltage. The circuit is designed with only MOSFETs and fabricated in standard 0.18-µm CMOS technology. Measurements show that the reference voltage is about 107.5 mV, and the temperature coefficient is about 40 ppm/, at a range from -20 to 80. The voltage line sensitivity is 0.017%/V. The minimum supply voltage is 0.85 V, and the supply current is approximately 24 nA at 80. The occupied chip area is around 0.028 mm2.

This paper clarifies the effects of metal wires placed around a Multiple-Input-Multiple-Output (MIMO) array with the goal of improving the channel capacity in near-field MIMO systems. Tests are performed on dual-dipole arrays with metal wires placed parallel to the dipoles. If the antenna elements have an appropriate half-power beamwidth (HPBW), there is a clear improvement in the channel capacity of the dual-dipole array. The metal wires are used to increase the multipath richness and the locations of the wires significantly impact the channel capacity. A significant increase in the channel capacity is observed even if only one metal wire is placed in the proper location. We verified the generality of applying a metal wire to improve the channel capacity and that the improvement in the channel capacity is approximately proportional to the number of metal wires.

The trench-gate type high-voltage (HV) MOSFET is one of the variants of HV-MOSFET, typically with its utility segments lying on a larger power consumption domain, compared to planar HV-MOSFETs. In this work, the HiSIM_HV compact model, originally intended for planar LDMOSFETs, was adequately extended to accommodate trench-gate type HV-MOSFETs. The model formulation focuses on a closed-form description of the current path in the highly resistive drift region, specific to the trench-gate HV-MOSFETs. It is verified that the developed compact expression can capture the conductivity in the drift region, which varies with voltage bias and device technology such as trench width. The notable enhancement of current drivability can be accounted for by the electrostatic control exerted by the trench gate within the framework of this model.

Distribution of current onset voltage (COV) as well as threshold voltage (VTH) and drain induced barrier lowering (DIBL) in MOSFETs fabricated by 65 nm technology is statistically analyzed. Although VTH distribution follows the normal distribution, COV and DIBL deviate from the normal distribution. It is newly found that COV follows the Gumbel distribution, which is known as one of the extreme value distributions. This result of statistical COV analysis supports our model that COV is mainly determined by the deepest potential valley between source and drain.

Many deterministic small-world network models have been proposed so far, and they have been proven useful in describing some real-life networks which have fixed interconnections. Search efficiency is an important property to characterize small-world networks. This paper tries to clarify how the search procedure behaves when random walks are performed on small-world networks, including the classic WS small-world network and three deterministic small-world network models: the deterministic small-world network created by edge iterations, the tree-structured deterministic small-world network, and the small-world network derived from the deterministic uniform recursive tree. Detailed experiments are carried out to test the search efficiency of various small-world networks with regard to three different types of random walks. From the results, we conclude that the stochastic model outperforms the deterministic ones in terms of average search steps.

In this paper, we present the validity and potential capacity of a modeling and simulation environment for the nonresonant plasmonic terahertz (THz) detector based on the silicon (Si) field-effect transistor (FET) with a technology computer-aided design (TCAD) platform. The nonresonant and “overdamped” plasma-wave behaviors have been modeled by introducing a quasi-plasma electron charge box as a two-dimensional electron gas (2DEG) in the channel region only around the source side of Si FETs. Based on the coupled nonresonant plasma-wave physics and continuity equation on the TCAD platform, the alternate-current (AC) signal as an incoming THz wave radiation successfully induced a direct-current (DC) drain-to-source output voltage as a detection signal in a sub-THz frequency regime under the asymmetric boundary conditions with a external capacitance between the gate and drain. The average propagation length and density of a quasi-plasma have been confirmed as around 100 nm and 11019/cm3, respectively, through the transient simulation of Si FETs with the modulated 2DEG at 0.7 THz. We investigated the incoming radiation frequency dependencies on the characteristics of the plasmonic THz detector operating in sub-THz nonresonant regime by using the quasi-plasma modeling on TCAD platform. The simulated dependences of the photoresponse with quasi-plasma 2DEG modeling on the structural parameters such as gate length and dielectric thickness confirmed the operation principle of the nonresonant plasmonic THz detector in the Si FET structure. The proposed methodologies provide the physical design platform for developing novel plasmonic THz detectors operating in the nonresonant detection mode.

In this paper, a high performance current latch sense amplifier (CLSA) with vertical MOSFET is proposed, and its performances are investigated. The proposed CLSA with the vertical MOSFET realizes a 11% faster sensing time with about 3% smaller current consumption relative to the conventional CLSA with the planar MOSFET. Moreover, the proposed CLSA with the vertical MOSFET achieves an 1.11 dB increased voltage gain G(f) relative to the conventional CLSA with the planar MOSFET. Furthermore, the proposed CLSA realizes up to about 1.7% larger yield than the conventional CLSA, and its circuit area is 42% smaller than the conventional CLSA.

In order to implement complementary logic function with L-shaped tunneling field-effect transistors (TFETs), current drivability and subthreshold swing (SS) need to be improved more. For this purpose, high-k material such as hafnium dioxide (HfO2) has been used as gate dielectric rather than silicon dioxide (SiO2). The effects of device parameters on performance have been investigated and the design of L-shaped TFETs has been optimized. Finally, the performance of L-shaped TFET inverters have been compared with that of conventional TFET ones.

A gate-all-around tunneling field-effect transistor (GAA TFET) with local high-k gate-dielectric and tunneling-boost n-layer based on silicon is demonstrated by two dimensional (2D) device simulation. Application of local high-k gate-dielectric and n-layer leads to reduce the tunneling barrier width between source and intrinsic channel regions. Thus, it can boost the on-current (Ion) characteristics of TFETs. For optimal design of the proposed device, a tendency of device characteristics has been analyzed in terms of the high-k dielectric length (Lhigh-k) for the fixed n-layer length (Ln-layer). The simulation results have been analyzed in terms of on- and off-current (Ion and Ioff), subthreshold swing (SS), and RF performances.

In this letter, we present an efficient method for high quality surface reconstruction from simulation data of smoothed particles hydrodynamics (SPH). For computational efficiency, instead of computing scalar field in overall particle sets, we only construct scalar field around fluid surfaces. Furthermore, an adaptive scalar field model is proposed, which adaptively adjusts the smoothing length of ellipsoidal kernel by a constraint-correction rule. Then the isosurfaces are extracted from the scalar field data. The proposed method can not only effectively preserve fluid details, such as splashes, droplets and surface wave phenomena, but also save computational costs. The experimental results show that our method can reconstruct the realistic fluid surfaces with different particle sets.

This paper presents a low-power LDPC decoder that can be used in Multimedia Wireless Sensor Networks. Three low power design techniques are proposed in the decoder design: a layered decoding algorithm, a modified Benes network and a modified memory bypassing scheme. The proposed decoder is implemented in TSMC 0.13 µm, 1.2 V CMOS process. Experiments show that when the clock frequency is 32 MHz, the power consumption of the proposed decoder is 38.4 mW, the energy efficiency is 53.3 pJ/bit/ite and the core area is 1.8 mm2.

A precoding design for double space-time block coding (STBC) system is investigated in this paper, i.e., the joint processing of STBC and dirty paper coding (DPC) techniques. These techniques are used for avoiding dual spatial streams interference and improving the transmitter diversity. The DPC system is interference free on multi-user or multi-antenna. The STBC transceiver can provide the transmit diversity. Due to the benefits about offered by the STBC and DPC techniques, we propose a new scheme called STBC-DPC system. The transceiver design involves the following procedures. First, the ordering QR decomposition of channel matrix and the maximum likelihood (ML) one-dimensional searching algorithm are proposed to acquire reliable performance. Next, the channel on/off assignment using the water filling algorithm, i.e., maximum capacity criterion, is proposed to overcome the deep fading channel problem. Finally, the STBC-DPC system with the modulus operation to limit the transmit signal level, i.e., the Tomlinson-Harashima precoding (THP) scheme, is proposed to achieve low peak-to-average power ratio (PAPR) performance. Simulation results confirm that the proposed STBC-DPC/THP with water filling ML algorithm can provide the low PAPR and excellent bit error rate (BER) performances.

We propose a novel acceleration scheme for Monte Carlo based statistical static timing analysis (MC-SSTA). MC-SSTA, which repeatedly executes ordinary STA using a set of randomly generated gate delay samples, is widely accepted as an accuracy reference. A large number of random samples, however, should be processed to obtain accurate delay distributions, and software implementation of MC-SSTA, therefore, takes an impractically long processing time. In our approach, a generalized hardware module, the STA processing element (STA-PE), is used for the delay evaluation of a logic gate, and netlist-specific information is delivered in the form of instructions from an SRAM. Multiple STA-PEs can be implemented for parallel processing, while a larger netlist can be handled if only a larger SRAM area is available. The proposed scheme is successfully implemented on Altera's Arria II GX EP2AGX125EF35C4 device in which 26 STA-PEs and a 624-port Mersenne Twister-based random number generator run in parallel at a 116 MHz clock rate. A speedup of far more than10 is achieved compared to conventional methods including GPU implementation.

Multiple-input multiple-output (MIMO) systems with antenna selection are practical in that they can alleviate the computational complexity at the receiver and achieve good reception performance. Channel correlation, not just carrier-to-noise ratio (CNR), has a great impact on reception performance in MIMO channels. We propose a practical receive antenna subset selection algorithm with reduced complexity that uses the condition number of the partial channel matrix and a predetermined CNR threshold. This paper describes the algorithm and its performance evaluation by both computer simulation and indoor experiments using a prototype receiver and received signals obtained in an actual mobile outdoor experiment. The results confirm that our proposed method provides good bit error rate performance by setting the CNR threshold properly.

In this paper, through extrinsic information transfer (EXIT) band chart analysis, an adaptive iterative decoding approach (AIDA) is proposed to reduce the iterative decoding complexity and delay for finite-length differentially encoded Low-density parity-check (DE-LDPC) coded systems with multiple-symbol differential detection (MSDD). The proposed AIDA can adaptively adjust the observation window size (OWS) of the MSDD soft-input soft-output demodulator (SISOD) and the outer iteration number of the iterative decoder (consisting of the MSDD SISOD and the LDPC decoder) instead of setting fixed values for the two parameters of the considered systems. The performance of AIDA depends on its stopping criterion (SC) which is used to terminate the iterative decoding before reaching the maximum outer iteration number. Many SCs have been proposed; however, these approaches focus on turbo coded systems, and it has been proven that they do not well suit for LDPC coded systems. To solve this problem, a new SC called differential mutual information (DMI) criterion, which can track the convergence status of the iterative decoding, is proposed; it is based on tracking the difference of the output mutual information of the LDPC decoder between two consecutive outer iterations of the considered systems. AIDA using the DMI criterion can adaptively adjust the out iteration number and OWS according to the convergence situation of the iterative decoding. Simulation results show that compared with using the existing SCs, AIDA using the DMI criterion can further reduce the decoding complexity and delay, and its performance is not affected by a change in the LDPC code and transmission channel parameters.

Process variation causes significant fluctuations in the timing performance of analog circuits, which causes a fraction of circuits to fail specifications. By testing the delay-performance, we can recognize the failed circuits during production testing. In this paper, we have proposed a low overhead and process tolerant delay evaluation circuit for built-in self test (BIST) function for analog differential circuits. This circuit contains a delay generation cell, an input differential signal generation cell, a delay matching cell, a sample-hold circuit, and a comparator. This circuit was implemented with 0.18 µm CMOS process. Simulation results over process variation, devices mismatch and layout parasitics, but without silicon measurement, show that the accuracy in delay detection is within 5 ps. A case study was done over a feed-forward equalizer (FFE). A typical use of this circuit is testing the delay of various FIR (Finite Impulse Response) filters.

A two-dimensional microarray of ten thousand (100100) chondrocyte-spheroids was successfully constructed with a 100-µm spacing on a micropatterned gold electrodes that were coated with poly(ethylene glycol) (PEG) hydrogels. The PEGylated surface as a cytophobic region was regulated by controlling the gel structure through photolithography. In this way, a PEG hydrogel was modulated enough to inhibit outgrowth of chondrocytes from cell adhering region in the horizontal direction. These structural control of PEG hydrogel was critical for inducing formation of three-dimensional chondrocyte condensations (spheroids) within 24 hours. We report noninvasive monitoring of the cellular functional change at the cell membrane using a chondrocyte-based field effect transistor (FET), which is based on detection of extracellular potential change induced as a result of the interaction between extracellular matrix (ECM) protein secreted from spheroid and substrate at the cell membrane. The interface potential change at the cell membrane/gate insulator interface can be monitored during the uptake of substrate without any labeling materials. Our findings on the time course of the interface potential would provide important information to understand the uptake kinetics for cellular differentiation.

Enocoro-128v2 is a lightweight stream cipher submitted to Cryptography Research and Evaluation Committees (CRYPTREC). In this paper, we first describe a side channel attack on Enocoro-128v2. We show that all secret key bytes of Enocoro-128v2 can be recovered by correlation power analysis, and it is shown by an experiment that around 6000 traces are needed to recover the secret key on SASEBO-GII (Side-channel Attack Standard Evaluation Board). We second propose a countermeasure with threshold implementation technique, which allows Enocoro-128v2 to be resistant against correlation power analysis as long as less than 105 traces are used.