Broadband optical access services are spreading throughout the world, and the number of fiber to the home (FTTH) subscribers is increasing rapidly. Telecom operators are constructing passive optical networks (PONs) to provide optical access services. Externally installed optical splitters for PONs are very important passive devices in optical access networks, and they must provide satisfactory performance as outdoor plant over long periods. Therefore, we calculate the failure rate of optical access networks and assign a failure rate to the optical splitters in optical access networks. The maximum cumulative failure rate of 18 optical splitters was calculated as 0.025 for an optical access fiber length of 2.1 km and a 20-year operating lifetime. We examined planar lightwave circuit (PLC) type optical splitters for use as outside plant in terms of their optical characteristics and environmental reliability. We confirmed that PLC type optical splitters have sufficient optical performance for a PON splitter and sufficient reliability as outside plant in accordance with ITU-T standard values. We estimated the lifetimes of three kinds of PLC type optical splitters by using accelerated aging tests. The estimated failure rate of these splitters installed in optical access networks was below the target value for the cumulative failure rate, and we confirmed that they have sufficient reliability to maintain the quality of the network service. We developed 18 optical splitter modules with plug and socket type optical connectors and optical fiber cords for optical aerial closures designed for use as outside plant. These technologies make it easy to install optical splitters in an aerial optical closure. The optical splitter modules have sufficient optical performance levels for PONs because the insertion loss at the commercially used wavelengths of 1.31 and 1.55 µm is less than the criterion established by ITU-T Recommendation G.671 for optical splitters. We performed a temperature cycling test, and a low temperature storage and damp heat test to confirm the long-term reliability of these modules. They exhibited sufficient reliability as regards heat and moisture because the maximum loss change was less than 0.3 dB.

This paper presents a high-speed, low-complexity VLSI architecture based on the modified Euclidean (ME) algorithm for Reed-Solomon decoders. The low-complexity feature of the proposed architecture is obtained by reformulating the error locator and error evaluator polynomials to remove redundant information in the ME algorithm proposed by Truong. This increases the hardware utilization of the processing elements used to solve the key equation and reduces hardware by 30.4%. The proposed architecture retains the high-speed feature of Truong's ME algorithm with a reduced latency, achieved by changing the initial settings of the design. Analytical results show that the proposed architecture has the smallest critical path delay, latency, and area-time complexity in comparison with similar studies. An example RS(255,239) decoder design, implemented using the TSMC 0.18 µm process, can reach a throughput rate of 3 Gbps at an operating frequency of 375 MHz and with a total gate count of 27,271.

Newly developed multi-layer inductors on GaAs three-dimensional MMICs are presented. We analyzed single-, double-, triple-, and quadruple-layer stacked-type inductors in what may be the first report on inductors on a GaAs MMIC with three or more layers. The performance of single- and multi-layer inductors was measured and calculated by electromagnetic field simulation. The multi-layer inductors produce 2-11 times higher inductance than that of conventional inductors on 2D-MMICs although they are the same size. This means that the proposed multi-layer inductors have smaller areas with the same inductances than those of conventional inductors. We also conducted the first-ever investigation of how performance factors such as parasitic capacitance, Q-factor, and self-resonant frequency are degraded in multi-layer inductors vis-a-vis those of conventional inductors. A microwave amplifier using multi-layer inductors was demonstrated and found to reduce circuit size by 20%.

In this paper, we study the problem of processing continuous range queries in a hierarchical wireless sensor network. Recently, as the size of sensor networks increases due to the growth of ubiquitous computing environments and wireless networks, building wireless sensor networks in a hierarchical configuration is put forth as a practical approach. Contrasted with the traditional approach of building networks in a "flat" structure using sensor devices of the same capability, the hierarchical approach deploys devices of higher-capability in a higher tier, i.e., a tier closer to the server. While query processing in flat sensor networks has been widely studied, the study on query processing in hierarchical sensor networks has been inadequate. In wireless sensor networks, the main costs that should be considered are the energy for sending data and the storage for storing queries. There is a trade-off between these two costs. Based on this, we first propose a progressive processing method that effectively processes a large number of continuous range queries in hierarchical sensor networks. The proposed method uses the query merging technique proposed by Xiang et al. as the basis. In addition, the method considers the trade-off between the two costs. More specifically, it works toward reducing the storage cost at lower-tier nodes by merging more queries and toward reducing the energy cost at higher-tier nodes by merging fewer queries (thereby reducing "false alarms"). We then present how to build a hierarchical sensor network that is optimal with respect to the weighted sum of the two costs. This allows for a cost-based systematic control of the trade-off based on the relative importance between the storage and energy in a given network environment and application. Experimental results show that the proposed method achieves a near-optimal control between the storage and energy and reduces the cost by 1.002 -- 3.210 times compared with the cost achieved using the flat (i.e., non-hierarchical) setup as in the work by Xiang et al.

This paper presents an enhanced dual-path delta-sigma analog-to-digital converter. Compared with other architectures, the enhanced architecture increases the noise shaping order without any instability problems and displays analog complexity equivalent to the multi-stage noise shaping architecture. Our delta-sigma converter is based on this new architecture. It employs not only doubly-differential structure to reduce common-mode errors in the system-level but also delayed-feed-in structure to mitigate the timing constraint of the feedback signal. Regarding the circuit implementation, the first-order enhancement of the quantization noise shaping is achieved via the use of a switched capacitor circuit technique. The circuit is incorporated into the active adder in a low-distortion structure. The supporting clock generation circuit that provides additional phases of clocks with the enhancement block is also implemented in the CMOS logic gates. A digital dynamic element matching circuit (i.e., segmented data-weighted-average circuit) is designed to reduce mismatch errors caused by the feedback DAC of modulator. A test chip, fabricated in a 0.18-µm CMOS process, provides a signal-to-noise+distortion ratio (SNDR) of 75-dB for a 1.0-MHz signal bandwidth clocked at 40-MHz. The 2nd harmonic is -101 dB and the 3rd harmonic is -94 dB when a -4.5-dB 100-kHz input signal is applied.

In the area of wireless sensor networks, the efficient spatial query processing based on the locations of sensor nodes is required. Especially, spatial queries on two sensor networks need a distributed spatial join processing among the sensor networks. Because the distributed spatial join processing causes lots of wireless transmissions in accessing sensor nodes of two sensor networks, our goal of this paper is to reduce the wireless transmissions for the energy efficiency of sensor nodes. In this paper, we propose an energy-efficient distributed spatial join algorithm on two heterogeneous sensor networks, which performs in-network spatial join processing. To optimize the in-network processing, we also propose a Grid-based Rectangle tree (GR-tree) and a grid-based approximation function. The GR-tree reduces the wireless transmissions by supporting a distributed spatial search for sensor nodes. The grid-based approximation function reduces the wireless transmissions by reducing the volume of spatial query objects which should be pushed down to sensor nodes. Finally, we compare naive and existing approaches through extensive experiments and clarify our approach's distinguished features.

Social bookmarking services have recently made it possible for us to register and share our own bookmarks on the web and are attracting attention. The services let us get structured data: (URL, Username, Timestamp, Tag Set). And these data represent user interest in web pages. The number of bookmarks is a barometer of web page value. Some web pages have many bookmarks, but most of those bookmarks may have been posted far in the past. Therefore, even if a web page has many bookmarks, their value is not guaranteed. If most of the bookmarks are very old, the page may be obsolete. In this paper, by focusing on the timestamp sequence of social bookmarkings on web pages, we model their activation levels representing current values. Further, we improve our previously proposed ranking method for web search by introducing the activation level concept. Finally, through experiments, we show effectiveness of the proposed ranking method.

We propose a simplified model of real-time joint source-channel coding, which can be used to adaptively determine the quality-optimal code rate of forward error correction (FEC) coding. The objective is to obtain the maximum video quality in the receiver, while taking time-varying packet loss into consideration. To this end, we propose a simplified model of the threshold set of the residual video packet loss rate (RVPLR). The RVPLR is the rate of residual loss of video packets after channel decoding. The threshold set is defined as a set of discrete RVPLRs in which the FEC code rate must be changed in order to maintain minimum distortion during increases or decreases of channel packet loss. Because the closed form of the proposed model is very simple and has one scene-dependent model parameter, a video sender can be easily implemented with the model. To train the scene-dependent model parameters in real-time, we propose a test-run method. This method accelerates the test-run while remaining sufficiently accurate for training the scene-dependent model parameters. By using the proposed model and test-run, the video sender can always find the optimal code rate on the fly whenever there is a change in the packet loss status in the channel. An experiment shows that the proposed model and test-run can efficiently determine the near-optimal code rate in joint source-channel coding.

Bag-of-Visual-Words representation has recently become popular for scene classification. However, learning the visual words in an unsupervised manner suffers from the problem when faced these patches with similar appearances corresponding to distinct semantic concepts. This paper proposes a novel supervised learning framework, which aims at taking full advantage of label information to address the problem. Specifically, the Gaussian Mixture Modeling (GMM) is firstly applied to obtain "semantic interpretation" of patches using scene labels. Each scene induces a probability density on the low-level visual features space, and patches are represented as vectors of posterior scene semantic concepts probabilities. And then the Information Bottleneck (IB) algorithm is introduce to cluster the patches into "visual words" via a supervised manner, from the perspective of semantic interpretations. Such operation can maximize the semantic information of the visual words. Once obtained the visual words, the appearing frequency of the corresponding visual words in a given image forms a histogram, which can be subsequently used in the scene categorization task via the Support Vector Machine (SVM) classifier. Experiments on a challenging dataset show that the proposed visual words better perform scene classification task than most existing methods.

We present a graph model and an ILP model for TAM design for transparency-based SoC testing. The proposed method is an extension of a previous work proposed by Chakrabarty with respect to the following three points: (1) constraint relaxation by considering test data flow for each core separately, (2) optimization of the cost for transparency as well as the cost for additional interconnect area simultaneously and (3) consideration of additional bypass paths. Therefore, the proposed ILP model can represent various problems including the same problem as the previous work and produce better results. Experimental results show the effectiveness and flexibility of the proposed method compared to the previous work.

The fast H∞ filter is developed by one of the authors, and its practical use in industries is expected. This paper derives a linear propagation model of numerical errors in the recursive variables of the fast H∞ filter, and then theoretically analyzes the stability of the filter. Based on the analyzed results, a numerical stabilization method of the fast H∞ filter is proposed with the error feedback control in the backward prediction. Also, the effectiveness of the stabilization method is verified using numerical examples.

Control Area Network (CAN) development began in 1983 and continues today. The forecast for annual world production in 2008 is approximately 65-67 million vehicles with 10-15 CAN nodes per vehicle on average . Although the CAN network is successful in automobile and industry control because the network provides low cost, high reliability, and priority messages, a starvation problem exists in the network because the network is designed to use a fixed priority mechanism. This paper presents a priority inversion scheme, belonging to a dynamic priority mechanism to prevent the starvation problem. The proposed scheme uses one bit to separate all messages into two categories with/without inverted priority. An analysis model is also constructed in this paper. From the model, a message with inverted priority has a higher priority to be processed than messages without inverted priority so its mean waiting time is shorter than the others. Two cases with and without inversion are implemented in our experiments using a probabilistic model checking tool based on an automatic formal verification technique. Numerical results demonstrate that low-priority messages with priority inversion have better expression in the probability in a full queue state than others without inversion. However, our scheme is very simple and efficient and can be easily implemented at the chip level.

Skyline query is very important because it is the basis of many applications, e.g., decision making, user-preference queries. Given an N-dimensional dataset D, a point p is said to dominate another point q if p is better than q in at least one dimension and equal to or better than q in the remaining dimensions. In this paper, we study a generalized problem of skyline query that, users are more interested in the details of the dominant relationship in a dataset, i.e., a point p dominates how many other points and whom they are. We show that the existing framework proposed in can not efficiently solve this problem. We find the interrelated connection between the partial order and the dominant relationship. Based on this discovery, we propose a new data structure, ParCube, which concisely represents the dominant relationship. We propose some effective strategies to construct ParCube. Extensive experiments illustrate the efficiency of our methods.

In this paper, a fully integrated 5 GHz voltage controlled oscillator (VCO) is presented. The VCO is designed with 0.18 µm silicon complementary metal oxide semiconductor (Si-CMOS) process. To achieve low phase noise, a novel varactors pair circuit is proposed to cancel effects of capacitance fluctuation that makes harmonic currents which increase phase noise of VCO. The VCO with the proposed varactor circuit has tuning range from 5.1 GHz to 6.1 GHz (relative value of 17.9%) and phase noise of lower than -110.8 dBc/Hz at 1 MHz offset over the full tuning range. Figure-of-merit-with-tuning-range (FOMT) of the proposed VCO is -182 dBc/Hz.

This paper proposes a de-embedding method for on-chip S-parameter measurements at mm-wave frequency. The proposed method uses only two transmission lines with different length. In the proposed method, a parasitic-component model extracted from two transmission lines can be used for de-embedding for other-type DUTs like transistor, capacitor, inductor, etc. The experimental results show that the error in characteristic impedance between the different-length transmission lines is less than 0.7% above 40 GHz. The extracted pad model is also shown.

This paper deals with a design problem of an observer-based robust stabilizing controller for a class of polytopic uncertain systems. The proposed controller synthesis differs from the conventional quadratic stabilization based on Lyapunov criterion and is based on the computation of the system's trajectory. In this paper, we show a LMI-based design method of the observer-based robust controller. The effectiveness of the proposed controller design approach is presented through a simple numerical example.

A low-voltage operational capability near 1 V along with low noise and distortion characteristics have been realized in a passive sigma-delta modulator. To achieve low-voltage operation, the dc voltage in signal paths in the switched-capacitor-filter section was set to be 0.2 V so that sufficient gate-to-source voltages were obtained for metal-oxide-semiconductor (MOS) switches in signal paths without using a gate-voltage boosting technique. In addition, the input switch that connects the input signal from the outside to the inside of an integrated circuit chip was replaced by a passive resistor to eliminate a floating switch, and gain coefficients in the feedback and input paths were modified so that the bias voltage of the digital-to-analog converter could be set to VDD and 0 V to easily activate MOS switches. As the signal swing becomes small under low-voltage operational circumstances, correlated double sampling was used to suppress the offset voltage and the 1/f noise that appeared at the input of a comparator. The modulator was fabricated using a standard CMOS 0.18-µm process, and the measured results show that the modulator realized 77 dB of dynamic range for 40 kHz of signal bandwidth with a 40 MHz sampling rate while dissipating 2 mW from a 1.1 V supply voltage.

This paper presents a wide range DCO with fine discrete tuning steps using a ΣΔ modulation technique for UWB frequency synthesizer. The proposed discrete tuning scheme provides a low effective frequency resolution without any degradation of the phase noise performance. With its three step discrete tunings, the DCO simultaneously has a wide tuning range and fine tuning steps. The frequency synthesizer was implemented using 0.13 µm CMOS technology. The tuning range of the DCO is 5.8-6.8 GHz with an effective frequency resolution of 3.9 kHz. It achieves a measured phase noise of -108 dBc/Hz at 1 MHz offset and a tuning range of 16.8% with the power consumption of 5.9 mW. The figure of merit with the tuning range is -181.5 dBc/Hz.

An arbitrary noise generator (ANG) is based on time-series charging of divided parasitic capacitance (TSDPC) and emulates power supply noise generation in a CMOS digital circuit. A prototype ANG incorporates an array of 32 x 32 6-bit TSDPC cells along with a 128-word vector memory and occupies 2 x 2 mm2 in a 65 nm 1.2 V CMOS technology. Digital noise emulation of functional logic cores such as register arrays is demonstrated with chip-level waveform monitoring at power supply, ground, as well as substrate nodes.

In this paper, an ultra low power analog front-end for EPCglobal Class 1 Generation 2 RFID tag is presented. The proposed RFID tag removes the need for high frequency clock and counters used in conventional tags, which are the most power hungry blocks. The proposed clock-free decoder employs an analog integrator with an adaptive current source that provides a uniform decoding margin regardless of the data rate and a link frequency extractor based on a relaxation oscillator that generates frequency used for backscattering. A dual supply voltage scheme is also employed to increase the power efficiency of the tag. In order to improve the tolerance of the proposed circuit to environmental variations, a self-calibration circuit is proposed. The proposed RFID analog front-end circuit is designed and simulated in 0.25 µm CMOS, which shows that the power consumption is reduced by an order magnitude compared to the conventional RFID tags, without losing immunity to environmental variations.