The dielectric breakdown strength of thermally grown silicon dioxide films was studied for MOS capacitors fabricated on silicon wafers that were intentionally contaminated with magnesium and zinc. Most of magnesium was detected in the oxide film after oxidation. Zinc, some of which evaporated from the surface of wafers, was detected only in the oxide film. The mechanism of the dielectric degradation is dominated by formation of metal silicates, such as Mg2SiO4 (Forsterite) and Zn2SiO4 (Wilemite). The formation of metal silicates has no influence on the generation lifetime of minority carriers, however, it provides the flat-band voltage shift less than 0.3 eV, and forces to increase the density of deep surface states with the zinc contamination.

Dislocation-free thin silicon layers are created on the three kinds of substrates such as oxide film, synthetic quartz glass and sapphire. They are bonded with silicon wafers using hydrogen bonding at room temperature but without any adhesive, and their bonding are changed into covalent bonding at elevated temperature. Thick (2 µm) silicon layers are first produced by surface grinding and polishing, and then thinned to 0.1 µm by plasma assisted chemical etching (PACE). A multiple repeated process of thinning the silicon layer and annealing the bonded silicon/quartz and silicon/sapphire interface is applied for tight bonding between a silicon wafer and a quartz wafer, and a silicon wafer and a sapphire wafer which have different thermal expansion coefficients. In case of bonding with sapphire, oxide with 200 in thickness plays an important role in the preventions of void formation and diffusion of interface contaminants into the silicon layer.

The theoretical modelling bandgap narrowing and percentage of ionized impurity atoms for uncompensated uniformly doped silicon containing conventional impurities (B, P, As, Sb) under thermodynamic-equilibrium conditions is presented. As distinct from existing approaches, this modelling is valid for impurity concentrations up to electrically-active-impurity-concentration limits and for the temperature range from 40 K up to 400 K. A relevant and efficient calculation software is proposed. The results of the calculations are compared with the results extracted by many authors from measurement data. A good agreement between these results is noted and possible reasons of some discrepancies are pointed out. The present modelling and software can be used for investigation of BJT charge-neutral regions as well as diffused or implanted resistors.

A simulation model for arsenic diffusion in polycrystalline silicon has been developed considering dynamic dopant clustering and polysilicon grain growth kinetics tightly coupled with dopant diffusion and segregation. It was assumed that the polysilicon layer consists of column-like grains surrounded by thin grain-boundaries, so that one dimensional description is permissible for dopant diffusion. The dynamic clustering model was introduced for describing arsenic activation in polysilicon grains, considering the solubility limit increase for arsenic in a polysilicon. For a grain-growth calculation, a previous formula was modified to include a local concentration dependence. The simulation results show that these effects are significant for a high dose implantation case.

Recently, high-dose implantation and low temperature annealing have become one of the key techniques in shallow junction formation. To fabricate shallow junction in quarter-micron CMOS VLSIs, it is well known being important to evaluate the transient enhanced diffusion (TED) of implanted dopants at low temperature furnace annealing, which is caused by the damages of implantation. We have newly studied the TED phenomena by a compact empirical method. This approach has merits of simplicity and better physical intuition, because we can use only minimal parameters to describe the TED phenomena. The other purpose of this work is to evaluate two-dimensional transient enhanced diffusion focusing on phosphorus implant and furnace annealing. Firstly, we defined effective diffusivity of the TED and determined extraction procedure of the model parameters. Number of the TED model parameters is minimized to two, which describe effective enhanced diffusivity and its activation energy. The parameters have been extracted from SIMS profile data obtained from samples which range 1013-31015 cm-2 and 850-950 for phosphorus implanted dose and annealing temperature, respectively. Simulation results with the extracted transient enhanced diffusion parameters show good agreements well with the SIMS data within 2% RMS-error. Critical doses for phosphorus enhanced diffusion have been determined in 950 annealing condition. No transient enhanced diffusion is observed at 950 under the implant dose of 11013 cm-2. Also the transient enhanced diffusivity is leveled off over the dose of 11014 cm-2. It is seen that the critical dose in TED phenomena might be temperature dependent to a certain extent. We have also verified that two-dimensional effect of the TED phenomena experimentally. Two-dimensional phosphorus n- layer is chosen to verify the simulation. It was concluded that the TED has isotropic nature in phosphorus n- diffusion formation.

A two-dimensional self-aligned silicide (SALICIDE) model has been developed using the general-purpose process simulator OPUS. A new two-dimensional growth model is proposed. Utilizing a newly-difined effective silicide thickness, the model accounts both silicon-diffusion and metal-diffusion limited silicide growth. Silicide lateral-growth along a sidewall spacer is successfully simulated for Si-diffusion limited silicide growth. Complete MOSFET process simulation with a SALICIDE process is demonstrated for the first time.

In order to develop silicon ICs operating up to above 450, Integrated Injection Logic (IIL) was chosen. A new structure for IIL was designed through experimental and theoretical studies of pn junctions, transistors, and IIL at high temperatures. A 5-µm design rule was used. The new IIL was fabricated by a specially developed combined process of ion implantation and low temperature epitaxy. The IIL was fully operational from room temperature to 454, and the output amplitude of a nine-stage ring oscillator was about 30 mV at 454. The minimum delay time of the IIL was 22 nsec at 454. The minimum power-delay product was 11 pJ and was one-third of that for IILs fabricated by 10-µm rule at 50.

A strictly nonblocking 88 matrix switch was designed and fabricated using silica-based planar lightwave circuits (PLC) on a silicon substrate. The average insertion loss was 11 dB in the TE mode and 11.3 dB in the TM mode. The average switch element extinction ratio was 16.7 dB in the TE mode and 17.7 dB in the TM mode. The accumulated crosstalk was estimated to be 7.4 dB in the TE mode and 7.6 dB in the TM mode. The driving power of the phase shifter required for switching was about 0.5 W and the polarization dependence of the switching power was 4%. The switching response time was 1.3 msec. The wavelength range with a switch extinction ratio of over 15 dB was 1.31 µm30 nm.

Phosphorus-doped amorphous or polycrystalline silicon can yield a conformal, low resistance, thermallystable plug for the high-aspect-ratio, sub-half-micron contactholes found in current development prototypes of future 64 and 256 Mega-bit DRAMs. When directly contacted to a silicide layer, however, such as WSix found in polycide gate or bit line metallization/contact structures, the outdiffusion of phosphorus from the doped-silicon layer into the silicide can occur, resulting in an increase in resistance. The characteristics of both the doped-silicon and WSix layers influence the outdiffusion. The grain size of the doped silicon appears to control diffusion at the WSix/doped-silicon interface while the transition of WSix from an as-deposited amorphous to a post-annealed polycrystalline state appears to help cause uniform phosphorus diffusion throughout the silicide film. The results of phosphorus pre-doping of the silicide to reduce the effects of outdiffusion are dependent upon the relative material volumes and interfacial areas of the layers. Due to the effectiveness of the TiN barrier layer/Ti contact layer structure used in Al-based contacts, Ti and TiN were evaluated on their ability to prevent phosphorus outdiffusion. Ti reacts easily with doped silicon and to some extent with WSix, thereby allowing phosphorus to outdiffuse through the TiSix into the overlying WSix. TiN, however, is very effective in preventing phosphorus outdiffusion and preserving polycide interface smoothness. A WSix/TiN/Ti metallization layer on an in situ-doped (ISD) silicon layer with ISD silicon-plugged contactholes yields contact resistances comparable to P+-implanted or non-implanted WSix layers on similar ISD layers/plugs for contact sizes greater than approximately 0.5 µm but for contacts of 0.4 µm or below the trend in contact resistance is lowest for the polycide with TiN barrier/Ti contact interlayers. A 20 nm-thick TiN film retains its barrier characteristics even after a 4-hour 850 anneal and is applicable to the silicide-on-doped-silicon structures of future DRAM and other ULSI devices.

Copper contamination behavior is studied, depending on the pH level, conductivity type P or N of a silicon substrate, and contamination method of copper. If the pH level of a copper containing solution is adjusted by using ammonia, copper atoms and ammonia molecules produce copper ion complexes. Accordingly, the amount of copper adsorption on the substrate surface is decreased. When N-type silicon substrates are contaminated by means of copper containing solutions, copper atoms on the surfaces diffuse into bulk crystal even at room temperature. But for P-type silicon substrates, copper atoms are transferred into bulk crystal only after high temperature annealing. In the case of silicon substrates contaminated by contact with metallic copper, no copper atom diffusion into bulk crystal was observed. The above mentioned copper contamination behavior can be explained by the charge transfer interaction of copper atoms with silicon substrates.

A glass precursor resist (GPR) is designed on the basis of an idea of conversion of organosilicon polymer to an inorganic substance by lithographic procedure. Developed chemical amplification resist system is composed of poly (di-t-butoxysiloxane) and a photoacid generator. It has a high sensitivity of 1.6 µC/cm2, a resolution of 0.2 µm and an extremely high O2-RIE durability compared with bottom resist. Exposed film changed into silicate glass, and it was confirmed by IR spectra.

Charges in buried oxide layers formed by wafer bonding were evaluated by capacitance-voltage (C-V) measurements. In this study, silicon-insulator-silicon (SIS) and metal-oxide-silicon (MOS) capacitors were fabricated on bonded wafers. For analyzing C-V curves of SIS structures, C-V simulation programs were developed. From the analysis, we conclude that approximately 2 1011/cm2 negative charges were distributed uniformly in the oxide. The effect of the experimental conditions during wafer bonding on generated charges in buried oxides is also discussed.

The self-checking design using 2-rail logic is one of the most popular design of self-shecking circuits. Even for a self-checking circuit, a test is necessary after VLSI chip or system fabrication, at each time the system is powered, and, under certain circumstances, in the case of maintenance. Therefore, an easy test scheme is desirable for that circuit. A new design method for a 2-rail logic combinational circuit is proposed, where stuck-open and sutck-on faults FETs can be easily detected. In the proposed circuit design, 4 FETs are added to each gate in a conventional 2-rail logic circuit. Two logical gates, DOR and DAND, are also added to the circuit as fault observing gates. Each test consists of a sequence of 3 input vectors, that is, a type of 3-pattern test, ti1ti2ti3. A test can be easily generated and fault observation is easy. Stuck-at fault and stuck-open fault on lines and almost all multiple faults can also be detected by the test. A gate construction method, test generation method, circuit construction method, and several discussions including gate delay increasing are presented.

Diffusion of phosphorus impurities from a polycrystalline silicon films into a silicon substrate was investigated as a function of the mean concentration of phosphorus in a polycrystalline silicon film at the first diffusion stage. We presented that good control of the redistribution of implanted phosphorus impurities was possible by optimizing the normalized dose, which is the value: [the total dose of phosphorus impurities]/[the polycrystalline silicon film thickness], in the case of samples both with and without an arsenic doped layers. In the range where the normalized dose was less than 1.52.51020 cm-3, deeper junctions were formed in samples with an arsenic doped layer. In the range where the normalized dose was more than 1.52.51020 cm-3, however, deeper junctions were formed in samples without any arsenic doped layer rather than in samples with an arsenic doped layer. These results mean that formation of the junction in the device structure where a high concentration phosphorus doped polysilicon layer is stacked on to the high concentration arsenic layer embeded at the surface of the substrate can be restricted by optimizing the normalized dose. Moreover, a trade-off relationship between suppressing phosphorus diffusion and maintaining low contact resistance against normalized doses was also observed.

The quality of polycrystalline silicon films and electrical characteristics of polycrystalline silicon gate metal-oxide-semiconductor (MOS) capacitors were investigated under various processing conditions, including phosphorus doping. The stresses observed in Si films deposited in the amorphous phase show complex behavior during thermal treatment. The stresses in as-deposited Si films are compressive. They change to tensile with annealing at 800, and to compressive after an additional annealing at 900. The kind of charges trapped in the SiO2 film during the negative constant current stress in Polycrystalline silicon gate MOS capacitors differ with the maximum process temperature. The trapped charges of samples annealed at 800 were negative, while those of samples annealed at 900 were positive.

Silicon nitride (SiNx) films have been deposited at lower substrate temperatures (500) by direct (without mercury-sensitization) photo-chemical vapor deposition (photo-CVD) using SiH4 and NH3 with a low-pressure mercury lamp. Films deposited at around 350 have a polymeric structure such as (Si(NH)2)n. Films deposited at 500 were close to stoichiometric Si3N4 with a slight amount of hydrogen. The refractive index and the dielectric constant of films deposited at 500 became almost equal to the values of thermally synthesized Si3N4. The resistivity was as high as 51016 Ωcm. The minimum density of interface states in Al/SiNx/Si MIS (metal-insulator-semiconductor) diodes was estimated to be 91010 cm-2eV-1 by a quasi-static capacitance-voltage measurement. For SiNx films deposited at 300, the density of interface states, which was in the order of 1011 cm-2eV-1 as deposited, decreased by a rapid thermal anneal after the deposition. For Al/SiNx/InP MIS diodes, it was 31011 cm-2eV-1 by high-frequency capacitance-voltage measurements. Direct photo-CVD for SiNx films is promising for low-temperature formation of a gate insulator.

Microcrystalline silicon embedded in silicon oxide has been prepared by means of a wet oxidation of porous silicon (PS) anodically produced from degenerate Si wafers in a HF solution. As the oxidation proceeded, optical absorptions of the PS specimen in the visible light region shifted obviously to the higher energy side. Visible light emission from the oxidized specimen was observed at room temperature with photoexcitation by a He-Cd laser while the as-prepared specimen emitted no visible lights. These results are discussed in relation to the quantum size effect of the microcrystalline silicon confined in the oxide matrix as well as visible emissions from as-prepared specimens produced from non-degenerate Si wafers.

After the intrinsic pulsed light illumination, a transient negative photoconductivity (TRANP) was observed in silicon doped with gold. The ambient temperature dependence of the TRANP-current was measured and compared with the simulated results obtained by solving rate equations. The temperature dependence of the peak value of the TRANP-current was in agreement with the simulated result. The activation energy of gold acceptor level obtained from the time constant in the recovery process was also consistent with the simulation. It was cleared from this result that the recovery process is dominated by the electron re-emission from gold acceptor level to the conduction band. It was concluded that the occurrence of the TRANP is well explained by using our model proposed before.

The mechanism of UV-excited dry cleaning using photoexcited chlorine radicals has been investigated for removing iron and aluminum contamination on a silicon surface. The iron and aluminum contaminants with a surface concentration of 1013 atoms/cm2 were intentionally introduced via an ammonium-hydrogenperoxide solution. The silicon etching rates from the Uv-excited dry cleaning differ depending on the contaminants. Fe and Al can be removed in the same manner. The removal of Fe and Al is highly temperature dependent, and is little affected by the silicon etching depth. Both Fe and Al on the silicon surface were completely removed by UV-excited dry cleaning at a cleaning temperature of 170, and were decreased by two orders of magnitude from the initial level when the surface was etched only 2 nm deep.

Plasmaless etching using ClF3 gas has been investigated on nitride films with different composition. For the sputter deposited and thermally grown silicon nitride films containing no hydrogen, the etch rate increases and the activation energy decreases with increase of the composition ratio of silicon to nitrogen between 0.75 and 1.3. This fact indicates that the etching is likely to proceed through the reaction between Si and ClF3. The native oxide on the silicon-nitride films can also be removed with ClF3 gas. Ultra-violet light irradiation from a low pressure mercury lamp remarkably accelerates the removal of the native oxide and the etch rate of the thermally grown silicon-nitride films. For the plasma deposited films, the etch rate is strongly accelerate with increasing hydrogen content in the films, but the activation energy hardly depends on the bounded hydrogen in the films, consistent with the results for Si etching.