The performance of multi-pulse pulse position modulation (MPPM) consisting of m slots and 2 pulses, denoted as (m, 2) MPPM, with imperfect slot synchronization is analyzed. The word error probability of (m, 2) MPPM in the presence of timing offset is analyzed, and the optimum symbol sets of (m, 2) MPPM minimizing the symbol error probability are assigned. When an unassigned symbol is detected, the receiver decodes the unassigned symbol as one of the assigned symbols having the highest probability of transition from the assigned symbol to the unassigned symbol. The bit error probability of (m, 2) MPPM in the presence of the timing offset is analyzed, and the bit error probability of (m, 2) MPPM is compared with that of PPM for the same transmission bandwidth and the same transmission rate. Moreover, the bit error probability of (m, 2) MPPM synchronized by a phase-locked loop (PLL) is also analyzed. It is shown that a word with two continuous pulses has better performance than a word with two separate pulses. It is also shown that when the timing offset occurs, and when the slot clock is synchronized by a PLL, (m, 2) MPPM performs better than PPM because (m, 2) MPPM has the optimum assigned symbols, and can decode detected words more correctly than PPM.

We compare interfaces of Nb/AlOx-Al/Nb and Nb/ZrOx-Zr/Nb junctions using secondary ion mass spectroscopy and cross-sectional transmission electron microscopy. We have clarified that an interface of the Nb/AlOx-Al/Nb junction is drastically different from that of the Nb/ZrOxZr/Nb junction. An adsorbed water vapor layer plays an important role in suppressing grain boundary diffusion between Nb and Al at the interface of the Nb/AlOxAl/Nb junction. In depositing Nb and Al at low power and cooling the substrate, it is important to control the formation of the adsorbed water vapor layer for fabricating Nb/AlOx-Al/Nb junctions exhibiting excellent current-voltage characteristics.

We have fabricated Nb/AlOx/Nb Josephson tunnel junctions by a sputtering apparatus with a load-lock system. This sputtering apparatus had the sub chamber for preparation and the main chamber for sputtering. The substrate temperature was confirmed to be kept less than 85 during Nb sputtering at the deposition rate of 1.18 nm/s for 7 minutes. The junctions that had 50µm50 µm area successfully showed the Vm value (the product of the critical current and the subgap resistance at 2 mV) as high as 50 mV at the current density of 100 A/cm2.

The magnitude of low frequency noise is studied in a Nb-(nanoconstrictions)-NbN system with adjustable current-voltage characteristics. We find that the magnitude of low frequency noise decreases sharply with increasing the subgap conductivity of the device. We suggest a qualitative explanation of this observation in terms of gradual build up of the nanoconstriction region by field assisted growth. The decrease of low frequency noise is related to the "cleanliness" of the system as measured by the amount of Andreev reflection-related conductivity. The scaling of the magnitude of low frequency noise with device resistance is also discussed.

This paper describes a new method for joining BiSrCaCuO superconductors (BSCCO) which realizes low microwave loss and high mechanical strength. This method consists of two processes. In the first the BSCCO surface is metallized with Ag and in the second a joint is formed by using thermally curable Ag paste. With this method, we obtained a joint with a loss of 0.3 dB around 1.1 GHz with the co-axial cavity techniques. Furthermore, the mechanical strength of the joint was greater than that of the BSCCO sample. From the results of DC resistance measurements and SEM observations, we attribute this good performance to the adhesion and continuity of the metallized Ag with the BSCCO surface.

High temperature superconductors are eminently suitable for use in high frequency devices because of their large energy gap. We fabricated weak link Josephson junctions connected in series. The junctions were constructed of EuBa2Cu3O7-x (EBCO) superconducting thin films on bicrystal MgO substrates. We measured their microwave broadband detection (video detection) characteristics. The responsivity (Sr) of the junctions depended on the bias current and their normal state resistance. The array junctions were effective in increasing normal state resistance. We obtained a maximum Sr of 22.6 [V/W].

The data retention characteristics of a Flash memory cell with a self-aligned double poly-Si stacked structure have been drastically improved by applying a bi-polarity write and erase technology which uses uniform Fowler-Nordheim tunneling over the whole channel area both during write and erase. It is clarified experimentally that the detrapping of electrons from the gate oxide to the substrate results in an extended retention time. A bi-polarity write and erase technology also guarantees a wide cell threshold voltage window even after 106 write/erase cycles. This technology results in a highly reliable EEPROM with an extended data retention time.

A method is described for constructing an interpolant to a set of arbitrary data points (xi, yi), i1, 2, , n. The constructed interpolant is a piecewise parametric cubic polynomial and satisfies C1 continuity, and it reproduces all parametric polynomials of degree two or less exactly. The experiments to compare the new method with Bessel method and spline method are also shown.

Linear lightwave networks (LLNs) are optical networks in which network nodes perform only linear operations on optical signals: power splitting, combining, and non-regenerative amplification. While previous efforts on LLNs assume only one fiber per link, we consider a multi-fiber linear lightwave network (M-LLN) architecture for telecommunications where switching exchanges are normally connected by multi-fiber cables. We propose a class of linear path (LP) allocation schemes for establishing optical paths in M-LLNs, and show that they have a better performance than those proposed for single-fiber LLNs. We show that M-LLNs can be implemented with commercially available components, and discuss the implementation issues in detail.

The progress of LSI technologies makes it possible to fabricate 256 MDRAM. However, it depends on the cost effectiveness of device fabrication that LSI memory can continue to be the technology driver or not. It is indispensable to make the device, process, and equipment as simple as possible for next generation LSI. For example, wavefront technologies in lithography, high energy ion implantation, and simple DRAM cell with SOI structure or high dielectric constant capacitor, are under development to satisfy both device performance improvement and process simplicity.

This paper describes CMOS embedded RAMs we developed utilizing 1.3 µm and 0.8 µm process technologies. Our goal was to achieve high-performance switching for digital communication systems. Because such switching can best be obtained by using high-performance embedded RAMs, we used 0.8 µm process technology and developed a 4 kW9 b single-port embedded RAM with 5 ns access time and 100 mW power dissipation during32 MHz operation, and a 1 kW9 b dual-port embedded RAM with 3.7 ns access time and 100 mW power dissipation during 40 MHz operation. We implemented these RAMs on one chip in developing three time-switch VLSIs, one buffer memory VLSI for ATM switches, and two cross-connect switch VLSIs.

Recently there has been considerable interest in coded modulation schemes that offer multiple levels of error protection. That is, constructions of (block or convolutional) modulation codes in which signal sequences associated with some message symbols are separated by a squared Euclidean distance that is larger than the minimum squared Euclidean distance (MSED) of the code. In this paper, the trellis structure of linear unequal-error-protection (LUEP) codes is analyzed. First, it is shown that LUEP codes have trellises that can be expressed as a direct product of trellises of subcodes or clouds. This particular trellis structure is a result of the cloud structure of LUEP codes in general. A direct consequence of this property of LUEP codes is that searching for trellises with parallel structure for a block modulation code may be useful not only in analyzing its structure and in simplifying its decoding, but also in determining its UEP capabilities. A basic 3-level 8-PSK block modulation code is analyzed under this new perspective, and shown to offer two levels of error protection. To illustrate the trellis structure of an LUEP code, we analyze a trellis diagram for an extended (64,24) BCH code, which is a two-level LUEP code. Furthermore, we introduce a family of LUEP codes based on the |||-construction, using Reed-Muller (RM) codes as component codes. LUEP codes in this family have the advantage of having a well known trellis structure. Their application in constructing LUEP-QPSK modulation codes is presented, and their error performance over an AWGN channel examined.

This paper describes a new method to determine the 3-D position coordinates of a Lambertian surface from four shaded images acquired with an actively controlled, nearby moving point light source. The method treats both the case when the initial position of the light source is known and the case when it is unknown.

Circuit techniques for realizing fast cycle time of DRAM are described. 1) A high-speed and high-efficiency word-line level Vpp supply can be obtained by a unique static CMOS double-boosted level generator (SCDB) which controls the Vpp charge supply gate. 2) A new write-control scheme eliminates the timing overhead of a read access time after write cycle in a fast page mode operation. 3) A floor plan that minimizes the load of signal paths by employing the lead-on-chip (LOC) assembly technique. These techniques are implemented in an address-multiplexed 16 Mbit CMOS DRAM using a 0.5-µm CMOS technology. A 31-ns RAS cycle time and a 19-ns fast page mode cycle time at Vcc3.3 V, and also even at Vcc1.8 V, a 53-ns RAS cycle time and a 32-ns fast page mode cycle time were achieved. This DRAM is applicable to battery-operated computing tools.

In this paper we propose a new algorithm for recognizing 3-D objects from 2-D images. The algorithm takes the multiple view approach in which each 3-D object is modeled by a collection of 2-D projections from various viewing angles where each 2-D projection is called an object model. To select the candidates for the object model that has the best match with the input image, the proposed algorithm computes the surface matching score between the input image and each object model by using Hopfield nets. In addition, the algorithm gives the final matching error between the input image and each candidate model by the error of the pose-transform matrix proposed by Hong et al. and selects an object model with the smallest matching error as the best matched model. The proposed algorithm can be viewed as a combination of the algorithm of Lin et al. and the algorithm of Hong et al. However, the proposed algorithm is not a simple combination of these algorithms. While the algorithm of Lin et al. computes the surface matching score and the vertex matching score berween the input image and each object model to select the candidates for the best matched model, the proposed algorithm computes only the surface matching score. In addition, to enhance the accuracy of the surface matching score, the proposed algorithm uses two Hopfield nets. The first Hopfield net, which is the same as that used in the algorithm of Lin et al., performs a coarse matching between surfaces of an input image and surfaces of an object model. The second Hopfield net, which is the one newly proposed in this paper, establishes the surface correspondences using the compatibility measures between adjacent surface-pairs of the input image and the object model. the results of the experiments showed that the surface matching score obtained by the Hopfield net proposed in this paper is much more useful for the selectoin of the candidates for the best matched model than both the sruface matching score obtained by the first Hopfield net of Lin et al. and the vertex matching score obtained by the second Hopfield net of Lin et al. and, as the result, the object recognition algorithm of this paper can perform much more reliable object recognition than that obtained by simply combining the algorithm of Lin et al. and the algorithm of Hong et al.

A capacitor-error-free SC voltage inverter with zero sensitivity to element-value variations is proposed. By virtue of the capacitor-error-free property, this SC voltage inverter is free from the capacitor mismatch. The performance of this SC voltage inverter has been confirmed from both the simulation and experiment.

A polarity-convertible driver is necessary as a basic component of several Josephson random access memories. This driver must be able to inject a current having positive or negative polarity into a load transmission line such as a word or bit line of the RAM. In this paper, we propose a resistor coupled Josephson polarity-convertible driver which is highly sensitive to input signals and has a wide operating margin. The driver consists of several Josephson junctions and several resistors. The input signal is directly injected to the driver through the resistors. The circuit design is discussed on the operating principle of the driver. The driver is fabricated by 1.5 µm Nb technology with Nb/AlOx/Nb Josephson junctions, two layer Nb wirings, an Nb ground plane, Mo resistors, and SiO2 insulators. The Nb/AlOx/Nb Josephson junctions are fabricated using technology refined for sub-micron size junctions. The insulators between wirings are formed using bias sputtering technique to obtain good step coverage. The driver circuit size is 53 µm34 µm. Measurements are carried out at 10 kHz to quasistatically test the polarity-convertible function and the operating margin of the driver. Proper polarity-convertible operation is confirmed for a large operating bias margin of 70% at a fairly small input current of 0.3 mA.

A distributive serial multi-bit parallel test scheme for large capacity DRAMs has been developed. The scheme, distributively and serially, extracts and compares the data from cells on a main word-line. This test scheme features a high parallel test bit number, little restriction on test patterns, and, with regard to cells and sense-amplifiers, the same operational margin as normal mode. In an experimental 256-Mb DRAM, the scheme successfully has achieved a 512-bit parallel test.

In this paper, trellis coded modulation with bandwidth expansion is examined. The proposed scheme is a modified Symbol-rate-increased TCM [3]-[5], which allows the bandwidth expansion ratio to be varied to an arbitrary value. The Symbol-rate-increased TCM has been shown to be a particular case of the proposed scheme. Simulation results have clarified that the proposed scheme achieves a significant improvement over an uncoded scheme in an AWGN channel.

We define the complexity and the distortion-complexity of an individual finite length string from a finite set. Assuming that the string is produced by a stationary ergodic source, we prove that the distortion-complexity per source letter and its expectation approximate arbitrarily close the rate-distortion function of this source as the length of the string grows. Furthermore, we apply this property to construct a universal data compression scheme with distortion.