This paper proposes an appearance-based novel descriptor for estimating head orientation. Our descriptor is inspired by the Weber-based feature, which has been successfully implemented for robust texture analysis, and the gradient which performs well for shape analysis. To further enhance the orientation differences, we combine them with an analysis of the intensity deviation. The position of a pixel and its intrinsic intensity are also considered. All features are then composed as a feature vector of a pixel. The information carried by each pixel is combined using a covariance matrix to alleviate the influence caused by rotations and illumination. As the result, our descriptor is compact and works at high speed. We also apply a weighting scheme, called Block Importance Feature using Genetic Algorithm (BIF-GA), to improve the performance of our descriptor by selecting and accentuating the important blocks. Experiments on three head pose databases demonstrate that the proposed method outperforms the current state-of-the-art methods. Also, we can extend the proposed method by combining it with a head detection and tracking system to enable it to estimate human head orientation in real applications.

Two-port SRAMs are frequently installed in gate-array VLSIs to implement smart functions. This paper presents a new high-density 10T CMOS base cell for gate-array-based two-port SRAM applications. Using the single base cell alone, we can implement a two-port memory cell whose bitline contacts are shared with the memory cell adjacent to one of two dedicated sides, resulting in greatly reduced parasitic capacitance in bitlines. To throw light on the total performance derived from the base cell, a plain two-port SRAM macro was designed and fabricated with a 0.35-µm low cost, logic process. Each of two 10-bit power-saved address decoders was formed with 36% fewer base cells by employing complex gates and a subdecoder. The new sense amplifier with a complementary sensing scheme had a fine sensitivity of 35 mVpp, and so we successfully reduced the required read bitline signal from 250 to 70 mVpp. With the macro with 1024 memory cells per bitline, the address access time under typical conditions of a 2.5-V power supply and 25°C was 4.0 ns (equal to that obtained with full-custom style design) and the power consumption at 200-MHz simultaneous operations of two ports was 6.7 mW for an I/O-data width of 1 bit.

Distributed power delivery is blooming in SoC power system because the fine-grained power management needs separate power sources to adjust each voltage island dynamically. In addition, dedicated power sources for critical circuit blocks can achieve better signal integrity. To extensively utilize the power modules when they are redundant and idle, this work applies the cooperation concept in SoC power management. The key controller is a mixed-signal estimator that executes the intelligent procedures, like real-time swap the power module depending on its loading and healthy condition, automatically configure the power system with phase interleaving, and support all the peripheral functions. To demonstrate the proposed concept, a prototype chip for voltage down-conversion is implemented. This chip contains four switched-inductor converter modules to emulate the cooperative power network. Each module is small therefore the power efficiency is not optimal for the heavy load. With the cooperation between power modules, the power efficiency is 88% for 300mA load, that is 8.5% higher than the single module operation.

A 10-bit 20-MS/s asynchronous SAR ADC with a meta-stability detector using replica comparators is proposed. The proposed SAR ADC with the area of 0.093mm2 is implemented using a 130-nm CMOS process with a 1.2-V supply. The measured peak ENOBs for the full rail-to-rail differential input signal is 9.6bits.

In this paper, we exploit MapReduce framework and other optimizations to improve the performance of hash join algorithms on multi-core CPUs, including No partition hash join and partition hash join. We first implement hash join algorithms with a shared-memory MapReduce model on multi-core CPUs, including partition phase, build phase, and probe phase. Then we design an improved cuckoo hash table for our hash join, which consists of a cuckoo hash table and a chained hash table. Based on our implementation, we also propose two optimizations, one for the usage of SIMD instructions, and the other for partition phase. Through experimental result and analysis, we finally find that the partition hash join often outperforms the No partition hash join, and our hash join algorithm is faster than previous work by an average of 30%.

The cycling wheelchair “Profhand” was developed in Japan as locomotion and lower limb rehabilitation device for hemiplegic subjects and elderly persons. Functional electrical stimulation (FES) control of paralyzed lower limbs enables application of the Profhand to paraplegic subjects as a rehabilitation device. In this paper, simplified muscle stimulation control for FES cycling with Profhand was examined for practical application, because cycling speed was low and not stable in our preliminary study and there was a difficulty in setting stimulation electrodes for the gluteus maximus. First, a guideline of target cycling speed to be achieved by FES cycling was determined from voluntary cycling with healthy subjects in order to evaluate FES cycling control. The cycling speed of 0.6m/s was determined as acceptable value and 1.0m/s was as ideal one. Then, stimulation to the gluteus maximus and that to the dorsiflexor muscles in addition to the quadriceps femoris were examined for simple FES cycling control for Profhand with healthy subjects. Stimulation timing was adjusted automatically during cycling based on muscle response time to electrical stimulation and cycling speed, which was shown to be effective for FES cycling control. Simple FES cycling control with Profhand removing stimulation to the gluteus maximus was found to be feasible. Stimulation to the dorsiflexor muscles with the quadriceps femoris was suggested to be effective for practical, simple FES cycling with Profhand in case of removing the gluteus maximus stimulation.

In this letter, we propose a novel texture descriptor that takes advantage of an anisotropic neighborhood. A brand new encoding scheme called Reflection and Rotation Invariant Uniform Patterns (rriu2) is proposed to explore local structures of textures. The proposed descriptor is called Oriented Local Binary Patterns (OLBP). OLBP may be incorporated into other varieties of Local Binary Patterns (LBP) to obtain more powerful texture descriptors. Experimental results on CUReT and Outex databases show that OLBP not only significantly outperforms LBP, but also demonstrates great robustness to rotation and illuminant changes.

In this study, we investigated Si(100), Si(110) and Si(111) surface flattening process utilizing sacrificial oxidation method, and its effect on Metal-Insulator-Semiconductor (MIS) diode characteristics. By the etching of the 100 nm-thick sacrificial oxide formed by thermal oxidation at 1100°C, the surface roughness of Si(100), Si(110) and Si(111) substrates were reduced. The obtained Root-Mean-Square (RMS) roughness of Si(100) was reduced from 0.22 nm (as-cleaned) to 0.07 nm (after etching), while it was reduced from 0.23 nm to 0.12 nm in the case of Si(110), and from 0.23 nm to 0.11 nm in the case of Si(111), respectively. Furthermore, it was found that time-dependent dielectric breakdown (TDDB) characteristics of MIS diodes for p-Si(100), p-Si(110) and p-Si(111) were improved with the reduction of Si surface RMS roughness.

Codebooks with good parameters are preferred in many practical applications, such as direct spread CDMA communications and compressed sensing. In this letter, an upper bound on the set size of a codebook is introduced by modifying the Levenstein bound on the maximum amplitudes of such a codebook. Based on an estimate of a class of character sums over a finite field by Katz, a family of codebooks nearly meeting the modified bound is proposed.

In quasi-synchronous frequency-hopping multiple access (QS-FHMA) systems, relative delays are allowed to vary in a domain around the origin. Under such condition, the low hit zone (LHZ) frequency-hopping sequence (FHS) set is more propitious than the conventional FHS set to be applied by the systems. In this paper, a construction based on the interleaving techniques of FHS set with LHZ is proposed. Besides the requirement for this constructed LHZ FHS set to get the optimality or the near optimality with respect to the Peng-Fan-Lee bound is also given. It turns out that the constructed LHZ FHS set has new parameters not covered in the literature, thus it does have great significance in practice.

An application of laser annealing process, which is used to form the shallow P-type Base junction for 20-V planar power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) is proposed. We demonstrated that the fabricated devices integrated with laser annealing process have superior electrical characteristics than those fabricated according to the standard process. Moreover, the threshold voltage variation of the devices applied by the new annealing process is effectively suppressed. This is due to that a uniform impurity distribution at the channel region is achieved by adopting laser annealing. Laser annealing technology can be applied as a reliable, effective, and advantageous process for the low-voltage power MOSFETs.

Content centric network (CCN) is conceived as a good candidate for a futuristic Internet paradigm due to its simple and robust communication mechanism. By directly applying the CCN paradigm in wireless multihop mobile ad hoc networks, we experience various kind of issues such as packet flooding, data redundancy, packet collisions, and retransmissions etc., due to the broadcast nature of the wireless channel. To cope with the problems, in this study, we propose a novel location-aware forwarding and caching scheme for CCN-based mobile ad hoc networks. Extensive simulations are performed by using simulator, named ndnSIM. Experiment results show that proposed scheme does better as compared to other schemes in terms of content retrieval time and the number of Interest retransmissions triggered in the network.

This paper proposes a high clutter-rejection technique for wall-penetrating frequency-modulated continuous-wave (FMCW) radar. FMCW radars are widely used, as they moderate the receiver saturation problem in wall-penetrating applications by attenuating short-range clutter such as wall-clutter. However, conventional FMCW radars require a very high-order high-pass filter (HPF) to attenuate short-range clutter. A delay-line (DL) is exploited to overcome this problem. Time-delay shifts beat frequencies formed by reflection waves. This means that a proper time-delay increases the ratio of target-beat frequency to clutter-beat frequency. Consequently, low-order HPF fully attenuates short-range clutter. A third-order HPF rejects more than 20 dB and 30 dB for clutter located at 6 m and 3 m, respectively, with a target located at 9 m detection with a 10,000 GHz/s chirp rate and a 28 ns delay-line.

Content oriented network is expected to be one of the most promising approaches for resolving design concept difference between content oriented network services and location oriented architecture of current network infrastructure. There have been proposed several content oriented network architectures, but research efforts for content oriented networks have just started and technical issues to be resolved are still remained. Because of content oriented feature, content data transmitted in a network can be reused by content requests from other users. Pervasive cache is one of the most important benefits brought by the content oriented network architecture, which forms interconnected caching networks. Caching network is the hottest research area and lots of research activities have been published. This paper surveys recent research activities for caching networks in content oriented networks, with focusing on important factors which affect caching network performance, i.e. content request routing, caching decision, and replacement policy of cache. And this paper also discusses future direction of caching network researches.

An application of laser annealing process, which is used to form the P-type Base junction for high-performance low-voltage power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), is proposed. An equivalent shallow-junction structure for P-Base junction with uniform impurity distribution is achieved by adopting green laser annealing of pulsed mode. Higher impurity activation for the shallow junction has been achieved by the laser annealing of melted phase than by conventional RTA (Rapid Thermal Annealing) of solid phase. The application of the laser annealing technology in the fabrication process of Low-Voltage U-MOSFET is also examined.

In recent years, the need to build solid state drive (SSD)-based cloud storage systems has been increasing in order to process the big data generated by lots of Internet of Things devices and Internet users. Because these kinds of cloud systems require high performance and reliable storage, the use of flash-based Redundant Array of Independent Disks (RAID) will increase. But in flash-based RAID storage, parity data must be updated with every data write operation, which can more quickly overwhelm SSD's lifespan. To solve this problem, this letter proposes parity data deduplication for OpenStack cloud storage systems using an all flash array. Unlike the traditional data deduplication method, it only removes parity data, which will be stored in the parity disks of the all flash array. Experiments show that the proposed parity data deduplication method can efficiently reduce the number of parity data write operations, compared to the traditional data deduplication method.

We developed a 300-GHz high gain amplifier MMIC in 75-nm InP high electron mobility transistor technology. We approached the issues with accurate characterization of devices to design the amplifier. The on-wafer through-reflect-line calibration technique was used to obtain accurate transistor characteristics. To increase measurement accuracy, a highly isolated structure was used for on-wafer calibration standards. The common source amplifier topology was used for achieving high gain amplification. The implemented amplifier MMIC exhibited a gain of over 25 dB in the 280-310-GHz frequency band.

This paper presents the design of a multiple-standard 1080 high definition (HD) video decoder on a mixed-grained reconfigurable computing platform integrating coarse-grained reconfigurable processing units (RPUs) and FPGAs. The proposed RPU, including 16×16 multi-functional processing elements (PEs), is used to accelerate compute-intensive tasks in the video decoding. A soft-core-based microprocessor array is implemented on the FPGA and adopted to speed-up the dynamic reconfiguration of the RPU. Furthermore, a mail-box-based communication scheme is utilized to improve the communication efficiency between RPUs and FPGAs. By exploiting dynamic reconfiguration of the RPUs and static reconfiguration of the FPGAs, the proposed platform achieves scalable performances and cost trade-offs to support a variety of video coding standards, including MPEG-2, AVS, H.264, and HEVC. The measured results show that the proposed platform can support H.264 1080 HD video streams at up to 57 frames per second (fps) and HEVC 1080 HD video streams at up to 52fps under 250MHz, at the same time, it achieves a 3.6× performance gain over an industrial coarse-grained reconfigurable processor for H.264 decoding, and a 6.43× performance boosts over a general purpose processor based implementation for HEVC decoding.

We have investigated PtHf silicide formation utilizing a developed PtHf-alloy target to realize low contact resistivity for the first time. A 20 nm-thick PtHf-alloy thin film was deposited on the n-Si(100) by RF magnetron sputtering at room temperature. Then, silicidation was carried out by rapid thermal annealing (RTA) system at 450-600°C/5 min in N2/4.9%H2 ambient. The PtHf-alloy silcide, PtHfSi, layers were successfully formed, and the Schottky barrier height (SBH) for electron of 0.45 eV was obtained by 450°C silicidation. Furthermore, low contact resistivity was achieved for fabricated PtHSi such as 8.4x10-8 Ωcm2 evaluated by cross-bridge Kelvin resistor (CBKR) method.

In this paper, we propose a channel-unaware algorithm to suppress the narrowband interference (NBI) for the time synchronization, where multiple antennas are equipped at the receiver. Based on the fact that the characteristics of synchronization signal are different from those of NBI in both the time and spatial domain, the proposed algorithm suppresses the NBI by utilizing the multiple receive antennas in the eigen domain of NBI, where the eigen domain is obtained from the time domain statistical information of NBI. Because time synchronization involves incoherent detection, the proposed algorithm does not use the desired channel information, which is different from the eigen domain interference rejection combining (E-IRC). Simulation results show, compared with the traditional frequency domain NBI suppression technique, the proposed algorithm has about a 2 dB gain under the same probability of detection.