Min Young CHUNG Dan Keun SUNG Kyung Pyo JUN
A timer-based scheme is proposed to manage information within terminal and service profiles for both incall registration/deregistration of UPT users and incall registration resets of terminal owners. In the timer-based scheme, information related to incall registration for a UPT user in a terminal profile is deleted due to a timer expiration without accessing the terminal profile. The performance of the timer-based scheme is compared with the previously proposed request-based scheme in terms of; 1) total cost and, 2) the number of terminal profile accesses per unit time for a terminal. Even though provision of the timer-based scheme requires the modification of incoming call delivery procedure, the timer-based scheme can reduce both the total cost and the number of terminal profile accesses compared to the previously proposed request-based scheme.
Do-Jong KIM Yong-Woon PARK Dong-Jo PARK
The structural characteristics of clusters are investigated in the partitioning process. Two partition functions, which show opposite properties around the optimal cluster number, are found and a new cluster validity index is presented based on the combination of these functions. Some properties of the index function are discussed and numerical examples are presented.
ChangYoon LEE Mitsuo GEN Way KUO
In this paper, we examine an optimal reliability assignment/redundant allocation problem formulated as a nonlinear mixed integer programming (nMIP) model which should simultaneously determine continuous and discrete decision variables. This problem is more difficult than the redundant allocation problem represented by a nonlinear integer problem (nIP). Recently, several researchers have obtained acceptable and satisfactory results by using genetic algorithms (GAs) to solve optimal reliability assignment/redundant allocation problems. For large-scale problems, however, the GA has to enumerate a vast number of feasible solutions due to the broad continuous search space. To overcome this difficulty, we propose a hybridized GA combined with a neural-network technique (NN-hGA) which is suitable for approximating optimal continuous solutions. Combining a GA with the NN technique makes it easier for the GA to solve an optimal reliability assignment/redundant allocation problem by bounding the broad continuous search space by the NN technique. In addition, the NN-hGA leads to optimal robustness and steadiness and does not affect the various initial conditions of the problems. Numerical experiments and comparisons with previous results demonstrate the efficiency of our proposed method.
Shoji OTAKA Takafumi YAMAJI Ryuichi FUJIMOTO Hiroshi TANIMOTO
A direct conversion receiver IC including an on-chip balun, an I/Q mixer, a variable gain amplifier and a 90 phase-shifter is fabricated in a Bi-CMOS technology with 15 GHz transition frequency (fT). This paper demonstrates that cascaded connection of an on-chip balun and a double balanced mixer as the I/Q mixer is effective to achieve a low DC offset and a low second-order distortion, on the basis of both careful examination of the mixer behavior and measurement. Input-referred DC offset voltage of less than 300 µV and spurious free dynamic range (SFDR) of over 67 dB are obtained by measurement. The IC consumes 52 mA from 2.7 V power supply voltage. The die size is 3 mm 3 mm.
Kenichi OKADA Hidetoshi ONODERA
The variabilities of device characteristics are usually regarded as a normal distribution. If we consider the variabilities over the whole wafer, however, they cannot be expressed as a normal distribution due to the existence of global systematic component. We propose a statistical model, characterizing the global systematic component according to the distance from the center of the wafer, which can express the variabilities over the whole wafer statistically.
SungEun JO Sang Woo KIM Jin Soo LEE
This paper provides a normalized Iterative Feedback Tuning (IFT) method that assures the boundedness of the gradient vector estimate (ρ) and the Hessian matrix estimate without the assumption that the internal signals are bounded. The proposed method uses the unbiased Gauss-Newton direction by the addition of the 4-th experiment. We also present blended control criteria and a PID-like controller as new design choices. In examples, the normalized IFT method results in a good convergence although the internal signal or the measurement noise variance is large.
Kazuhiro TAKAYA Yuji MAEDA Nobuo KUWABARA
2.4-GHz-band mid-speed (1- to 2-Mbit/sec) wireless LAN systems are being widely used in offices and factories. Electromagnetic interference can occur between these systems because they use the same frequency range. In this paper, we investigate the characteristics of the interference between wireless LAN systems that use direct-sequence (DS) systems and frequency-hopping (FH) systems. The interference characteristics were measured for three DS systems and one FH system that meet the IEEE 802.11 and RCR standards and that use different modulation methods. Our results indicate that throughput depends on the system and the modulation method. We have also developed a model that can be used to calculate the interference characteristics between DS and FH systems by considering the bandwidth of their transmission signals, the dwell time of the FH system, and the time that the DS system needs to transmit a data frame. We used this model to calculate the bit error rate (BER) characteristics of the systems used in our experiment, and the results indicate that BER characteristics depend on the modulation method. The throughput characteristics of the systems used in our experiment were also calculated, and agreed with the experiment results within +/- 5 dB. The throughput characteristics of wireless LAN systems based on IEEE 802.11 were also calculated when the signal level was higher than the receiver noise level. The results show that FH systems require a D/U ratio about 7 or 8 dB higher than the ratio required in DS systems because the parameters in the standard differ between FH and DS systems.
Mitsuji MUNEYASU Kouichiro ASOU Yuji WADA Akira TAGUCHI Takao HINAMOTO
This paper presents a new implementation of fuzzy filters for edge-preserving smoothing of an image corrupted by impulsive and white Gaussian noise. This filter structure is expressed as an adaptive weighted mean filter that uses fuzzy control. The parameters of this filter can be adjusted by learning. Finally, simulation results demonstrate the effectiveness of the proposed technique.
Hongku KANG Hyunjae KIM Wooncheol HWANG Kiseon KIM
We evaluate the BER performance of the OFDM system with the one-tap equalizer bank under the two-ray multipath channel with the frequency offset by the simple Gaussian analysis method and by a proposed modified Gaussian analysis method. The proposed analysis method considers two adjacent inter-channel interferences, separately, and models the other inter-channel interferences as a Gaussian noise. It is shown that the proposed analysis method affords much closer results to the simulations than those by the simple Gaussian analysis method, when the frequency offset exists.
Hitoshi YOSHINO Hiroshi SUZUKI
This paper describes the results of a series of laboratory experiments for performance evaluations of our proposed Maximum Likelihood Sequence Estimation (MLSE) based interference canceller, the Interference Canceling Equalizer (ICE), which can cancel both co-channel interference (CCI) and inter-symbol interference (ISI). To verify the feasibility of ICE for the Japanese cellular communications system, a standard of which has been released under the name of Personal Digital Cellular (PDC) system, a prototype system was constructed using 27 TI TMS320C40 Digital Signal Processor (DSP) chips. The ICE prototype works in real-time on the PDC air interface, major specifications of which are π/4 QDPSK 21 k symbols/s 3-channel time-division multiple-access (TDMA). Two-branch diversity reception is used to enhance the signal detection performance of ICE. In the experiments, BER performances were evaluated using the prototype system. Under a single-path Rayleigh fading and a single CCI condition, the ICE receiver attains the BER of less than 310-2 with the negative values of the average CIR: for fD = 5 Hz and 40 Hz, the average CIR more than -20 dB and -10 dB, respectively. Under a double-path Rayleigh fading and a single CCI condition, the ICE receiver attains the BER of less than 1.510-2 with the negative values of the average CIR: for fD = 5 Hz and 40 Hz, the average CIR more than -20 dB and -10 dB, respectively. The laboratory test results suggest that the ICE receiver has potential for system capacity enhancement.
Dugin LYU Hirohito SUDA Fumiyuki ADACHI
The reverse-link of the DS-CDMA cellular system requires transmit power control (TPC) and diversity reception. This paper develops the expression of the received signal-to-interference ratio (SIR), and evaluates the outage probability using the Monte Carlo simulation to obtain the link capacity. The link capacities with received signal strength (SS)-based TPC and SIR-based TPC are compared. This paper investigates the required maximum and minimum transmit powers and the capacity gain of the SIR-based TPC over SS-based TPC as well as the effect of the diversity reception on the link capacity and transmit power. The reverse-link capacity is compared with the forward-link capacity to check the balance of capacities between both links.
The transmission S-parameter, S21, between dipole elements on a rectangular finite ground plane is calculated by the MoM with planar-segments in the horizontally and vertically polarized configurations. Supposed a 1/10 scaling, the frequency range is selected 0.15-0.8 GHz. The size of the finite ground plane is 40 cm 100 cm. The dipole-element length is 18.8 cm (half-wavelength at 0.8 GHz). The distance between dipole elements is 30 cm. The results are compared to the calculated results with the conventional MoM-GTD hybrid method and also the measured results with a TRL-calibrated network analyzer. It makes clear that the MoM-GTD hybrid method is not applicable to a small ground plane in the vertically polarized configuration. The results calculated by the MoM with planar-segments agree well to the measured results both in the horizontal and vertical polarizations. The results show that the size of the finite ground plane for the vertical polarization should be much larger than for the horizontal polarization.
It is well known that based on the structure of a transversal filter, the RLS equaliser provides the fastest convergence in stationary environments. This paper addresses an adaptive transversal equaliser which has the potential to provide more faster convergence than the RLS equaliser. A comparison is made with respect to computational complexity required for each update of equaliser coefficients, and computer simulations are demonstrated to show the superiority of the proposed equaliser.
Trong-Yen LEE Pao-Ann HSIUNG Sao-Jie CHEN
A novel Multi-Level Partitioning (MLP) technique taking into account real-world constraints for hardware-software partitioning in Distributed Embedded Multiprocessor Systems (DEMS) is proposed. This MLP algorithm uses a gradient metric based on hardware-software cost and performance as the core metric for selection of optimal partitions and consists of three nested levels. The innermost level is a simple binary search that allows quick evaluations of a large number of possible partitions. The middle level iterates over different possible allocations of processors (that execute software) to subsystems. The outermost level iterates over the number of processors and the hardware cost range. Heuristics are applied to each level to avoid the expensive exhaustive search. The application of MLP as a recently purposed Distributed Embedded System Codesign (DESC) methodology shows its feasibility. Comparisons between real-world examples partitioned using MLP and using other existing techniques demonstrate contrasting strengths of MLP. Sharing, clustering, and hierarchical system model are some important features of MLP, which contribute towards producing more optimal partition results.
Koichiro MINAMI Masayuki MIZUNO Hiroshi YAMAGUCHI Toshihiko NAKANO Yusuke MATSUSHIMA Yoshikazu SUMI Takanori SATO Hisashi YAMASHIDA Masakazu YAMASHINA
This paper describes a 1-GHz portable digital delay-locked loop (DLL) with 0.15-µm CMOS technology. There are three factors contributing to jitter in digital DLLs. One is supply-noise induced jitter, another is jitter caused by delay time resolution and phase step in the delay line, and the third is jitter caused by the sensitivity of the phase detector. In order to achieve a low jitter digital DLL, we have developed a master-slave architecture that achieves infinite phase capture ranges and low latency, a delay line that improves the delay time resolution, a phase step suppression technique and a dynamic phase detector with increased sensitivity. These techniques were used to fabricate a digital DLL with improved jitter performance. Measured results showed that the DLL successfully achieves 29-ps peak-to-peak jitter with a quiet supply and 0.2-ps/ mV supply sensitivity.
Masato SAITO Takaya YAMAZATO Masaaki KATAYAMA Akira OGAWA
We propose the analytical calculation method of average packet success probability of CDMA Slotted ALOHA systems, which derives accurate probability, and that is applicable to the system with any spreading codes and any amplitude distributions. In the method, we consider the bit-to-bit dependence of amplitude of signals, used spreading sequences, relative timing delays, and relative carrier phases. This bit-to-bit dependence is the case that the parameters above mentioned are constant for a slot time. By using the method to obtain the average packet success probability, we derive useful throughput performance of CDMA Slotted ALOHA systems on fading channel, and show that the normalized throughput becomes worse in the case of larger spreading factor.
Shigeki OBOTE Yasuaki SUMI Yoshio ITOH Yutaka FUKUI Masaki KOBAYASHI
Recently, in the modem, the spread spectrum communication system and the software radio, Digital Signal Processor type Squaring Loop (DSP-squaring-loop) is employed in the demodulation of Binary Phase Shift Keying (BPSK) signal. The DSP-squaring-loop extracts the carrier signal that is used for the coherent detection. However, in case the Signal to Noise Ratio (SNR) is low, the DSP-Phase Locked Loop (DSP-PLL) can not pull in the frequency offset and the phase offset. In this paper, we propose a DSP-squaring-loop that is robust against noise and which uses the adaptive notch filter type frequency estimator and the adaptive Band Pass Filter (BPF). The proposed method can extract the carrier signal in the low SNR environment. The effectiveness of the proposed method is confirmed by the computer simulation results.
For evaluating the output response fluctuation of the actual environmental acoustic system excited by arbitrary random inputs, it is important to predict a whole probability distribution form closely connected with many noise evaluation indexes Lx, Leq and so on. In this paper, a new type evaluation method is proposed by introducing lower and higher order type functional models matched to the prediction of the response probability distribution form especially from a problem-oriented viewpoint. Because of the non-negative property of the sound intensity variable, the response probability density function can be reasonably expressed in advance theoretically by a statistical Laguerre expansion series form. The system characteristic between input and output can be described by the regression relationship between the distribution parameters (containing expansion coefficients of this expression) and the stochastic input. These regression functions can be expressed in terms of the orthogonal series expansion. Since, in the actual environment, the observed output is inevitably contaminated by the background noise, the above regression functions can not be directly employed as the models for the actual environment. Fortunately, the observed output can be given by the sum of the system output and the background noise on the basis of additivity of intensity quantity and the statistical moments of the background noise can be obtained in advance. So, the models relating the regression functions to the function of the observed output can be derived. Next, the parameters of the regression functions are determined based on the least-squares error criteria and the measure of statistical independency according to the level of non-Gaussian property of the function of the observed output. Thus, by using the regression functions obtained by the proposed identification method, the probability distribution of the output reducing the background noise can be predicted. Finally, the effectiveness of the proposed method is confirmed experimentally too by applying it to an actual indoor-outdoor acoustic system.
Kunio UCHIYAMA Fumio ARAKAWA Yasuhiko SAITO Koki NOGUCHI Atsushi HASEGAWA Shinichi YOSHIOKA Naohiko IRIE Takeshi KITAHARA Mark DEBBAGE Andy STURGES
A 64-bit architecture for an embedded processor targeted for next-generation digital consumer products has been developed. It has dual-mode instruction sets and is optimized for high multimedia performance, provided by SIMD/floating-point vector instructions in 32-bit length ISA, and small code size, provided by a conventional 16-bit length ISA. Large register files, (6464b and 6432b), a split-branch mechanism, and virtual cache are also adopted in the architecture. A 714MIPS/9.6 GOPS/400 MHz processor core with the 64-bit architecture and a system LSI containing the core are developed using 0.15-µm technology. The LSI includes a 3.2 GB/sec high-bandwidth on-chip bus, a high-speed DRAM interface, a SRAM/Flash/ROM/Multiplexed-bus interface, and a 66 MHz PCI interface that provide the performance required for next-generation multimedia applications.
Kenji TOGURA Hiroyuki NAKASE Koji KUBOTA Kazuya MASU Kazuo TSUBOUCHI
We have proposed a current-cut switched-current matched filter (CC-SIMF) for direct-sequence code-division multiple-access (DS-CDMA). The 256-chip CC-SIMF can achieve low power consumption of less than 10 mW under high-speed operation of more than 16 Mcps. To reduce the current transfer error accumulation, we propose a parallel SIMF configuration. A 128-chip SIMF using 0.8-µm Complementally Metal Oxide Semiconductor (CMOS) process has been designed and fabricated. Optimization of the current memory cell structure has been described. The correlation operation at 16 Mcps has been obtained using a 128-chip orthogonal m-sequence. The code phase separation performance for path diversity has been clearly observed. The power consumption has been significantly reduced using the current-cut method.