A directly modulated LED or SLD (super luminescent diode) is attractive for low-cost lightwave systems such as access networks. This letter experimentally studies a directly modulated SLD followed by a gain-saturated semiconductor optical amplifier (SOA), and shows that the modulation rate is expanded in effect by the use of the gain-saturated SOA. This results from the shortened response time of the SLD due to the ASE light from the SOA and a level-equalizing effect in the gain-saturated SOA.

A reliable and automatic parameter extraction technique for DFB lasers is developed. The parameter extraction program which is named "LAPAREX" is able to determine many device parameters from a measured sub-threshold spectrum only, including gain- and index-coupling coefficients, and spatial phases of the grating at front and rear facets. Injection current dependence of coupling coefficients in a gain-coupled DFBlaser is observed, for the first time, by making use of it.

The operation of a novel all-optical wavelength converter based on directionally-coupled semiconductor optical amplifiers is described. Merits such as extinction enhancement and digital response are expected through a simple analytical model and a sophisticated transfer matrix method developed to take into account the spatial distributions of the optical power, carrier density, refractive index, propagation constant, and coupling coefficient along device. We fabricated devices operating at 1.55 µm band using an InGaAsP/InP material system and demonstrated successfully the static characteristics of wavelength conversion with the expected advantages. Devices are as small as 1.5 mm and do not need any active/passive integration step during fabrication.

Generating conditions of the optical feedback noise in self-pulsing lasers were experimentally examined. The noise charcteristics were determined by changing the operating power, the feedback distance and the feedback ratio for several types of self-pulsing lasers. The idea of the effective modulation index was introduced to evaluate the generating conditions in an uniform manner based on the mode competition theory. Validity of the idea was experimentally confirmed for generation of noise.

This paper describes the effectiveness of compact semiconductor optical amplifiers (SOAs) in the photonic transport system (PTS). Such amplifiers are small enough to permit high-density packaging. SOAs, having unsaturated signal gain of 10 dB and saturation output power of 10 dBm, can improve the Q-value by 3 over the SOA input power range of 10 dB. Within this range, the signal transport distance can be expanded from 360 km to 600 km by placing SOAs on individual optical channels in a PTS even though the amplified spontaneous emission (ASE) generated by individual SOAs is combined with the optical signals and delivered to the same output fiber. This result indicates that it is useful to employ compact SOAs in the PTS for enlarging the distances between nodes.

In this paper, an effective method of system modeling and dynamic scheduling to improve operation and control for the Back-End process of semiconductor manufacturing is developed by using Colored Timed Petri-Nets (CTPNs). The simulator of a CTPNs model was utilized to generate a new heuristic scheduling method with genetic algorithm(GA) which enables us to obtain the optimal values of the weighted delay time and standard deviation of lead time.

In a real-time system, it is required to reduce the response time to an interrupt signal, as well as the execution time of a Real-Time Operating System (RTOS). In order to satisfy this requirement, we have proposed a method of implementing some of the functionalities of an RTOS using hardware. Based on this idea, we have implemented a VLSI chip, called STRON (silicon TRON: The Realtime Operating system Nucleus), to enhance the performance of an RTOS, where the STRON chip works as a peripheral unit of any MPU. In this paper we describe the hardware architecture of the STRON chip and the performance evaluation results of the RTOS using the STRON chip. The following results were obtained. (1) The STRON chip is implemented in only about 10,000 gates when the number of each object (task, event flag, semaphore, and interrupt) is 7. (2) The task scheduler can execute within 8 clocks in a fixed period using the hardware algorithm when the number of tasks is 7. (3) Most of the basic µITRON system calls using the STRON chip can be executed in a fixed period of a few microseconds. (4) The execution time of a system call, measured by a multitask application program model, can be reduced to about one-fifth that in the case of the conventional software RTOS. (5) The total performance, including context switching, is about 2.2 times faster than that of the software RTOS. We conclude that the execution time of the part of the system call implemented by the STRON chip can almost be ignored, but the part of the interface software and context switching related to the architecture of a MPU strongly influence the total performance of an RTOS.

Silicon-based monolithic microwave integrated circuits (MMICs) present an interesting option for low-cost consumer wireless systems. SiGe/Si heterojunction bipolar transistors (HBTs) are a major driving force behind Si-based MMICs, because they offer excellent microwave performance without aggressive lateral scaling. This article reviews opportunities for receiver frontend components (low-noise amplifiers and mixers) using SiGe HBTs.

A high-frequency, low-noise silicon bipolar transistor that can be used in over-10 Gb/s optical communication systems and wireless communication systems has been developed. The silicon bipolar transistor was fabricated using self-aligned metal/IDP (SMI) technology, which produces a self-aligned base electrode of stacked layers of metal and in-situ doped poly-Si (IDP) by low-temperature selective tungsten CVD. It provides a low base resistance and high-cutoff frequency. The base resistance is reduced to half that of a transistor with a conventional poly-Si base electrode. By using the SMI technology and optimizing the depth of the emitter and the link base, we achieved the maximum oscillation frequency of 80 GHz, a minimum gate delay in an ECL of 11.6 ps, and the minimum noise figure of 0.34 dB at 2 GHz, which are the highest performances among those obtained from ion-implanted base Si bipolar transistors, and are comparable to those of SiGe base heterojunction bipolar transistors.

The growth behavior of copper particle on crystalline and amorphous silicon surfaces has been investigated. The study reveals that the growth behavior of copper particle depends on the substrate condition. When samples are intentionally contaminated in ultrapure water, both crystalline and amorphous silicon surfaces show no difference in their contamination levels. However, copper particles were not observed on an amorphous silicon surface except dipping in dilute CuCl2 solution. The copper concentration on an amorphous silicon surface after dipping in a 0.5% HF solution is similar to the level after contaminating in ultrapure water. The copper contamination level on a crystalline silicon surface, except from CuCl2 solution, decreased two orders of magnitude as compared with ultrapure water. The copper impurity level on crystalline silicon surface was reduced by two orders by cleaning in a sulfuric acid-hydrogen peroxide mixture. The sulfuric acid-hydrogen peroxide mixture cleaning was not effective on an amorphous silicon surface. When native oxide pre-existed on an amorphous silicon surface before contamination, however, the sulfuric acid-hydrogen peroxide mixture cleaning was effective for removing copper impurity. Our results suggest that copper contamination on an amorphous silicon surface have the characteristics of bonding directly with silicon and/or existing in the native oxide, in contrast with the situation on crystalline silicon surface. After contamination with 1000 ppm copper in CuF2 solution, the etch rate of an amorphous silicon film in a 0.5% HF solution was approximately one order of magnitude faster than that of crystalline silicon. This is attributed to the difference in crystalline structure between crystalline silicon and amorphous silicon.

A 1.55-µm hybrid integrated wavelength-converter module was fabricated using a two-channel spot-size converter integrated semiconductor optical amplifier (SS-SOA) on a planar-lightwave-circuit (PLC) platform. Clear eye opening and penalty-free wavelength conversion were obtained at 2.5-Gb/s modulation with a wide wavelength difference of 46 nm. The module showed good characteristics including low insertion loss (0.1 dB), and high conversion efficiency (-0.2 dB). It also showed stable wavelength conversion for as wide as a 13 temperature range.

After a short introduction to the different requirements to and techniques for wavelength conversion, focus is on cross-gain and cross-phase modulation in SOA based converters. Aspects like jitter accumulation, regeneration and conversion to the same wavelength is discussed. It is predicted that jitter accumulation can be minimised while also assuring a high extinction ratio by using a 9-10 dB ratio between the signal and CW power. Using this guideline simulations show that 20 cross-gain modulation converters can be cascaded at 10 Gbit/s with only 20 ps of accumulated jitter and an extinction ratio of 10 dB. The regenerative capabilities of the cross-phase converters are described and verified experimentally at 20 Gbit/s. By controlling the input power to an EDFA, the noise redistribution and improvement of the signal-to-noise ratio is demonstrated. In a similar experiment at 2.5 Gbit/s, the regeneration causes a reduction of the required input power to an in-line EDFA of 6 dB for a power penalty of 1 dB at a bit error rate of 10-9. If two converters are concatenated the power requirement is reduced 8 dB. Obviously, the power reduction allows for longer spans between in-line EDFAs. A simple scheme for regeneration without wavelength conversion is assessed at 2.5 Gbit/s resulting in 4.5 dB lower required EDFA input power. The scheme is characterised by a quasi-digital transfer function that is ideal for regeneration. A combination of cross-gain and cross-phase conversion is used to perform conversion to the same wavelength at 20 Gbit/s. The insertion penalty for this dual-stage converter is below 2 dB and is mainly caused by extinction ratio degradation from the cross-gain converter. Finally, a new device for all-optical wavelength conversion has been proposed and 2.5 Gbit/s operation has been simulated with good results.

After a short introduction to the different requirements to and techniques for wavelength conversion, focus is on cross-gain and cross-phase modulation in SOA based converters. Aspects like jitter accumulation, regeneration and conversion to the same wavelength is discussed. It is predicted that jitter accumulation can be minimised while also assuring a high extinction ratio by using a 9-10 dB ratio between the signal and CW power. Using this guideline simulations show that 20 cross-gain modulation converters can be cascaded at 10 Gbit/s with only 20 ps of accumulated jitter and an extinction ratio of 10 dB. The regenerative capabilities of the cross-phase converters are described and verified experimentally at 20 Gbit/s. By controlling the input power to an EDFA, the noise redistribution and improvement of the signal-to-noise ratio is demonstrated. In a similar experiment at 2.5 Gbit/s, the regeneration causes a reduction of the required input power to an in-line EDFA of 6 dB for a power penalty of 1 dB at a bit error rate of 10-9. If two converters are concatenated the power requirement is reduced 8 dB. Obviously, the power reduction allows for longer spans between in-line EDFAs. A simple scheme for regeneration without wavelength conversion is assessed at 2.5 Gbit/s resulting in 4.5 dB lower required EDFA input power. The scheme is characterised by a quasi-digital transfer function that is ideal for regeneration. A combination of cross-gain and cross-phase conversion is used to perform conversion to the same wavelength at 20 Gbit/s. The insertion penalty for this dual-stage converter is below 2 dB and is mainly caused by extinction ratio degradation from the cross-gain converter. Finally, a new device for all-optical wavelength conversion has been proposed and 2.5 Gbit/s operation has been simulated with good results.

A 1.55-µm hybrid integrated wavelength-converter module was fabricated using a two-channel spot-size converter integrated semiconductor optical amplifier (SS-SOA) on a planar-lightwave-circuit (PLC) platform. Clear eye opening and penalty-free wavelength conversion were obtained at 2.5-Gb/s modulation with a wide wavelength difference of 46 nm. The module showed good characteristics including low insertion loss (0.1 dB), and high conversion efficiency (-0.2 dB). It also showed stable wavelength conversion for as wide as a 13 temperature range.

Recent years have seen great advances in our understanding and modeling of the coupled diffusion of dopants and defects in silicon during integrated circuit fabrication processes. However, the ever-progressing shrinkage of device dimensions and tolerances leads to new problems and a need for even better models. In this review, we address some of the advances in the understanding of defect-mediated diffusion, focusing on the equations and parameters appropriate for modeling of dopant diffusion in submicron structures.

With the progress of LSI technology, the electronic device size is presently scaling down to the nano-meter region. In such an ultrasmall device, it is indispensable to take quantum mechanical effects into account in device modeling. In this paper, we first review the approaches to the quantum mechanical modeling of carrier transport in ultrasmall semiconductor devices. Then, we propose a novel quantum device model based upon a direct solution of the Boltzmann equation for multi-dimensional practical use. In this model, the quantum effects are represented in terms of quantum mechanically corrected potential in the classical Boltzmann equation.

Equipment simulation can provide valuable support in reactor design and process optimization. This article describes the physical and chemical models used in this technique and the current state of the art of the available software tools is reviewed. Moreover, the potential of equipment simulation will be highlighted by means of three recent examples from advanced quarter micron silicon process development. These include a vertical batch reactor for LPCVD of arsenic doped silicon oxide, a multi station tungsten CVD reactor, and a plasma reactor for silicon etching.

The full-band Monte Carlo technique is currently the most accurate device simulation method, but its usefulness is limited because it is very CPU intensive. This work describes efficient algorithms in detail, which raise the efficiency of the full-band Monte Carlo method to a level where it becomes applicable in the device design process beyond exemplary simulations. The k-space is discretized with a nonuniform tetrahedral grid, which minimizes the discretization error of the linear energy interpolation and memory requirements. A consistent discretization of the inverse mass tensor is utilized to formulate efficient transport parameter estimators. Particle scattering is modeled in such a way that a very fast rejection technique can be used for the generation of the final state eliminating the main cause of the inefficiency of full-band Monte Carlo simulations. The developed full-band Monte Carlo simulator is highly efficient. For example, in conjunction with the nonself-consistent simulation technique CPU times of a few CPU minutes per bias point are achieved for substrate current calculations. Self-consistent calculations of the drain current of a 60nm-NMOSFET take about a few CPU hours demonstrating the feasibility of full-band Monte Carlo simulations.

Design concepts and backgrounds of a 3-dimensional semiconductor process simulator are presented. It is designed to become a basis of developing semiconductor process models. An input language is designed to realize flexibly controlling simulation sequence, and its interpreter program is designed to accept external software to be controlled and to be integrated into a system. To realize data-exchanges between the process simulator and other software, a self-describing data-file format is designed and related program libraries are developed. A C++ class for solving drift-diffusion type partial-differential-equation in a three-dimensional space is developed.

We have improved the mechanical reliability of deep-submicron semiconductor devices by applying a simulation technique. Typical kinds of damages that reduce the reliability are dislocations in silicon substrates, delamination or cracking of thin films, and deterioration of electronic characteristics of devices. The mechanical stress that develops in device structures is caused by not only mismatches in thermal expansion coefficients among thin film materials but also intrinsic stress of thin films such as poly-silicon and silicides. Fine patterning by dry etching makes sharp edges and they also cause stress concentration and thus high stress. The manufacturing processes in which stress mainly develops are isolation, gate formation, and interconnect formation. We have developed methods for reducing the stress in each of the above-mentioned process. This stress reduction is very effective for highly reliable manufacturing. Finally, we clarify the effect of the residual stress in transistor structures on shift in the electronic characteristics of MOS transistors.