Passive optical network topology has been widely adopted in access networks due to its low-cost and yet flexible network structure. To further promote the passive optical networks, the cost reduction of optical modules is critical. Relatively expensive combination of a conventional index-coupled distributed feedback laser diode (IC-DFB-LD) and an optical isolator is commonly used for passive optical networks with transmission distance more than 30 km. Although gain-coupled DFB-LDs (GC-DFB-LD) have been widely investigated in the hope of eliminating the isolator in optical modules, their limited output power keeps them from practical use in passive optical networks. In this paper, we describe the development of 1.31 µm and 1.49 µm GC-DFB-LDs with high output power and optical feed back tolerance for isolator-free optical modules in access networks. The relative intensity noise (RIN) degradation was well suppressed below -120 dB/Hz at -8 dB optical feedback in the temperatures range from 0 to 85 from both 1.31 µm and 1.49 µm GC-DFB-LDs. Optical feedback tolerance of 1.31 µm and 1.49 µm GC-DFB-LDs were improved by more than 6 dB and 4 dB as compared with conventional IC-DFB-LDs. Dispersion power penalty after over 30 km transmission at 1.25 Gbps were achieved less than 0.3 dB and 0.7 dB under -15 dB optical feedback conditions. The proposed 1.31 µm GC-DFB-LD prototypes experimentally demonstrated 14 mW output power with over 5,000-hour operation at 85. Our devices are found to fully complying IEEE 802.3ah standard and seem to be promising for the low-cost optical modules in long-reach access network applications. The details of the device structure as well as transmission experiments are also reported.

This paper proposes a concept of a concurrent configuration of radio-frequency (RF) micromachined and micro-electro-mechanical-system (MEMS) devices. The devices are fabricated on an originally developed dielectric-air-metal (DAM) structure that suits for fabrication of various devices all together. The DAM structure can propose membrane-supported hollow elements embedded in a silicon wafer by creating cavities in it. Even though the devices have different cavity depths, they are processed by just one planarization. In addition, since the structure is worked only from the front side of the wafer, no flipping process as well as no wafer bonding process is required, and the fact realizes low-cost concurrent integration. As applications of the DAM structures, a hollow grounded co-planar waveguide, lumped element circuitries, and an MEMS switch are demonstrated.

In this paper, multiconductor transmission line (MTL) modelling is used to characterize the frequency response and dispersion of the low-voltage outdoor powerline channel. The analysis focuses on a single transmitter-to-receiver link and all the possible connection schemes associated with that link. By resorting to modal analysis, approximate analytical upper bounds of the channel frequency-response are derived for simplified but representative network configurations involving power cables with star-quad cross-section. Numerical solution of the MTL equations is used to validate the theoretical work and to show the dispersion of the channel frequency-responses, which results to be of the order of 20 dB.

We exploit a structural knowledge representation scheme called System Entity Structure (SES) methodology to represent and manage wafer failure patterns which can make a significant influence to FABs in the semiconductor industry. It is important for the engineers to simulate various system verification processes by using predefined system entities (e.g., decomposition, taxonomy, and coupling relationships of a system) contained in the SES. For better computational performance, given a certain failure pattern, a Pruned SES (PES) can be extracted by selecting the only relevant system entities from the SES. Therefore, the SES-based simulation system allows the engineers to efficiently evaluate and monitor semiconductor data by i) analyzing failures to find out the corresponding causes and ii) managing historical data related to such failures.

In this paper, a fully integrated 5 GHz voltage controlled oscillator (VCO) is presented. The VCO is designed with 0.18 µm silicon complementary metal oxide semiconductor (Si-CMOS) process. To achieve low phase noise, a novel varactors pair circuit is proposed to cancel effects of capacitance fluctuation that makes harmonic currents which increase phase noise of VCO. The VCO with the proposed varactor circuit has tuning range from 5.1 GHz to 6.1 GHz (relative value of 17.9%) and phase noise of lower than -110.8 dBc/Hz at 1 MHz offset over the full tuning range. Figure-of-merit-with-tuning-range (FOMT) of the proposed VCO is -182 dBc/Hz.

The programming characteristics of polysilicon-aluminum oxide-nitride-oxide-silicon (SANOS) nonvolatile memory devices with Al2O3 and SiO2 stacked tunneling layers were investigated. The electron and hole drifts in the Si3N4 layer were calculated to determine the program speed of the proposed SANOS devices. Simulation results showed that enhancement of the programming speed in SANOS was achieved by utilizing SiO2 and Al2O3 stacked tunneling layers.

We have fabricated VDP (van der Pauw) stress sensors on (111) silicon surfaces. This work focuses on a study of strain effects in VDP stress sensors, which were generally ignored in previous works, for the precise measurements of die stresses in electronic packages. The stress sensitivity was observed to be approximately 10% larger for p-type VDP sensors compared to n-type VDP sensors.

We designed and fabricated 4H-SiC PIN avalanche photodiodes (APD) for UV detection. The thickness of an intrinsic layer in a PIN structure was optimized in order to achieve the highest quantum efficiency at the wavelength of interest. The optimized 4H-SiC PIN APDs exhibited a maximum external quantum efficiency of >80% at the wavelength of 280 nm and a gain greater than 40000. Both electrical and optical characteristics of the fabricated APDs were in agreement with those predicted from simulation.

We report successful bottom-up synthesis of small diameter silicon nanowires (SiNWs) on SiO2 and Si3N4 surfaces. SiNWs with diameter comparable to the diameter of the Au nano-particles (10-20 nm) were grown on these surfaces, as well as on Si substrates which are commonly used for the nanowire growth. The growth temperature for obtaining a high density of SiNWs on SiO2 and Si3N4 substrates is higher (460-470) than that of the case of normal Si substrates (440). The growth on patterned substrates demonstrates that SiNWs can be selectively grown. Furthermore, the guided growth over metal structures is also shown to be possible. Selective growth of SiNWs on pre-patterned surfaces opens up the possibility of self-aligning SiNWs for the integration of complex device structures.

The electrical properties of poly-Si thin film transistors (TFTs) using rapid thermal annealing with various gate oxide thicknesses were studied in this work. It was found that Poly-Si TFT electrical characteristics with the thinnest gate oxide thickness after RTA treatment exhibits the largest performance improvement compared to TFT with thick oxide as a result of the increased incorporated amounts of the nitrogen and oxygen. Thus, the combined effects can maintain the advantages and avoid the disadvantages of scaled-down oxide, which is suitable for small-to-medium display mass production.

Initial growth of GaP on Si substrates using metalorganic vapor phase epitaxy was studied. Si substrates were exposed to PH3 preflow for 15 s or 120 s at 830 after they were preheated at 925. Atomic force microscopy (AFM) revealed that the Si surface after preflow for 120 s was much rougher than that after preflow for 15 s. After 1.5 nm GaP deposition on the Si substrates at 830, GaP islands nucleated more uniformly on the Si substrate after preflow for 15 s than on the substrate after preflow for 120 s. After 3 nm GaP deposition, layer structures were observed on a fraction of Si surface after preflow for 15 s. Island-like structures remained on the Si surface after preflow for 120 s. After 6 nm GaP deposition, the continuity of GaP layers improved on both substrates. However, AFM shows pits that penetrated a Si substrate with preflow for 120 s. Transmission electron microscopy of a GaP layer on the Si substrate after preflow for 120 s revealed that V-shaped pits penetrated the Si substrate. The preflow for a long time roughened the Si surface, which facilitated the pit formation during GaP growth in addition to degrading the surface morphology of GaP at the initial growth stage. Even after 50 nm GaP deposition, pits with a density on the order of 107 cm-2 remained in the sample. A 50-nm-thick flat GaP surface without pits was achieved for the sample with PH3 preflow for 15 s. The PH3 short preflow is necessary to produce a flat GaP surface on a Si substrate.

A precision in thickness recycling modus for a displays' color filter surface using a gear-form cathode in microelectrochemical removal is developed in the study. Through the precise removal processes of optical materials of nanostructure of Indium-Tin-Oxide crystallization, the optoelectronic semiconductor industry can effectively recycle defective products, and reducing production costs.

A flexible noise de-embedding method for on-wafer microwave measurements of silicon MOSFETs is presented in this study. We use the open, short, and thru dummy structures to subtract the parasitic effects from the probe pads and interconnects of a fixtured MOS transistor. The thru standard are used to extract the interconnect parameters for subtracting the interconnect parasitics in gate, drain, and source terminals of the MOSFET. The parasitics of the dangling leg in the source terminal are also modeled and taken into account in the noise de-embedding procedure. The MOS transistors and de-embedding dummy structures were fabricated in a standard CMOS process and characterized up to 20 GHz. Compared with the conventional de-embedding methods, the proposed technique is accurate and area-efficient.

The novel SCR-based (silicon controlled rectifier) device for ESD power clamp is presented in this paper. The proposed device has a high holding voltage and a high triggering current characteristic. These characteristics enable latch-up immune normal operation as well as superior full chip ESD protection. The device has a small area in requirement robustness in comparison to ggNMOS (gate grounded NMOS). The proposed ESD protection device is designed in 0.25 µm and 0.5 µm CMOS Technology. In the experimental result, the proposed ESD clamp has a double trigger characteristic, a high holding voltage of 4 V and a high trigger current of above 350 mA. The robustness has measured to HBM 8 kV (HBM: Human Body Model) and MM 400 V (MM: Machine Model). The proposed device has a high level It2 of 52 mA/ µm approximately.

This paper presents the analysis of multiconductor striplines with a finite strip thickness using the Fourier transform and mode-matching technique. The formulations, based on quasi-static approach, are developed to obtain simultaneous equations for the modal coefficients of the potential distributions between striplines. The residue calculus is applied to represent the potential distributions in convergent series form. The closed-form expressions for the self and mutual capacitances are developed analytically. Numerical computations are performed and their results show a good agreement with those of other methods.

We have developed InGaAs-based VCSELs operating around 1.1 µm for high-speed optical interconnections. By applying GaAsP barrier layers, temperature characteristics were considerably improved compared to GaAs barrier layers. As a result, 25 Gbps 100 error-free operation was achieved. These devices also exhibited high reliability. No degradation was observed over 3,000 hours under operation temperature of 150 and current density of 19 kA/cm2. We also developed VCSELs with tunnel junctions for higher speed operation. High modulation bandwidth of 24 GHz and a relaxation oscillation frequency of 27 GHz were achieved. 40 Gbps error-free operation was also demonstrated.

A data analysis technology of atomic force microscopy for atomically flat silicon surfaces has been developed. Atomically flat silicon surfaces composed of atomic terraces and steps are obtained on (100) orientation 200 mm diameter wafers by annealing in pure argon ambience at 1,200 for 30 minutes. Atomically flat silicon surfaces are lead to improve the MOS inversion layer mobility and current drivability of MOSFETs and to decrease the fluctuations in electrical characteristics of MOSFETs. It is important to realize the technology that evaluates the flatness and the uniformity of atomically flat silicon surfaces. The off direction angle is calculated by using two straight edge lines selected from measurement data. And the off angle is calculated from average atomic terrace width under assumption that height difference between neighboring terraces is equal to the step height, 0.135 nm, of (100) silicon surface. The analyzing of flatness of each terrace can be realized by converting the measurement data using the off direction angle and the off angle. And, the average roughness of each terrace is about 0.017-0.023 nm. Therefore, the roughness and the uniformity of each terrace can be evaluated by this proposed technique.

Three-dimensional integrated circuits (3-D ICs), i.e., stacked dies, can alleviate the interconnect problem coming with the decreasing feature size and increasing integration density, and promise a solution to heterogenous integration. The vertical connection, which is generally implemented by the through-the-silicon via, is a key technology for 3-D ICs. In this paper, given 3-D circuit placement or floorplan results with white space reserved between blocks for inter-layer interconnections, we proposed methods for assigning inter-layer signal via locations. Introducing a grid structure on the chip, the inter-layer via assignment of two-layer chips can be optimally solved by a convex-cost max-flow formulation with signal via congestion optimized. As for 3-D ICs with three or more layers, the inter-layer signal via assignment is modeled as an integral min-cost multi-commodity flow problem, which is solved by a heuristic method based on the lagrangian relaxation. Relaxing the capacity constraints in the grids, we transfer the min-cost multi-commodity flow problem to a sequence of lagrangian sub-problems, which are solved by finding a sequence of shortest paths. The complexity of solving a lagrangian sub-problem is O(nntng2), where nnt is the number of nets and ng is the number of grids on one chip layer. The experimental results demonstrated the effectiveness of the method.

Silicon photonic devices based on silicon photonic wire waveguides are especially attractive devices, since they can be ultra-compact and low-power consumption. In this paper, we demonstrated various devices fabricated on silicon photonic wire waveguides. They included optical directional couplers, reconfigurable optical add/drop multiplexers, 12, 14, 18 and 44 optical switches, ring resonators. The characteristics of these devices show that silicon photonic wire waveguides offer promising platforms in constructing compact and power-saving photonic devices and systems.

We identify a broadband equivalent circuit of an on-chip self-complementary antenna integrated with a µm-sized semiconductor mesa structure whose circuit elements can be interpreted by using closed-form analysis. Prior to the equivalent circuit analysis, an electromagnetic simulation is done to investigate frequency independency of the input impedance for the integrated self-complementary antenna in terahertz range.