We review our recent achievements in monolithic 3D-ICs and flexible electronics based on single-grain Si TFTs that are fabricated inside a single-grain with a low-temperature process. Based on pulsed-laser crystallization and submicron sized cavities made in the substrate, amorphous-Si precursor film was converted into poly-Si having grains that are formed on predetermined positions. Using the method called µ-Czochralski process and LPCVD a-Si precursor film, two layers of the SG Si TFT layers with the grains having a diameter of 6µm were vertically stacked with a maximum process temperature of 550°C. Mobility for electrons and holes were 600cm2/Vs and 200cm2/Vs, respectively. As a demonstration of monolithic 3D-ICs, the two SG-TFT layers were successfully implemented into CMOS inverter, 3D 6T-SRAM and single-grain lateral PIN photo-diode with in-pixel amplifier. The SG Si TFTs were applied to flexible electronics. In this case, the a-Si precursor was prepared by doctor-blade coating of liquid-Si based on pure cyclopentasilane (CPS) on a polyimide (PI) substrate with maximum process temperature of 350°C. The µ-Czochralski process provided location-controlled Si grains with a diameter of 3µm and mobilities of 460 and 121cm2/Vs for electrons and holes, respectively, were obtained. The devices on PI were transferred to a plastic foil which can operate with a bending diameter of 6mm. Those results indicate that the SG TFTs are attractive for their use in both monolithic 3D-ICs and flexible electronics.

In a convex drawing of a plane graph, all edges are drawn as straight-line segments without any edge-intersection and all facial cycles are drawn as convex polygons. In a convex grid drawing, all vertices are put on grid points. A plane graph G has a convex drawing if and only if G is internally triconnected, and an internally triconnected plane graph G has a convex grid drawing on an (n-1)×(n-1) grid if either G is triconnected or the triconnected component decomposition tree T(G) of G has two or three leaves, where n is the number of vertices in G. An internally triconnected plane graph G has a convex grid drawing on a 2n×2n grid if T(G) has exactly four leaves. In this paper, we show that an internally triconnected plane graph G has a convex grid drawing on a 6n×n2 grid if T(G) has exactly five leaves. We also present an algorithm to find such a drawing in linear time. This is the first algorithm that finds a convex grid drawing of such a plane graph G in a grid of polynomial size.

A reduction in the intensity deviation of a nine-channel optical frequency comb block (OFCB) is demonstrated, by adopting an asymmetric differential drive method for an InP-based dual drive Mach-Zehnder modulator. The generation of a tailored OFCB with an intensity deviation of less than 0.8dB is confirmed by using the modulator.

This paper proposes the use of on-chip monitor circuits to detect process shift and process spread for post-silicon diagnosis and model-hardware correlation. The amounts of shift and spread allow test engineers to decide the correct test strategy. Monitor structures suitable for detection of process shift and process spread are discussed. Test chips targeting a nominal process corner as well as 4 other corners of “slow-slow”, “fast-fast”, “slow-fast” and “fast-slow” are fabricated in a 65nm process. The monitor structures correctly detects the location of each chip in the process space. The outputs of the monitor structures are further analyzed and decomposed into the process variations in threshold voltage and gate length for model-hardware correlation. Path delay predictions match closely with the silicon values using the extracted parameter shifts. On-chip monitors capable of detecting process shift and process spread are helpful for performance prediction of digital and analog circuits, adaptive delay testing and post-silicon statistical analysis.

There is a relentless push for cost and size reduction in optical transmitters and receivers for fiber-optic links. Monolithically integrated optical chips in InP and Si may be a way to leap ahead of this trend. We discuss uses of integration technology to accomplish various telecommunications functions.

20-Gbps non return-to-zero (NRZ) – binary phase shift keying (BPSK) using the silicon Mach-Zehnder modulator is demonstrated and characterized. Measurement of a constellation diagram confirms successful modulation of 20-Gbps BPSK with the silicon modulator. Transmission performance is characterized in the measurement of bit-error-rate in accumulated dispersion range from -347 ps/nm to +334 ps/nm using SMF and a dispersion compensating fiber module. Optical signal-to-noise ratio required for bit-error-rate of 10-3 is 10.1 dB at back-to-back condition. It is 1.2-dB difference from simulated value. Obtained dispersion tolerance less than 2-dB power penalty for bit-error-rate of 10-3 is -220 ps/nm to +230 ps/nm. The symmetric dispersion tolerance indicates chirp-free modulation. Frequency chirp inherent in the modulation mechanism of the silicon MZM is also discussed with the simulation. The effect caused by the frequency chirp is limited to 3% shift in the chromatic dispersion range of 2 dB power penalty for BER 10-3. The effect inherent in the silicon modulation mechanism is confirmed to be very limited and not to cause any significant degradation in the transmission performance.

We have succeeded in demonstrating high-performance four-channel 25 Gb/s integrated receiver for 100 Gb/s Ethernet with a built-in spatial Demux optics and an integrated PD array. All components which configure to the Demux optics adhered to a prism. Because of the shaping accuracy for prism, the insertion loss was able to suppress to 0.8 dB with small size. The connection point of the package for high speed electrical signals was improved to decrease the transmission loss. The small size of 12 mm 17 mm 7 mm compact package with a side-wall electrical connector has been achieved, which is compatible with the assembly in CFP2 form-factor. We observed the sensitivity at average power of -12.1 dBm and the power penalty of sensitivity due to the crosstalk of less than 0.1 dB.

We have designed and fabricated a compact 4-array integrated SOA module using a novel parallel optical coupling scheme and polarization-insensitive built-in array isolators. We achieved ultra-high On/Off extinction ratio of more than 60 dB and low cross talk of better than -60 dB as well as high-isolation of over 47 dB in wide wavelength ranges. We also developed a wavelength-insensitive parallel optical coupling scheme and an efficient thermal dissipating structure for a 4-array SOA module. We applied these technologies into 4-array SOA module fabrication and demonstrated a uniform optical coupling with the loss variance of 1 dB over the 140-nm wavelength ranges. We also demonstrated simultaneous operation of 300 mA 4 channels with low thermal degradation of the module gain less than 1 dB.

An SiO2/Si-cap/Si0.55Ge0.45 heterostructure was fabricated on p-type Si(100) and strained silicon on insulator (SOI) substrates by low pressure chemical vapor deposition (LPCVD) and subsequent thermal oxidation in an O2 + H2 gas mixture. Chemical bonding features and valence band offsets in the heterostructures were evaluated by using high-resolution x-ray photoelectron spectroscopy (XPS) measurements and thinning the stack layers with a wet chemical solution.

In this paper, we present the validity and potential capacity of a modeling and simulation environment for the nonresonant plasmonic terahertz (THz) detector based on the silicon (Si) field-effect transistor (FET) with a technology computer-aided design (TCAD) platform. The nonresonant and “overdamped” plasma-wave behaviors have been modeled by introducing a quasi-plasma electron charge box as a two-dimensional electron gas (2DEG) in the channel region only around the source side of Si FETs. Based on the coupled nonresonant plasma-wave physics and continuity equation on the TCAD platform, the alternate-current (AC) signal as an incoming THz wave radiation successfully induced a direct-current (DC) drain-to-source output voltage as a detection signal in a sub-THz frequency regime under the asymmetric boundary conditions with a external capacitance between the gate and drain. The average propagation length and density of a quasi-plasma have been confirmed as around 100 nm and 11019/cm3, respectively, through the transient simulation of Si FETs with the modulated 2DEG at 0.7 THz. We investigated the incoming radiation frequency dependencies on the characteristics of the plasmonic THz detector operating in sub-THz nonresonant regime by using the quasi-plasma modeling on TCAD platform. The simulated dependences of the photoresponse with quasi-plasma 2DEG modeling on the structural parameters such as gate length and dielectric thickness confirmed the operation principle of the nonresonant plasmonic THz detector in the Si FET structure. The proposed methodologies provide the physical design platform for developing novel plasmonic THz detectors operating in the nonresonant detection mode.

We have fabricated MOS capacitors with a hybrid floating gate (FG) consisting of Ni silicide nanodots (NiSi-NDs) and silicon-quantum-dots (Si-QDs) and studied electron transfer characteristics in the hybrid FG structures induced by the irradiation of 1310 nm light. The flat-band voltage shift due to the charging of the hybrid FG under light irradiation was lower than that in the dark. The observed optical response can be attributed to the shift of the charge centroid in the hybrid FG caused by the photoexcitation of electrons in NiSi-NDs and their transfer to Si-QDs. The photoexcited electron transfer from the NiSi-NDs to the Si-QDs in response to pulsed gate voltages was also evaluated from the increase in transient current caused by the light irradiation. The amount of transferred charge is likely to increase in proportion to pulse gate voltage.

This paper evaluates the impact of Through-Silicon Via (TSV) on the performance and power consumption of 3D circuitry. The physical and electrical model of TSV which considers the coupling effects with adjacent TSVs is exploited in our investigation. Simulation results show that the overall performance of 3D IC infused with TSV can be improved noticeably. The frequency of the ring oscillator in 4-tier stacking layout soars up to two times compared with one in 2D planar. Furthermore, TSV process variations are examined by Monte Carlo simulations to figure out the geometrical factor having more impact in manufacturing. An in-depth research on repeater associated with TSV offers a metric to compute the optimization of 3D systems integration in terms of performance and energy dissipation. By such optimization metric with 45 nm MOSFET used in our circuit layout, it is found that the optimal number of tiers in both performance and power consumption approaches 4 since the substantial TSV-TSV coupling effect in the worst case of interference is expected in 3D IC.

In this paper, we have addressed the problem of ordering transactions in network-on-chips (NoCs) for post-silicon validation. The main idea is to extract the order of the transactions from the local partial orders in each NoC tile based on a set of “happened-before” rules, assuming transactions do not have a timestamp. The assumption is based on the fact that implementation and usage of a global time as timestamp in such systems may not be practical or efficient. When a new transaction is received in a tile, we send special messages to the neighboring tiles to inform them regarding the new transaction. The process of sending those special messages continues recursively in all the tiles that receive them until another such special message is detected. This way, we relate local orders of different tiles with each other. We show that our method can reconstruct the correct transaction orders when communication delays are deterministic. We have shown the effectiveness of our method by correctly ordering the transaction in NoCs with mesh and torus topologies with different sizes from 5*5 to 9*9. Also, we have implemented the proposed method in hardware to show its feasibility.

Post-silicon tuning is attracting a lot of attention for coping with increasing process variation. However, its tuning cost via testing is still a crucial problem. In this paper, we propose tuning-friendly body bias clustering with multiple bias voltages. The proposed method provides a small set of compensation levels so that the speed and leakage current vary monotonically according to the level. Thanks to this monotonic leveling and limitation of the number of levels, the test-cost of post-silicon tuning is significantly reduced. During the body bias clustering, the proposed method explicitly estimates and minimizes the average leakage after the post-silicon tuning. Experimental results demonstrate that the proposed method reduces the average leakage by 25.3 to 51.9% compared to non clustering case. In a test case of four clusters, the number of necessary tests is reduced by 83% compared to the conventional exhaustive test approach. We reveal that two bias voltages are sufficient when only a small number of compensation levels are allowed for test-cost reduction. We also give an implication on how to synthesize a circuit to which post-silicon tuning will be applied.

Microwave photoconductivity decay (µ-PCD) method was applied to evaluate the effects of chemical composition and Ar+ plasma induced damage on the bulk and the surface states in amorphous In-Ga-Zn-O (a-IGZO) films. It was found that the peak reflectivity signal in the photoconductivity response increased with decreasing the Ga content, and had a strong correlation with the a-IGZO transistor performances. In addition, the peak reflectivity signals obtained after various Ar+ plasma treatment duration were well correlated with the transistor characteristics. With Ar+ plasma treatment, the peak reflectivity signal decreased in accordance with degradation of transistor characteristics. The µ-PCD method was found to be a very useful tool not only to evaluate the bulk and the surface states, but also to predict the performance of a-IGZO transistors subjected to various plasma processes in the production.

3 dB bandwidth enhancement of single mode semiconductor lasers is confirmed numerically and experimentally when they are operated by intensity modulated signal light injection. 3 dB bandwidth is enlarged to 2.5 times of resonant frequency. The numerical analysis of rate equations predicts that the bandwidth enhancement is accomplished by the modal gain control of semiconductor lasers with injected intensity modulated signal light through non-linear gain coefficient term.

Reduction of the intensity noise in semiconductor lasers is an important subject for the higher performance of an application. Simultaneous usage of the superposition of high frequency current and the electric negative feedback loop was proposed to suppress the noise for the higher power operation of semiconductor lasers. Effective noise reduction of more than 25 dB with 80 mW operation was experimentally demonstrated.

A dual-core spot size converter (DC-SSC) is integrated with a lateral grating assisted lateral co-directional coupler (LGLC) tunable laser by using no additional complicated fabrication processes. The excess loss due to the DC-SSC is only 0.5 dB, and narrow full width half maximums (FWHMs) of vertical and horizontal far-field patterns (FFPs) produced by the laser are about 25° and 20°. This integration causes no degradations of the performance of the LGLC laser; in other words, it maintains good lasing characteristics, namely, wide tuning range of over 68 nm and SMSR of over 35 dB in the C-band under a 50 semi-cooled condition.

To improve the observability during the post-silicon validation, it is the key to select the limited trace signals effectively for the data acquisition. This paper proposes an automated trace signal selection algorithm, which uses the pruning-based strategy to reduce the exploration space. First, the restoration range is covered for each candidate signals. Second, the constraints are generated based on the conjunctive normal form (CNF) to avoid the conflict. Finally the candidates are selected through pruning-based enumeration. The experimental results indicate that the proposed algorithm can bring higher restoration ratios and is more effective compared to existing methods.

Efficient silicon-based light sources are expected to be key devices for applications such as optical interconnection. Huge number of researches has been conducted for realizing silicon-based light sources. Most of them utilized silicon-related materials such as silicon nanostructures or germanium, not crystalline silicon, which has been considered as a poor light emitter because of its indirect electronic bandgap. Light emission properties of materials can be tailored not only by modifying the material properties directly, but also by controlling the electromagnetic environment surrounding the material. Photonic nanostructures are a powerful tool for creating the engineered environment. In this paper, we briefly review the mechanisms for improving the light emission properties of materials by photonic nanostructures and present our recent experimental results showing the enhancement of light emission from silicon by introducing photonic crystal structures.