Monolithic integration of various kinds of optical components on a silicon wafer is the key to making silicon (Si) photonics practical technology. Applying silicon photonics to telecommunications further requires low insertion loss and polarization independence. We propose an integration concept for telecommunications based on Si and related materials and demonstrate monolithic integration of passive and dynamic functional components. This article shows the great potential of Si photonics technology for telecommunications.

We demonstrate phase demodulation of 10-Gbps DPSK signals using a silicon micro-ring resonator with a radius of 10 µm and with various coupling gaps for light of ∼1550 nm in wavelength. Influence of the Q factors and transmissions of the resonators on the response speed and power balance of the two output ports is discussed. Furthermore, temperature sensitivity on resonance peak was measured and we discuss its effect on practical demodulation application.

To characterize and predict the dynamics of the nonlinear polarization rotation in SOAs, an experimental method based on the frequency response technique and a model based on the density matrix and effective index formalisms are presented. Both determine the angular displacement, at the Poincare Sphere, that produces the evolution of the polarization of the output signal.

We fabricated solution-processed organic complementary inverters based on α,ω-bis(2-hexyldecyl)sexithiophene (BHD6T) for p-channel and C60-fused N-methylpyrrolidine-meta-dodecyl phenyl (C60MC12) for n-channel. The BHD6T and C60MC12 thin-film transistors showed high field-effect mobilities of 0.035 and 0.057 cm2/Vs, respectively. The complementary inverter with a supply voltage of 50 V exhibited inverting voltages of 26.8 V for forward and 27.0 V for backward sweeps and a high gain of 76.

Polymer multimode optical waveguides were fabricated from optically-sensitive hybrid silicone using the ultraviolet laser drawing method. The waveguide loss values were measured as 0.069 dB/cm with a laser diode, 0.069 dB/cm with a vertical-cavity surface-emitting laser, and 0.128 dB/cm with a light-emitting diode. The cross waveguide on a curved waveguide was drawn by overlapped direct laser drawing. The crosstalk and excess loss at the cross angle of 50 in the cross waveguide were measured as 47 dB and 0.5 dB, respectively.

Thin-film transistors based on Liquid-crystalline phenylterthiophenes, 3-TTPPh-5 and 3-TTPPhF4-6 are fabricated with a spin-coating method. The devices exhibit p-type operation with the mobility on the order of 10-2 cm2V-1s-1. The field-effect mobilities of the transistors using 3-TTPPh-5 and 3-TTPPhF4-6 are almost independent of the temperature above room temperature. In particular, the temperature range in which the mobility is constant is between 230 and 350 K for 3-TTPPh-5.

We have succeeded in developing high-performance p-type of organic semiconductors with phenylethynyl groups, which have high filed-effect mobilities (>3 cm2V-1s-1) by improving molecular planarity. A single crystal of the organic semiconductors has a herringbone structure. It plays an important role for carrier transport. In addition, we found that they had lower contact resistances to Au electrodes as well. Then, we used the materials for the carrier injection layer deposited onto another organic semiconductor we developed recently, which achieved a high field-effect mobility, and a low threshold voltage (Vth).

This report describes a crystallization method we developed for amorphous (a)-Si film by using 405-nm laser diodes (LDs). The proposed method has been used to fabricate bottom gate (BG) microcrystalline (µc)-Si TFTs for the first time. A µc-Si film with high crystallinity was produced and high-performance BG µc-Si TFTs with a field effect mobility of 3.6 cm2/Vs and a current on/off ratio exceeding 108 were successfully demonstrated. To determine the advantages of a 405-nm wavelength, a heat flow simulation was performed with full consideration of light interference effects. Among commercially available solid-state lasers and LDs with wavelengths having relatively high optical absorption coefficients for a-Si, three (405, 445, and 532 nm) were used in the simulation for comparison. Results demonstrated that wavelength is a crucial factor for the uniformity, efficiency, and process margin in a-Si crystallization for BG µc-Si TFTs. The 405-nm wavelength had the best simulation results. In addition, the maximum temperature profile on the gate electrode through the simulation well explained the actual crystallinity distributions of the µc-Si films.

Well-crystallized Ba2SiO4:Eu2+ powders were grown on a substrate by the vapor phase reaction between a mixed powder (barium carbonate and europium oxide) and SiO gas. The vaporization of SiO occurs at 1400–1600 from the SiO2 source (or SiO powder) in a reducing atmosphere. The formed SiO gas was transported by 95 vol% Ar - 5 vol% H2 gas and reacted with the raw material powders. The emission intensity of the Ba2SiO4:Eu2 + phosphor synthesized by the new vapor phase technique is about 2.6 times higher than that of a conventional solid-state reaction sample.

We have studied effects of additive elements into the channel layers of amorphous IGZO TFTs on threshold voltage shift issues under light illumination stress condition. By addition of Hf or Si element, the Vth shift under light illumination and negative bias-temperature stress and illumination stress conditions was drastically suppressed while the switching operation of TFTs using IGZO with Mn or Cu was not observed. It was found that the addition of Si or Hf element into the IGZO channel layer leads to reducing the hole trap sites formed at or near the gate insulator/IGZO channel interface.

Post-silicon debugging is getting even more critical to shorten the time-to-market than ever, as many more bugs escape pre-silicon verification according to the increasing design scale and complexity. Post-silicon debugging is generally harder than pre-silicon debugging due to the limited observability and controllability of internal signal values. Conventionally, simulation of corresponding low-level designs such as RTL or gate-level has been used to get observability and controllability, which is inefficient for contemporary large designs. In this paper, we introduce a post-silicon debugging approach using simulation of high-level designs, instead of low-level designs. To realize such a debugging approach, we propose an I/O sequence mapping method that converts I/O sequences of chip executions to those of the corresponding high-level design. First, we provide a formal definition of I/O sequence mapping and relevant notions. Then, based on the definition, we propose an I/O sequence mapping method by executing FSMs representing the interface specifications of the target design. Also, we propose an implementation of the proposed method to get further efficiency. We demonstrate that the proposed method can be effectively applied to several practical design examples with various interfaces.

Silicon Mach-Zehnder interferometric (MZI) waveguide modulator incorporating the n-channel junction field-effect transistor (JFET) as a signal modulation unit was designed, fabricated, and analyzed. The proposed MZI with JFET was designed to operate based on the plasma dispersion effect in the infrared wavelength of 1550 nm. The three different modulation lengths (ML) of 500, 1000, and 2000 µm while keeping the overall MZI length constant at 1.5 cm were set as a general design rule for these 10 µm-wide MZIs under study. When the JFET was operated in an active mode by injecting approximately 50 mA current (Is) to achieve a π phase shift, the modulation efficiency of the device was measured to be η = π /(Is· L) 40π/A-mm. The temporal and frequency response measurements also demonstrate that the respectively rise and fall times measured using a high-speed photoreceiver were in the neighborhood of 8.5 and 7.5 µsec and the 3 dB roll-off frequency (f3 dB) measured was in the excess of 400 kHz.

In this paper we present eigenmode analysis of the propagation constant for a microstrip line with dummy fills on a Si CMOS substrate. The effect of dummy fills is not negligible, particularly in the millimeter-wave band, although it has been ignored below frequencies of a few GHz. The propagation constant of a microstrip line with a periodic structure on a Si CMOS substrate is analyzed by eigenmode analysis for one period of the line. The calculated propagation constant and characteristic impedance were compared with measured values for a chip fabricated by the 0.18 µm CMOS process. The agreement between the analysis and measurement was very good. The dependence of loss on the arrangement of dummy fills was also investigated by eigenmode analysis. It was found that the transmission loss becomes large when dummy fills are arranged at places where the electromagnetic field is strong.

This work focuses on a study of strain effects in resistor stress sensors fabricated on (001) silicon and their influences on the determination of piezoresistive (pi) coefficients for the precise measurements of die stresses in electronic packages. We obtained the corrected values of the pi-coefficients by considering the strain effects, without which more than 50% discrepancies may be induced.

We investigated the effects of various field plate and buried gate structures on the DC and small signal characteristics of 4H-silicon carbide (SiC) metal-semiconductor field-effect transistors (MESFETs). In comparison with the source-connected field plate, the gate-connected field plate exhibited superior frequency response while having similar DC characteristics. In order to further enhance the output power, dual field plates were employed in conjunction with a buried gate structure.

In a rooted triangulated planar graph, an outer vertex and two outer edges incident to it are designated as its root, respectively. Two plane embeddings of rooted triangulated planar graphs are defined to be equivalent if they admit an isomorphism such that the designated roots correspond to each other. Given a positive integer n, we give an O(n)-space and O(1)-time delay algorithm that generates all biconnected rooted triangulated planar graphs with at most n vertices without delivering two reflectively symmetric copies.

Semiconducting polymers, poly(1,4-phenylene) (PPP) and poly(4-diphenylaminostyrene) (PDAS), which are soluble to organic solvents, were synthesized and were deposited by means of electrospray deposition (ESD). The ESD generated spherical shells of diameters ranging from a few to several tens of microns. The shells consisted of coagulation of nanometric particles of the semiconducting polymers. Formation of the shells was largely influenced by the concentration of spray solution. It was also found that the formation of shells can be achieved with various types of soluble polymers.

We have demonstrated the inverter operation of stacked-structure CMOS devices using pentacene and ZnO as active layers. The fabrication process of the device is as follows: A top-gate-type ZnO thin-film transistor (TFT), working as an n-channel transistor, was formed on a glass substrate. Then, a bottom-gate-type pentacene TFT, as a p-channel transistor, was fabricated on top of the ZnO TFT while sharing a common gate electrode. For both TFTs, solution-processed silicone-resin layers were used as gate dielectrics. The stacked-structure CMOS has several advantages, for example, easy patterning of active material, compact device area per stage and short interconnection length, as compared with the planar configuration in a conventional CMOS circuit.

Hydrogenated polymorphous Silicon allows to fabricate TFTs with very interesting characteristics including better threshold voltage stability than a-Si TFTs, lower leakage current than µc-Si:H TFTs and excellent uniformity. Investigation of threshold voltage shift mechanisms of pm-Si:H TFTs has shown a specific semiconductor material degradation with different activation energies compared to a-Si:H TFTs. TEM analysis has evidenced for the first time a significant structural difference between pm-Si:H and a-Si:H materials, in the TFT device configuration. Pm-Si:H appears to be very suitable for low cost and high performance AM-OLED fabrication.

An analog pre-distortion linearizer employing a radio frequency (RF) transistor with a self base bias control circuit is proposed. The self base bias control circuit extracts the envelope from the modulated input RF signal of the RF transistor and automatically controls its base current according to the extracted envelope. As a result, the proposed linearizer realizes positive gain deviation at high input power level. By adding a resistor between the RF transistor and the self base bias control circuit, the negative gain deviation can be derived. The design of the proposed lineaizer is described with taking the envelope frequency response of the self base bias control circuit into consideration. The fabricated linearizer achieves the adjacent channel power leakage ratio (ACLR) improvement of 8.1 dB for a 2 GHz-band, 10 W-class GaAs FET high-power amplifier (HPA) with negative gain deviation for W-CDMA base stations. It also achieves the ACLR improvement of 8.3 dB for a LDMOS HPA with positive gain deviation for the same application.