We review our research progress of multi-port optical switches based on the silicon photonics platform. Up to now, the maximum port-count is 32 input ports×32 output ports, in which transmissions of all paths were demonstrated. The switch topology is path-independent insertion-loss (PILOSS) which consists of an array of 2×2 element switches and intersections. The switch presented an average fiber-to-fiber insertion loss of 10.8 dB. Moreover, -20-dB crosstalk bandwidth of 14.2 nm was achieved with output-port-exchanged element switches, and an average polarization-dependent loss (PDL) of 3.2 dB was achieved with a non-duplicated polarization-diversity structure enabled by SiN overpass waveguides. In the 8×8 switch, we demonstrated wider than 100-nm bandwidth for less than -30-dB crosstalk with double Mach-Zehnder element switches, and less than 0.5 dB PDL with polarization diversity scheme which consisted of two switch matrices and fiber-type polarization beam splitters. Based on the switch performances described above, we discuss further improvement of switching performances.

A compact silicon photonic crystal waveguide (PCW) slow-light modulator is presented. The proposed modulator is capable of achieving a 64 Gbps bit-rate in a wide operating spectrum. The slow-light enhances the modulation efficiency in proportion to its group index ng. Two types of 200-µm-long PCW modulators are presented. These are low- and high-dispersion devices, which are implemented using a complementary metal-oxide-insulator process. The lattice-shifted PCW achieved low-dispersion slow-light and exhibited ng ≈ 20 with an operating spectrum Δλ ≈ 20 nm, in which the fluctuation of the extinction ratio is ±0.5 dB. The PCW device without the lattice shift exhibited high-dispersion, for which a large or small value of ng can be set on demand by changing the wavelength. It was found that for a large ng, the frequency response was degraded due to the electro-optic phase mismatch between the RF signals and slow-light even for such small-size modulators. Meander-line electrodes, which bypass and delay the RF signals to compensate for the phase mismatch, are proposed. A high cutoff frequency of 55 GHz was theoretically predicted, whereas the experimentally measured value was 38 GHz. A high-quality open eye pattern for a drive voltage of 1 V at 32 Gbps was observed. The clear eye pattern was maintained for 50-64 Gbps, although the drive voltage increased to 3.5-5.3 V. A preliminary operation of a 2-bits pulse amplitude modulation up to 100 Gbps was also attempted.

Effective user accommodation will be more and more important in passive optical networks (PONs) in the next decade since the number of subscribers has been leveling off as well and it is becoming more difficult for network operators to keep sufficient numbers of maintenance workers. Drastically reducing the number of small-scale communication buildings while keeping the number of accommodated users is one of the most attractive solutions to meet this situation. To achieve this, we propose two types of long-reach repeater-free upstream transmission configurations for PON systems; (i) one utilizes a semiconductor optical amplifier (SOA) as a pre-amplifier and (ii) the other utilizes distributed Raman amplification (DRA) in addition to the SOA. Our simulations assuming 10G-EPON specifications and transmission experiments on a 10G-EPON prototype confirm that configuration (i) can add a 17km trunk fiber to a normal PON system with 10km access reach and 1 : 64 split (total 27km reach), while configuration (ii) can further expand the trunk fiber distance to 37km (total 47km reach). Network operators can select these configurations depending on their service areas.

This work reports a new technique to suppress the undesirable multiple-triggering effect in the typical diode triggered silicon controlled rectifier (DTSCR), which is frequently used as an ESD protection element in the advanced CMOS technologies. The technique is featured by inserting additional N-Well areas under the N+ region of intrinsic SCR, which helps to improve the substrate resistance. As a consequence, the delay of intrinsic SCR is reduced as the required triggering current is largely decreased and multiple-triggering related higher trigger voltage is removed. The novel DTSCR structures can alter the stacked diodes to achieve the precise trigger voltage to meet different ESD protection requirements. All explored DTSCR structures are fabricated in a 65-nm CMOS process. Transmission-line-pulsing (TLP) and Very-Fast-Transmission-line-pulsing (VF-TLP) test systems are adopted to confirm the validity of this technique and the test results accord well with our analysis.

In partially depleted SOI (PD-SOI) technology, the SCR-based protection device is desired due to its relatively high robustness, but be restricted to use because of its inherent low holding voltage (Vh) and high triggering voltage (Vt1). In this paper, the body-tie side triggering diode inserting silicon controlled rectifier (BSTDISCR) is proposed and verified in 180 nm PD-SOI technology. Compared to the other devices in the same process and other related works, the BSTDISCR presents as a robust and latchup-immune PD-SOI ESD protection device, with appropriate Vt1 of 6.3 V, high Vh of 4.2 V, high normalized second breakdown current (It2), which indicates the ESD protection robustness, of 13.3 mA/µm, low normalized parasitic capacitance of 0.74 fF/µm.

We have developed the world's largest 16.7-inch hybrid in-cell touch panel. To realize the large sized in-cell touch panel, we applied a vertical Vcom system and low resistance sensor, which are JDI's original technologies. For glove touch function, we applied mutual bundled driving, which increases the signal intensity higher. The panel also has a low surface reflection, curved-shaped, and non-rectangular characteristics, which are particular requirements in the automotive market. The over 15-inch hybrid in-cell touch panel adheres to automotive quality requirements. We have also developed a force touch panel, which is a new human machine interface (HMI) based on a hybrid in-cell touch panel in automotive display. This study reports on the effect of the improvements on the in-plane variation of force touch and the value change of the force signal under different environment conditions. We also a introduce force touch implemented prototype.

With the advantages of higher blocking voltage, higher operation temperature, fast-switching characteristics, and lower switching losses, the silicon carbide (SiC) MOSFET has attracted more attentions and become an available replacement of traditional silicon (Si) power semiconductor in applications. Despite of all the merits above, electromagnetic interference (EMI) issues will be induced consequently by the ultra-fast switching transitions of the SiC MOSFET. To quickly and precisely assess the switching behaviors of the SiC MOSFET for EMI investigation, an analytical model is proposed. This model has comprehensively considered most of the key factors, including parasitic inductances, non-linearity of the junction capacitors, negative feedback effect of Ls and Cgd shared by the power and the gate stage loops, non-linearity of the trans-conductance, and skin effect during voltage and current ringing stages, which will considerably affect the switching performance of the SiC MOSFET. Additionally, a finite-state machine (FSM) is especially utilized so as to analytically and intuitively describe the switching behaviors of the SiC MOSFET via Stateflow. Based on double pulse test (DPT), the effectiveness and correctness of the proposed model are validated through the comparison between the calculated and the measured waveforms during switching transitions. Besides, the model can appropriately depict the spectrum of the drain-source voltage of the MOSFET and is suitable for EMI investigation in applying of SiC devices.

Due to progressing process technology, yield of chips is reduced by timing violation caused by delay variation of gates and wires in fabrication. Recently, post-silicon delay tuning, which inserts programmable delay elements (PDEs) into clock trees before the fabrication and adjusts the delays of the PDEs to recover the timing violation after the fabrication, is promising to improve the yield. Although post-silicon delay tuning improves the yield, it increases circuit area and power consumption since the PDEs are inserted. In this paper, a PDE structure is taken into consideration to reduce the circuit area and the power consumption. Moreover, a delay selection algorithm, and a clustering method, in which some PDEs are merged into a PDE and the PDE is inserted for multiple registers, are proposed to reduce the circuit area and the power consumption. In computational experiments, the proposed method reduced the circuit area and the power consumption in comparison with an existing method.

We report our recent progress in silicon photonics integrated device technology targeting on-chip-level large-capacity optical interconnect applications. To realize high-capacity data transmission, we successfully developed on-package-type silicon photonics integrated transceivers and demonstrated simultaneous 400 Gbps operation. 56 Gbps pulse-amplitude-modulation (PAM) 4 and wavelength-division-multiplexing technologies were also introduced to enhance the transmission capacity.

To address the bandwidth bottleneck that exists between LSI chips, we have proposed a novel, high-sensitivity receiver circuit for differential optical transmission on a silicon optical interposer. Both anodes and cathodes of the differential photodiodes (PDs) were designed to be connected to a transimpedance amplifier (TIA) through coupling capacitors. Reverse bias voltage was applied to each of the differential PDs through load resistance. The proposed receiver circuit achieved double the current signal amplitude of conventional differential receiver circuits. The frequency response of the receiver circuit was analyzed using its equivalent circuit, wherein the temperature dependence of the PD was implemented. The optimal load resistances of the PDs were determined to be 5kΩ by considering the tradeoff between the frequency response and bias voltage drop. A small dark current of the PD was important to reduce the voltage drop, but the bandwidth degradation was negligible if the dark current at room temperature was below 1µA. The proposed circuit achieved 3-dB bandwidths of 18.9 GHz at 25°C and 13.7 GHz at 85°C. Clear eye openings in the TIA output waveforms for 25-Gbps 27-1 pseudorandom binary sequence signals were obtained at both temperatures.

A number of all-optical signal processing schemes based on nonlinear optical effects have been proposed and demonstrated for use in future photonic networks. Since various modulation formats have been developed for optical communication systems, all-optical converters between different modulation formats will be a key technology to connect networks transparently and efficiently. This paper reviews our recent works on all-optical modulation format conversion technologies in order to highlight the fundamental principles and applications in variety of all-optical signal processing schemes.

Optical I/O core based on silicon photonics technology and optical/electrical assembly was developed as a fingertip-size optical module with high bandwidth density, low power consumption, and high temperature operation. The advantages of the optical I/O core, including hybrid integration of quantum dot laser diode and optical pin, allow us to achieve 300-m transmission at 25Gbps per channel when optical I/O core is mounted around field-programmable gate array without clock data recovery.

We examined single crystal growth of benzothienobenzothiophene-based organic semiconductors by solution coating method using liquid crystal and investigated its electrical characteristics. As the results, we revealed that the averaged mobility in the saturation region reached 2.08 cm2/Vs along crystalline b-axis, and 1.08 cm2/Vs along crystalline a-axis.

In this paper, we examined the transfer method of fluororesin as the novel formation method of polymer wall in order to realize the lattice-shaped polymer walls without patterned light irradiation using photomask. We clarified that the transfer method was effective for formation of polymer wall structure on flexible substrate.

A design-for-testability method and an electrical interconnect test method are proposed to detect open defects occurring at interconnects among dies and input/output pins in 3D stacked ICs. As part of the design method, an nMOS and a diode are added to each input interconnect. The test method is based on measuring the quiescent current that is made to flow through an interconnect to be tested. The testability is examined both by SPICE simulation and by experimentation. The test method enabled the detection of open defects occurring at the newly designed interconnects of dies at experiments test speed of 1MHz. The simulation results reveal that an open defect generating additional delay of 279psec is detectable by the test method at a test speed of 200MHz beside of open defects that generate no logical errors.

The growth mechanisms of three-dimensionally (3D) faceted InGaN quantum wells (QWs) on (=1=12=2) GaN substrates are discussed. The structure is composed of (=1=12=2), {=110=1}, and {=1100} planes, and the cross sectional shape is similar to that of 3D QWs on (0001). However, the 3D QWs on (=1=12=2) and (0001) show quite different inter-facet variation of In compositions. To clarify this observation, the local thicknesses of constituent InN and GaN on the 3D GaN are fitted with a formula derived from the diffusion equation. It is suggested that the difference in the In incorporation efficiency of each crystallographic plane strongly affects the surface In adatom migration.

Frequency chirp of a semiconductor laser is controlled by using hybrid modulation, which simultaneously modulates intra-cavity loss and injection current to the laser. The positive adiabatic chirp of injection-current modulation is compensated with the negative adiabatic chirp created by intra-cavity-loss modulation, which enhances the chromatic-dispersion tolerance of the laser. A proof-of-concept transmission experiment confirmed that the hybrid modulation laser has a larger dispersion tolerance than conventional directly modulated lasers due to the negative frequency chirp originating from intra-cavity-loss modulation.

Quadrant silicon avalanche photodiodes (APDs) were fabricated by standard 0.18µm CMOS process, and were characterized at 405nm wavelength for Blu-ray applications. The size of each APD element is 50×50µm2. The dark current was 10pA at low bias voltage, and low crosstalk of about -80dB between adjacent APD elements was achieved. Although the responsivity is less than 0.1A/W at low bias voltage, the responsivity is enhanced to more than 1A/W at less than 10V bias voltage due to avalanche amplification. The wide bandwidth of 1.5GHz was achieved with the responsivity of more than 1A/W, which is limited by the capacitance of the APD. We believe that the fabricated quadrant APD is a promising photodiode for multi-layer Blu-ray system.

In the past decade, real-time systems (RTSs), which must maintain time constraints to avoid catastrophic consequences, have been widely introduced into various embedded systems and Internet of Things (IoTs). The RTSs are required to be energy efficient as they are used in embedded devices in which battery life is important. In this study, we investigated the RTS energy efficiency by analyzing the ability of body bias (BB) in providing a satisfying tradeoff between performance and energy. We propose a practical and realistic model that includes the BB energy and timing overhead in addition to idle region analysis. This study was conducted using accurate parameters extracted from a real chip using silicon on thin box (SOTB) technology. By using the BB control based on the proposed model, about 34% energy reduction was achieved.

To prepare antireflection coating (ARC) by wet process is important technology for low cost fabrication of solar cells. In this research, we consider the optical reflectance of a three layer stack structure of ARC films on the pyramidally textured single-crystalline silicon substrates. Each layer of the ARC films is deposited by a spin-coating method. The triple layers consist of SiO2, SiO2-TiO2 mixture, and TiO2 films from air to the silicon substrate in that order, and the refractive index is slightly increased from air to the substrate. Light reflection can be reduced further mainly due to graded index effect. The optimized three layer structure ARC shows that the reflectance is below 0.048 at the wavelength of 600 nm.