This paper describes the experimental performance of eigenbeam multi-input multi-output with orthogonal frequency division multiplexing (MIMO-OFDM) systems as measured in a testbed implemented with field programmable gate arrays (FPGAs). The FPGA-testbed, characterized by the software-defined radio (SDR) technique, offers 1/5-scale real time signal processing. Extensive experiments on the testbed confirm the basic operation and performance of eigenbeam MIMO-OFDM with quadrature phase-shift keying (QPSK) and 16 quadrature amplitude modulation (QAM). From the packet error rate (PER) performance, we confirm that the eigenbeam 16QAM/MIMO-OFDM scheme with permutation matrix and three transmit antennas (Mt=3) drastically improves the required carrier-to-noise power ratio (CNR) by approximately 5.6 dB over the scheme without eigenbeam with Mt=2. Furthermore, to determine the impact of Doppler frequency fd, we focus on the transmission interval between the MIMO channel estimation and data transmission. To suppress the required CNR degradation to within 1.5 dB, it is found that the eigenbeam 16QAM/MIMO-OFDM scheme with permutation matrix and Mt=3 permits a transmission interval of approximately 68.5 ms when fd=1 Hz for a 1/5-scale model.

We have developed a solid-electrolyte nonvolatile switch (here we refer as NanoBridge) with a low ON resistance and its small size. When we use a NanoBridge to switch elements in a programmable logic device, the chip size (or die cost) can be reduced and performance (speed and power consumption) can be enhanced. Developing this application required solving a couple of problems. First, the switching voltage of the NanoBridge (0.3 V) needed to be larger than the operating voltage of the logic circuit (>1 V). Second, the programming current (>1 mA) needed to be suppressed to avoid large power consumption. We demonstrate how the Nanobridge enhances the switching voltage and reduces the programming current.

In this paper, the authors present a new digital circuit of neuron hardware using a field programmable gate array (FPGA). A new Inverse function Delayed (ID) neuron model is implemented. The Inverse function Delayed model, which includes the BVP model, has superior associative properties thanks to negative resistance. An associative memory based on the ID model with self-connections has possibilities of improving its basin sizes and memory capacity. In order to decrease circuit area, we employ stochastic logic. The proposed neuron circuit completes the stimulus response output, and its retrieval property with negative resistance is superior to a conventional nonlinear model in basin size of an associative memory.

The optical ZCZ code is a set of pairs of binary and bi-phase sequences with zero correlation zone. An optical M-ary direct sequence spread spectrum (M-ary/DS-SS) system using this code can detect a desired sequence without interference of undesired sequences. However, the bank of matched filters in a receiver circuit may fall into large scale. In this paper, we propose the compact construction of a bank of matched filters for an M-ary/DS-SS system using an optical ZCZ code. This filter bank can decrease the number of 2-input adders from O(N2) to O(N) and delay circuits from O(N2) to O(Nlog 2 N), respectively, and is implemented on a field programmable gate array (FPGA) corresponding to 400,000 logic gates.

QMNF is a QoS-aware multicast routing protocol using N-hop dominating flooding and built upon a layered routing architecture. In this architecture, QMNF invites the N-hop flooding component and the shortest path routing table from OSPF by open signaling interfaces, floods the path-probing packets, and employs a two-pass resource reservation scheme to avoid unnecessary resource reservation. The QMNF is QoS-aware, loop-free, flexible and scalable, and improves network resource utilization. In our simulation, the performance of QMNF is compared with that of traditional flooding protocol with the shortest path resources reservation, a traditional flooding protocol with the widest path resources reservation, PIM and QMBF. The simulation results confirm that QMNF has a high success rate and good resource utilization, and it can distribute traffic in a network evenly.

We developed two types of practical maximum-likelihood detectors (MLD) for multiple-input multiple-output (MIMO) systems, using a field programmable gate array (FPGA) device. For implementations, we introduced two simplified metrics called a Manhattan metric and a correlation metric. Using the Manhattan metric, the detector needs no multiplication operations, at the cost of a slight performance degradation within 1 dB. Using the correlation metric, the MIMO-MLD can significantly reduce the complexity in both multiplications and additions without any performance degradation. This paper demonstrates the bit-error-rate performance of these MLD prototypes at a 1 Gbps-order real-time processing speed, through the use of an all-digital baseband 44 MIMO testbed integrated on the same FPGA chip.

This paper presents a design method for three-level programmable logic arrays (PLAs), which have input decoders and two-input EXOR gates at the outputs. The PLA realizes an EXOR of two sum-of-products expressions (EX-SOP) for multiple-valued input two-valued output functions. We developed an output phase optimization method for EX-SOPs where some outputs of the function are minimized in the complemented form and presented techniques to minimize EX-SOPs for adders by using an extension of Dubrova-Miller-Muzio's AOXMIN algorithm. The proposed algorithm produces solutions with a half products of AOXMIN-like algorithm in 250 times shorter time for large adders with two-valued inputs. We also proved that an n-bit adder with two-valued inputs requires at most 32n-2+7n-5 products in an EX-SOP while it is known that a sum-of-products expression (SOP) requires 62n-4n-5 products.

A systolic array is an ideal for ASICs because of its massive parallelism with a minimum communication overhead, regularity and modularity. Most of commercial FPGAs cannot handle systolic structure with fast sampling rate for their general-purpose architecture nature. This paper presents a new PLD architecture targeting a super-systolic array for application-specific arithmetic operations such as MAC. This architecture combines the high performance of ASICs with the flexibility of PLDs and it offers a significant alternative view on the programmable logic devices. The super-systolic array is ideal for a newly proposed PLD architecture when it comes to area-efficiency, P&R and clock speed.

Programmable Logic Controller (PLC) has been widely used in the industrial control. Inherently, the PLC-based system is a class of Hybrid Dynamical System (HDS) in which continuous state of the plant is controlled by the discrete logic-based controller. This paper firstly presents the formal algebraic model of the PLC-based control systems which enable the designer to formulate the various kinds of optimization problem. Secondly, the optimization problem of the 'sensor parameters,' such as the location of the limit switch in the material handling system, the threshold temperature of the thermostat in the temperature control system, is addressed. Finally, we formulate this problem as Mixed Logical Dynamical Systems (MLDS) form which enables us to optimize the sensor parameters by applying the Mixed Integer Programming.

In this paper, we present the condition for the effective wire addition in Look-Up-Table-based (LUT-based) field programmable gate array (FPGA) circuits, and an optimization procedure utilizing the effective wire addition. Each wire has different characteristics, such as delay and power dissipation. Therefore, the replacement of one critical wire for the circuit performance with many non-critical ones, i.e., many-addition-for-one-removal (m-for-1) is sufficiently useful. However, the conventional logic optimization methods based on sets of pairs of functions to be distinguished (SPFDs) for LUT-based FPGA circuits do not make use of the m-for-1 manipulation, and perform only simple replacement and removal, i.e., the one-addition-for-one-removal (1-for-1) manipulation and the no-addition-for-one-removal (0-for-1) manipulation, respectively. Since each LUT can realize an arbitrary internal function with respect to a specified number of input variables, there is no sufficient condition at the logic design level for simple wire addition. Moreover, in general, simple addition of a wire has no effects for removal of another wire, and it is important to derive the condition for non-simple and effective wire addition. We found the SPFD-based condition that wire addition is likely to make another wire redundant or replaceable, and developed an optimization procedure utilizing this effective wire addition. According to the experimental results, when we focused on the delay reduction of LUT-based FPGA circuits, our method reduced the delay by 24.2% from the initial circuits, while the conventional SPFD-based logic optimization and the enhanced global rewiring reduced it by 14.2% and 18.0%, respectively. Thus, our method presented in this paper is sufficiently practical, and is expected to improve the circuit performance.

A look-up table (LUT) cascade is a new type of a programmable logic device (PLD) that provides an alternative way to realize multiple-output functions. An LUT ring is an emulator for an LUT cascade. Compared with an LUT cascade, the LUT ring is more flexible. In this paper we discuss the realization of multiple-output functions with the LUT ring. Unlike an FPGA realization of a logic function, accurate prediction of the delay time is easy in an LUT ring realization. A prototype of an LUT ring has been custom-designed with 0.35 µm CMOS technology. Simulation results show that the LUT ring is 80 to 241 times faster than software programs on an SH-1, and 36 to 93 times faster than software programs on a PentiumIII when the frequencies for the LUT ring and the MPUs are the same, but is slightly slower than commercial FPGAs.

A multifunctional Boolean logic circuit composed of single-electron transistors (SETs) was fabricated and its operation demonstrated. The functions of Boolean logic can be changed by the half-period phase shift of the Coulomb-blockade (CB) oscillation of some SETs in the circuit, and an automatic control based on a feedback process is used to attain an exact shift. The amount of charges in the memory node (MN), which is capacitively coupled to the SET, controls the phase of the CB oscillation, and the output signal of the SET controls the amount of charge in the MN during the feedback process. This feedback process automatically adjusts SET output characteristics in such a way that it is used for the multifunctional Boolean logic. We experimentally demonstrated the automatic phase control and examined the speed of the feedback process by SPICE circuit simulation combined with a compact analytical SET model. The simulation revealed that programming time could be of the order of a few ten nanoseconds, thereby promising high-speed switching of the functions of the multifunctional Boolean logic circuit.

Circuit techniques to realize stable recall operation and virtually unlimited read/program cycle operations in ferroelectric memory based nonvolatile (NV) SRAM composed of six-transistor and four-ferroelectric capacitor cells have been developed. Unlimited program cycle operation independent of ferroelectric material characteristics is realized by proper control of plate lines. Reliability evaluation results show that the developed memory cell has sufficient operation margin after stresses of temperature, fatigue, DC bias. Application of NV-SRAM to programmable logic devices has been discussed with a prototype of dynamically programmable gate arrays.

This paper describes the design of a programmable QAM transceiver for VDSL applications. A 12-b DAC with 64-dB spurious-free dynamic range (SFDR) at 75-MS/s and an 11-b ADC with 72.3-dB SFDR at 70-MS/s are integrated in this complete physical layer IC. A digital IIR notch filter is included in order to not interrupt existing amateur radio bands. The proposed dual loop AGC adjusts the gain of a variable gain amplifier (VGA) to obtain maximum SNR while avoiding saturation. Using several low power techniques, the total power consumption is reduced to 300-mW at 1.8-V core and 3.3-V I/O supplies. The transceiver is fabricated in a 0.18-µm CMOS process and the chip size is 5-mm 5-mm. This VDSL transceiver supports 13-Mbps data rate over a 9000-ft channel with a BER < 10-7.

The PLC (Programmable Logic Controller) has been widely used in the industrial world as a controller for manufacturing systems, as a process controller and so on. The conventional PLC has been designed and verified as a pure Discrete Event System (DES) by using an abstract model of a controlled plant. In verifying the PLC, however, it is also important to take into account the physical behavior (e.g. dynamics, shape of objects) of the controlled plant in order to guarantee such important factors as safety. This paper presents a new verification technique for the PLC-based control system, which takes into account these physical behaviors, based on a Hybrid Dynamical System (HDS) framework. The other key idea described in the paper is the introduction of the concept of signed distance which not only measures the distance between two objects but also checks whether two objects interfere with each other. The developed idea is applied to illustrative material handling problems, and its usefulness is demonstrated.

Field Configurable Self-assembly is a novel programmable force field based heterogeneous integration technology. Herein, we demonstrate application of the method to rapid, parallel assembly of similar and dissimilar sub-200 µm GaAs-based light emitting diodes at silicon chip substrates. We also show that the method is compatible with post-process collective wiring techniques for fully planar hybrid integration of active devices.

In this paper, we propose a novel pulse-coupled neural network (PCNN) simulator using a programmable gate array (PGA) technique. The simulator is composed of modified phase-locked loops (PLLs) and a programmable gate array (PGA). The PLL, which is modified by the addition of multiple inputs and multiple feedbacks, works as a neuron. The PGA, which controls the network connection, works as nodes of dendritic trees. This simulator, which has 16 neurons and 32 32 network connections, is designed on a chip (4.73mm 4.73mm), and its basic operations such as synchronization, an oscillatory associative memory, and FM interactions are confirmed using circuit simulator SPICE.

The paper describes the folding method of logic functions to reduce the size of memories to keep the functions. The folding is based on the relation of fractions of logic functions. If the logic function includes 2 or 3 same parts, then only one part should be kept and other parts can be omitted. We show that the logic function of 1-bit addition can be reduced to half size using the bit-wise NOT relation and the bit-wise OR relation. The paper also introduces 3-1 LUT's with the folding mechanism. A full adder can be implemented using only one 3-1 LUT with the folding. Multi-bit AND and OR operations can be mapped to our LUT's not using the extra cascading circuit but using the carry circuit for addition. We have also tested the mapping capability of 4 input functions to our 3-1 LUT's with folding and carry propagation mechanisms. We have shown the reduction of the area consumption when using our LUT's compared to the case using 4-1 LUT's on several benchmark circuits.

In this paper, we focus attention on the development of security techniques using software defined radio (SDR) technologies. We propose a new secure download system which uses the characteristics of the field programmable gate arrays (FPGAs) composing the SDR. The proposed system has the novelty that realization of high security encipherment is possible. This is achieved using the characteristic of FPGAs which allows systems to be arranged in a variety of different layouts, as well as by using the configuration information as the key. This unifies the renewal of the key and the encipherment. In addition the proposed system has the merit that it has high security against illegal acquisition such as a wiretapping, and can also be used in conjunction with any other current cipher algorithm. As an evaluation of the security, we show that the proposed system has high immunity to illegal acquisition of software using replay attack, by verification of the protocol as well as by numerical computation. The proposed system can therefore realize high security software downloads based on SDR.

This paper presents an architecture for a table-lookup (TLU) engine that allows the real-time operation of complicated TLU for telecommunications, such as the longest prefix match (LPM) and the long-bit match in packet classification. The engine consists of many CAM (Content Addressable Memory) chips, which are classified into several groups. When actual TLU is performed, the entries in each CAM group are searched simultaneously, and the best entry candidate in each group is selected by an intra-group arbiter. The final output, the entry desired, is decided by an inter group arbiter that selects one group. This hierarchical structure of arbitration is the key to the scalability of the engine. To accelerate the operation speed of the engine, we introduce a novel mechanism called "hit-flag look-ahead" that sends a hit-flag signal from each matched CAM chip to the inter group arbiter before each intra group arbiter calculates the best CAM output in the group. We show that a TLU engine based on the above architecture achieves significantly fast performance compared to engines based on conventional techniques, especially in the case of a large number of entries with long-bit matching. Furthermore, our architecture can realize an 33.3 Mlps (lookups per second) within a 128 bit 300,000-entry table at wire speed.