For over 40-Gbps optical communication systems, phase coded modulation formats, like differential phase shift keying (DPSK) and quadrature phase shift keying (QPSK), are very important for signal frequency efficiency and long-reach transmission. In such systems, differential receivers which regenerate phase signals are key components. Dual Photo Diodes (dual PDs) are key semiconductor devices which determine the receiver performance. Each PD of the dual PDs should realize high speed performance, high responsibility and high input power operation capability. Highly symmetrical characteristics between the two PDs should be also realized, thus the dual PDs are desired to be monolithically integrated to one chip. In this paper, we describe the design, fabrication, characteristics and reliability of monolithically integrated dual evanescently coupled waveguide photodiodes (EC-WG-PDs) for the purpose described above. The structure of the EC-WG-PDs offers the attractive advantages of high speed performance, high responsivity and high input power operation. Furthermore, their fabrication process is suitable for the integration of two PDs on one ship. First, the optimization was done for high products of 3-dB bandwidth and responsivity for 43-Gbps DPSK receivers. Excellent characteristics (50 GHz bandwidth with a responsivity of 0.95 A/W), and high reliability were demonstrated. The other type of optimization was done for ultra high speed operation up to 100-Gbps. The fabricated PDs exhibited the 3 dB-bandwidth of 80 GHz with a responsivity of 0.25 A/W. Furthermore, 43-Gbps RZ-DPSK receivers including the dual EC-WG-PDs based on the former optimization and differential transimpedance amplifiers (TIAs) newly developed for the purpose were also presented. Clear and symmetrical eye openings were observed for both ports. The OSNR characteristics exhibited 14.3 dB at a bit error rate of 10^-3 that is able to be recovery with FEC. These performances are enough for practical use in 43-Gbps RZ-DPSK systems.

This paper presents a quantitative analysis and design methodology of resistor-based phase error averaging scheme for precise multiphase generation. Unlike the previously reported works stating that more averaging simply achieves better linearity, the proposed analysis leads to the existence of the optimum number of averaging contributions by including the effect of the signal transition time. The developed model shows a good agreement with a Monte-Carlo circuit simulation. A test PLL with a 32-phase two-dimensional ring VCO, implemented in a 0.18 µm CMOS, generates monotonous 32 phases with the best linearity performance, showing an INL of +0.27/-1.0 LSB and a DNL of +0.37/-0.27 LSB at 1.2 GHz, and an INL of +0.23/-1.57 LSB and a DNL of +0.44/-0.44 LSB at 1.6 GHz.

In renewable power generators, because of high initial cost and duty cycle of systems, efficiency parameter has an important place. For this reason, line frequency controlled multilevel inverters are one of most proper choices for renewable power converters. Among these, diode-clamped multilevel inverter structures are one of most important and best efficient inverters. In this paper, a simple diode-clamped equivalent circuit for exploring the efficiency under resistive loads is proposed, and based on this simple circuit, the on-state power dissipation in improved and original diode-clamped multilevel inverter under resistive loads is analyzed. Then, comparative efficiency equations are extracted for inverters that use metal oxide semiconductor field-effect transistors (MOSFETs) and other p-n junction as switches. These equations enable us to have a better idea of conducting power dissipation in diode-clamped and help us to choose appropriate switches for having a lower on-state power dissipation. Some cases are studied and in the end it is proven that the calculated efficiency under resistive load is a boundary for inductive load with the same impedance in diode-clamped inverter with p-n junction switches. This means that calculating the efficiency under resistive loads enables us to approximately predict efficiency under inductive loads.

Due to the superlinear dependence of leakage power consumption on temperature, and spatial variations in on-chip thermal profiles, methods of leakage power estimation that are known to be accurate require detailed knowledge of thermal profiles. Leakage power depends on the integrated circuit (IC) thermal profile and circuit design style. Here, we show that piecewise linear models can be used to permit accurate leakage estimation over the operating temperature ranges of the ICs. We then show that for typical IC packages and cooling structures, a given amount of heat introduced at any position in the active layer will have a similar impact on the average temperature of the layer. These two observations support the proof that, for wide ranges of design styles and operating temperatures, extremely fast, coarse-grained thermal models, combined with piecewise linear leakage power consumption models, enable the estimation of chip-wide leakage power consumption. These results are further confirmed through comparisons with leakage estimates based on detailed, time-consuming thermal analysis techniques. Experimental results indicate that, when compared with a leakage analysis technique that relies on accurate spatial temperature estimation, the proposed technique yields a 59,259 to 1,790,000 speedup in estimating leakage power consumption, while maintaining accuracy.

A novel 3D RRAM concept using a stackable multi-layer 1TXR memory cell structure is proposed. The access transistor is fabricated in silicon, which has excellent affinity to the standard CMOS process. Using an 8-layer metal of stacked 1TXR (X=64) as an example, the density is over 260% higher than that of the conventional single layer 1T1R structure. Further, a corresponding operation algorithm is put forward, which can inhibit effectively mis-write and mis-read caused by sneaking current and reduce power consumption.

A Q-enhanced 8th order CMOS active bandpass filter is presented employing a novel two-stage self-calibration technique. The proposed active filter shows the better out-band attenuation performance than other reported CMOS active bandpass filters. The proposed calibration method enables the stable filtering operation affected by neither the input power variation nor the strong interference power. It is fabricated using 65 nm CMOS process. The measured 3 dB bandwidth is 54 MHz at 2.37 GHz. The insertion loss is 2.9 dB and the out-band attenuation is 27.5 dB at 15 MHz offset frequency. The performance of the filter remains unchanged for 5% supply voltage variations.

A mixed-mode high-speed binary phase-shift keying (BPSK) demodulator for IEEE802.15.3c mm-wave wireless personal area network (WPAN) application is realized with 0.18-µm CMOS process. The proposed demodulator scheme does not require any analog-to-digital converters (ADC) and, consequently, can have advantages over the conventional schemes for high-data-rate demodulation. The demodulator core consumes 53.8 mW from 2.5-V power supply while the chip area is 380500 µm². The fabricated chip is verified by 60-GHz wireless link tests with 1.6-Gb/s data.

This paper presents a voltage reference that utilizes the virtually diode-connected MOS transistors, biased in the weak-inversion region. The proposed architecture increases the gain of the feedback loop that consequently reduces the system sensitivity, and hence improves the PSRR. The circuit is designed and simulated in a standard 0.18 µm CMOS technology. The simulation results in HSPICE indicate the successful operation of the circuit as follows: the PSRR at DC frequency is 86 dB and for the temperature range from -55C to 125C, the variation of the output reference voltage is less than 66 ppm/C.

Scattering characteristics of a domain wall displacement detection (DWDD) disk with a control layer were investigated by finite-difference time-domain (FDTD) analysis. DWDD is one of the high-density storage technologies of magneto-optical (MO) disks and the control layer is used to suppress ghost signals due to a rear process. The effects of the control layer on the scattering characteristics were studied.