This paper proposes the overlapped block relaxation Newton method for greatly reducing the number of iterations needed for simulating large scale nonlinear circuits. The circuit is partitioned into subcircuits, i.e., overlapped blocks consisting of core nodes and overlapped nodes. The core nodes form the core circuit for each overlapped block and the overlapped nodes form the overlapped circuit. The Newton-Raphson method is applied to all overlapped blocks independently and the approximation vector for relaxation is determined by node voltages of core nodes. An overlapped circuit is considered to be the representative circuit of the outside circuit for the core circuit. Therefore, the accuracy of the approximation vector for relaxation may be improved and the number of relaxation steps may be greatly reduced. Core nodes are determined automatically by reflecting the circuit structure, then the overlapping level is determined automatically. We show that this method has good performance for simulating large scale circuits, and that it is faster than the nonlinear direct method which is used in standard circuit simulators.

This paper proposes a new approach for the development of a module generator that can parameterize both the size and the structure of layout. The proposed method acquires a design procedure from the design process of a designer, and reuses it to synthesize new layouts with different input parameters that affect the size or the structure of layout. In this method, a designer creates a module layout on a layout editor instead of writing a program. From his design process, a procedure to synthesize the layout is automatically derived. Then, it is generalized so that it could be valid under different values of input parameters. The generalized procedure is independent of design rules, and is capable of synthesizing error-free module layouts of different size and structure. Also, the procedure includes designer's requirements on how the layout should be designed. The experimental results of applying the approach for developing generators of analog device components show effectiveness of our approach.

We propose a new compaction problem that allows layout elements to have many shape possibilities. The objective of the problem is to find not only positions but also shapes of layout elements. We present an efficient method to solve the problem--compaction with shape optimization. This method simplifies the problem by considering the optimization of shapes only for the layout elements on a critical path. The layout is compacted step by step while optimizing the shapes of layout elements. Another importance of this compaction technique is that it makes layout to be "recyclable" for other set of device parameters. The experimental examples, which attempt shape optimization and recycle of analog layout, confirms the importance and efficiency of our method.

A method of driving the effects caused by finite input impedance and nonzero output impedance of functional building blocks into a frequency shift of transfer characteristics is proposed. The method is quite simple and systematic. The input and output impedances can have arbitrary values under a simple condition which meets the monolithic integration of circuits. The effects of non ideal input and output impedances are converted to a change of integrator gain leading to a simple frequency shift of circuits. The frequency shift can easily be adjusted by conventional methods. A typical example shows a remarkable effect of the method.

This paper proposes a constructive linearization method for transistor circuits based on a polynomial representation of nonlinear transfer functions. The nonlinear transfer functions for various configurations have been shown in a polynomial form. Then the results have been applied to several bipolar transistor circuits to exemplify the proposed designing method.

This paper describes an efficient slew rate enhancement technique especially suitable for an operational amplifier used in an LCD driver IC. This technique employs an input-dependent biasing without directly monitoring an input; instead, monitoring an output of the first stage of the amplifier. This enhancement technique is easily applied to a conventional two-stage operational amplifier and requires only 8 additional transistors to increase slew rates for both rising and falling edges. The bias currents of the first and the second stages are simultaneously controlled by this biasing. Experimental operational amplifiers with and without this enhancement have been fabricated to demonstrate the improvement of slew rate. Slew rates of 12.5V/µsec for the rising edge and 50V/µsec for the falling edge with a 100 pF load capacitance have been achieved by this technique, compared with slew rates of 0.3V/µsec for the rising edge and 5V/µsec for the falling edge in the conventional amplifier.

In this letter, we propose a simple voltage controlled oscillator (VCO) with circuitry combining a Miller integrator and an RS flip-flop circuit. With the VCO, the control voltage can be varied over a broad range, and the oscillation frequency varies in proportion to the control voltage. The maximum voltage is up to 1000 times the minimum, and the calculated design values and measured values agree well. This VCO can be applied to FM modulators, FSK modulators, and other systems.

An excitation signal for a synthesis filter plays an important role in producing high quality speech at a low bit rate. This paper presents a new efficient excitation model, Adaptive Density Pulse (ADP) , for low bit-rate speech coding. This ADP is a pulse train whose density (spacing interval) is constant within a subframe but can be varied subframe by subframe. First, the ADP excitation signal is defined. A procedure for finding the optimal ADP excitation is presented. Some results on investigating the effects of the ADP parameters on the synthesized speech quality are discussed. ADP excitation is introduced to the CELP (Code Excited Linear Prediction) coding method to improve speech quality at bit rates around 4 kbps. A CELP coder with an ADP (ADP-CELP) is described. ADP excitation makes it possible for the CELP coder to follow transient portions of speech signals. Also ADP excitation can reduce computational complexity in selecting the best excitation from a codebook, which has been the primary drawback of CELP. The number of multiplications can be reduced to the order of 1/D² by utilizing the sparseness of ADP excitation, where D is the pulse interval. The authors evaluated the speech quality of a 4 kbps ADP-CELP coder by computer simulation. ADP excitation improved the performance of conventional CELP in segmental SNR.

A systematic theory of the optimum multi-path interpolation using parallel filter banks is presented with respect to a family of n-dimensional signals which are not necessarily band-limited. In the first phase, we present the optimum spacelimited interpolation functions minimizing simultaneously the wide variety of measures of error defined independently in each separate range in the space variable domain, such as 8 8 pixels, for example. Although the quantization of the decimated sample values in each path is contained in this discussion, the resultant interpolation functions possess the optimum property stated above. In the second phase, we will consider the optimum approximation such that no restriction is imposed on the supports of interpolation functions. The Fourier transforms of the interpolation functions can be obtained as the solutions of the finite number of linear equations. For a family of signals not being band-limited, in general, this approximation satisfies beautiful orthogonal relation and minimizes various measures of error simultaneously including many types of measures of error defined in the frequency domain. These results can be extended to the discrete signal processing. In this case, when the rate of the decimation is in the state of critical-sampling or over-sampling and the analysis filters satisfy the condition of paraunitary, the results in the first phase are classified as follows: (1) If the supports of the interpolation functions are narrow and the approximation error necessarily exists, the presented interpolation functions realize the optimum approximation in the first phase. (2) If these supports become wide, in due course, the presented approximation satisfies perfect reconstruction at the given discrete points and realizes the optimum approximation given in the first phase at the intermediate points of the initial discrete points. (3) If the supports become wider, the statements in (2) are still valid but the measure of the approximation error in the first phase at the intermediate points becomes smaller. (4) Finally, those interpolation functions approach to the results in the second phase without destroying the property of perfect reconstruction at the initial discrete points.

For symmetric cryptosystems, their transformations should have nonlinear elements to be secure against various attacks. Several nonlinearity criteria have been defined and their properties have been made clear. This paper focuses on, among these criteria, the propagation criterion (PC) and the strict avalanche criterion (SAC), and makes a further investigation of them. It discusses the sets of Boolean functions satisflying the PC of higher degrees, the sets of those satisfying the SAC of higher orders and their relationships. We give a necessary and sufficient condition for an n-input Boolean function to satisfy the PC with respect to a set of all but one or two elements in {0,1}ⁿ{(0,...,0)}. From this condition, it follows that, for every even n 2, an n-input Boolean function satisfies the PC of degree n 1 if and only if it satisfies the PC of degree n. We also show a method that constructs, for any odd n 3, n-input Boolean functions that satisfy the PC with respect to a set of all but one elements in {0,1}ⁿ{(0,...,0)}. This method is a generalized version of a previous one. Concerned with the SAC of higher orders, it is shown that the previously proved upper bound of the nonlinear order of Boolean functions satisfying the criterion is tight. The relationships are discussed between the set of n-input Boolean functions satisfying the PC and the sets of those satisfying the SAC.

There have been many investigations of mutual synchronization of oscillators. In this article, N oscillators with the same natural frequencies mutually coupled by one resistor are analyzed. In this system, various synchronization phenomena can be observed because the system tends to minimize the current through the coupling resistor. When the nonlinear characteristics are third-power, we can observe N-phase oscillation, and this system can take (N 1)! phase states. When the nonlinear characteristics are fifth-power, we can observe (N 1),(N 2)3 and 2-phase oscillations as well as N-phase oscillations and we can get much more phase states from this system than that of the system with third-power nonlinear characteristics. Because of their coupling structure and huge number of steady states of the system, our system would be a structural element of cellular neural networks. In this study, it is confirmed that our systems can stably take huge number of phase states by theoretical analysis, computer calculations and circuit experiments.

This letter proposes a time varying step size normalized LMS (TVS-NLMS) algorithm for adaptive echo canceler structures. Proposed algorithm reduces distortion during double talk, without increasing the computational cost nor decreasing the convergence rate of the normalized LMS algorithm significantly. Simulation results using white noise and actual speech signals confirm the desirable features of the proposed scheme.

In this letter, we demonstrate an experimental CMOS neural circuit towards an understanding of how particular computations can be performed by a T-Model neural network. The architecture and a digital hardware implementation of the learning T-Model network are presented. Our experimental results show that the T-Model allows immense collective network computations and powerful learning.

An efficient algorithm is given for finding all solutions of piecewise-linear resistive circuits containing nonseparable transistor models such as the Gummel-Poon model or the Shichman-Hodges model. The proposed algorithm is simple and can be easily programmed using recursive functions.

It is shown by the derivation of solution methods for an elementary optimization problem that the stochastic relaxation in image analysis, the Potts neural networks for combinatorial optimization and interior point methods for nonlinear programming have common formulation of their dynamics. This unification of these algorithms leads us to possibility for real time solution of these problems with common analog electronic circuits.

This paper presents improvement of data error rate against burst noise by using both chip interleaving and hard limiter in direct sequence spread spectrum (DS/SS) communication systems. Chip interleaving, which is a unique method of DS/SS systems, is effective when burst noise power is small. However, when the burst noise power is large, date error rate is degraded. While, though hard limiter suppresses burst noise power, it gives little effectiveness when the burst noise length is long. Using chip interleaving and hard limiter together, as they work complementary, stable and considerable improvement of data error rate is achieved.