In this paper, a novel charge coupled device matched filter (CCD-MF) for Electrical code division multiplexing (ECDM) decoder is proposed and experimentally demonstrated. Simulation results clarify the influence of low charge transfer efficiency (CTE) and the validity of a parallel CCD-MF we proposed. A 15-channel ECDM system using a 2 Gchip/s, 2-parallel CCD-MF is experimentally demonstrated.

We performed the (NH4)2S surface treatments before Al2O3 deposition to improve the Al2O3/III-Nitride interface quality in Al2O3/AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOSHFETs). Interface state density at the Al2O3/GaN interface was decreased by the (NH4)2S treatment. The hysteresis width in ID-VGS and gm-VGS characteristics of the Al2O3/AlGaN MOSHFETs with the (NH4)2S treatment was smaller than that without the (NH4)2S treatment. In addition, transconductance (gm) decrease at a large gate voltage was relaxed by the (NH4)2S treatment. We also performed ultraviolet (UV) illumination during the (NH4)2S treatment for further improvement of the Al2O3/III-Nitride interface quality. Interface state density of the Al2O3/GaN MOS diodes with the UV illumination was smaller than that without the UV illumination.

Recently, server virtualization technology, which is one of the key technologies to support cloud computing, has been making progress and gaining in maturity, resulting in an increase in the provision of cloud-based services and the integration of servers in enterprise networks. However, the progress in network virtualization technology, which is needed for the efficient and effective construction and operation of clouds, is lagging behind. It is only recently that all the required technical areas have started to be covered. This paper identifies network-related issues in cloud environments, describes the needs for network virtualization, and presents the recent trends in, and application fields of, network virtualization technology.

This paper is a report on a high ESD breakdown-voltage InP HBT transimpedance amplifier IC for optical video distribution systems. To make ESD breakdown-voltage higher, we designed ESD protection circuits integrated in the TIA IC using base-collector/base-emitter diodes of InP HBTs and resistors. These components for ESD protection circuits have already existed in the employed InP HBT IC process, so no process modifications were needed. Furthermore, to meet requirements for use in optical video distribution systems, we studied circuit design techniques to obtain a good input-output linearity and a low-noise characteristic. Fabricated InP HBT TIA IC exhibited high human-body-model ESD breakdown voltages (±1000 V for power supply terminals, ±200 V for high-speed input/output terminals), good input-output linearity (less than 2.9-% duty-cycle-distortion), and low noise characteristic (10.7 pA/ averaged input-referred noise current density) with a -3-dB-down higher frequency of 6.9 GHz. To the best of our knowledge, this paper is the first literature describing InP ICs with high ESD-breakdown voltages.

We report on the fabrication and analysis of basic digital circuits containing InAs nanowire transistors on a host substrate. The nanowires were assembled at predefined positions by means of electric field-assisted self-assembly within each run generating numerous circuits simultaneously. Inverter circuits composed of two separated nanowire transistors forming a driver and an active load have been fabricated. The inverter circuits exhibit a gain (>1) in the MHz regime and a time constant of about 0.9 ns. A sample & hold core element is fabricated based on an InAs nanowire transistor connected to a hold capacitor, both on a Silicon and an InP isolating substrate, respectively. The low leakage read-out of the hold capacitor is done by InP-based metal-insulator heterojunction FET grown on the same substrate prior to nanowire FET fabrication. Experimental operation of the circuit is demonstrated at 100 MHz sampling frequency. The presented approach enables III/V high-speed, low-voltage logic circuits on a wide variety of host substrates which may be up scaled to high volume circuits.

Person re-identification is challenging due to illumination changes and viewpoint variations in the multi-camera environment. In this paper, we propose a novel spatial pyramid color representation (SPCR) and a local region matching scheme, to explore person appearance for re-identification. SPCR effectively integrates color layout into histogram, forming an informative global feature. Local region matching utilizes region statistics, which is described by covariance feature, to find appearance correspondence locally. Our approach shows robustness to illumination changes and slight viewpoint variations. Experiments on a public dataset demonstrate the performance superiority of our proposal over state-of-the-art methods.

Novel thermopiles based on modulation doped AlGaAs/InGaAs and AlGaN/GaN heterostructures are proposed and developed for the first time, for uncooled infrared FPA (Focal Plane Array) image sensor application. The high responsivity with the high speed response time are designed to 4,900 V/W with 110 µs for AlGaAs/InGaAs, and to 460 V/W with 9 µs for AlGaN/GaN thermopiles, respectively. Based on integrated HEMT-MEMS technology, the AlGaAs/InGaAs 3232 matrix FPAs are fabricated to demonstrate its enhanced performances by black body measurement. The technology presented here demonstrates the potential of this approach for low-cost uncooled infrared FPA image sensor application.

This paper presents measurement results of bit error rate (BER) and soft error rate (SER) improvement on 150-nm FD-SOI 7T/14T (7-transistor/ 14-transistor) SRAM test chips. The reliability of the 7T/14T SRAM can be dynamically changed by a control signal depending on an operating condition and application. The 14T dependable mode allocates one bit in a 14T cell and improves the BER in a read operation and SER in a retention state, simultaneously. We investigate its error rate mitigating mechanisms using Synopsys TCAD simulator. In our measurements, the minimum operating voltage was improved by 100 mV, the alpha-induced SER was suppressed by 80.0%, and the neutron-induced SER was decreased by 34.4% in the 14T dependable mode over the 7T normal mode.

A new clock gating circuit suitable for shift register is presented. The proposed clock gating circuit that consists of basic NOR gates is low power and small area. The power consumption of a 16-bit shift register implemented with the proposed clock gating circuit is about 66% lower than that found when using the conventional design.

Current collapse of AlGaN/GaN heterostructure field-effect transistors (HFETs) formed on qualified epitaxial layers on Si substrates was successfully suppressed using graded field-plate (FP) structures. To improve the reproducibility of the FP structure manufacturing process, a simple process for linearly graded SiO2 profile formation was developed. An HFET with a graded FP structure exhibited a significant decrease in an on-resistance increase ratio of 1.16 even after application of a drain bias of 600 V.

A complete analysis of GaN-based structures with very promising characteristics for future optical waveguide devices, such as modulators, is presented. First the material growth was optimized for low dislocation density and surface roughness. Optical measurements demonstrate excellent waveguide properties in terms of index and temperature dependence while planar propagation losses are below 1 dB/cm. Bias was applied on both sides of the epitaxially grown films to evaluate the refractive index dependence on reverse voltage and a variation of 2.10-3 was found for 30 V. These results support the possibility of using structures of this type for the fabrication of modulator devices such as Mach-Zehnder interferometers.

Template matching for image sequences captured with a moving camera is very important for several applications such as Robot Vision, SLAM, ITS, and video surveillance systems. However, it is difficult to realize accurate template matching using only visual feature information such as HSV histograms, edge histograms, HOG histograms, and SIFT features, because it is affected by several phenomena such as illumination change, viewpoint change, size change, and noise. In order to realize robust tracking, structure information such as the relative position of each part of the object should be considered. In this paper, we propose a method that considers both visual feature information and structure information. Experiments show that the proposed method realizes robust tracking and determine the relationships between object parts in the scenes and those in the template.

This paper describes high-temperature electron transport properties of AlGaN-channel HEMT fabricated on a free-standing AlN substrate, estimated at temperatures between 25 and 300. The AlGaN-channel HEMT exhibited significantly reduced temperature dependence in DC and RF device characteristics, as compared to those for the conventional AlGaN/GaN HEMT, resulting in larger values in both saturated drain current and current gain cutoff frequency at 300. Delay time analyses suggested that the temperature dependence of the AlGaN-channel HEMT was primarily dominated by the effective electron velocity in the AlGaN channel. These results indicate that an AlGaN-channel HEMT fabricated on an AlN substrate is promising for high-performance device applications at high temperatures.

Reduction of the intensity noise in semiconductor lasers is an important subject for the higher performance of an application. Simultaneous usage of the superposition of high frequency current and the electric negative feedback loop was proposed to suppress the noise for the higher power operation of semiconductor lasers. Effective noise reduction of more than 25 dB with 80 mW operation was experimentally demonstrated.

In resetting attacks against a proof system, a prover or a verifier is reset and enforced to use the same random tape on various inputs as many times as an adversary may want. Recent deployment of cloud computing gives these attacks a new importance. This paper shows that argument systems for any NP language that are both resettably-sound and resettable zero-knowledge are possible by a constant-round protocol in the BPK model. For that sake, we define and construct a resettably-extractable conditional commitment scheme.

This paper proposes a new first-scan method for two-scan labeling algorithms. In the first scan, our proposed method first scans every fourth image line, and processes the scan line and its two neighbor lines. Then, it processes the remaining lines from top to bottom one by one. Our method decreases the average number of times that must be checked to process a foreground pixel will; thus, the efficiency of labeling can be improved.

In recent years, local pattern based features have attracted increasing interest in object detection and recognition systems. Local Binary Pattern (LBP) feature is widely used in texture classification and face detection. But the original definition of LBP is not suitable for human detection. In this paper, we propose a novel feature named gradient local binary patterns (GLBP) for human detection. In this feature, original 256 local binary patterns are reduced to 56 patterns. These 56 patterns named uniform patterns are used for generating a 56-bin histogram. And gradient value of each pixel is set as the weight which is always same in LBP based features in histogram calculation to computing the values in 56 bins for histogram. Experiments are performed on INRIA dataset, which shows the proposal GLBP feature is discriminative than histogram of orientated gradient (HOG), Semantic Local Binary Patterns (S-LBP) and histogram of template (HOT). In our experiments, the window size is fixed. That means the performance can be improved by boosting methods. And the computation of GLBP feature is parallel, which make it easy for hardware acceleration. These factors make GLBP feature possible for real-time pedestrian detection.

This paper presents a novel CMOS readout circuit for satellite infrared time delay and integration (TDI) arrays. An integrate-while-read method is adopted, and a dead-pixel-elimination circuit for solving a critical problem of the TDI scheme is integrated within a chip. In addition, an adaptive charge capacity control method is proposed to improve the signal-to-noise ratio (SNR) for low-temperature targets. The readout circuit was fabricated with a 0.35-µm CMOS process for a 5004 mid-wavelength infrared (MWIR) HgCdTe detector array. Using the circuit, a 90% background-limited infrared photodetection (BLIP) is satisfied over a wide input range (∼200–330 K), and the SNR is improved by 11 dB for the target temperature of 200 K.

This paper proposes a new generative model which can deal with rotational data variations by extending Separable Lattice 2-D HMMs (SL2D-HMMs). In image recognition, geometrical variations such as size, location and rotation degrade the performance. Therefore, the appropriate normalization processes for such variations are required. SL2D-HMMs can perform an elastic matching in both horizontal and vertical directions; this makes it possible to model invariance to size and location. To deal with rotational variations, we introduce additional HMM states which represent the shifts of the state alignments among the observation lines in a particular direction. Face recognition experiments show that the proposed method improves the performance significantly for rotational variation data.

Clock gating is supported by commercial tools as a power optimization feature based on the guard signal described in HDL (structural method). However, the identification of control signals for gated registers is hard and designer-intensive work. Besides, since the clock gating cells also consume power, it is imperative to minimize the number of inserted clock gating cells and their switching activities for power optimization. In this paper, we propose an automatic multi-stage clock gating algorithm with ILP (Integer Linear Programming) formulation, including clock gating control candidate extraction, constraints construction and optimum control signal selection. By multi-stage clock gating, unnecessary clock pulses to clock gating cells can be avoided by other clock gating cells, so that the switching activity of clock gating cells can be reduced. We find that any multi-stage control signals are also single-stage control signals, and any combination of signals can be selected from single-stage candidates. The proposed method can be applied to 3 or more cascaded stages. The multi-stage clock gating optimization problem is formulated as constraints in LP format for the selection of cascaded clock-gating order of multi-stage candidate combinations, and a commercial ILP solver (IBM CPLEX) is applied to obtain the control signals for each register with minimum switching activity. Those signals are used to generate a gate level description with guarded registers from original design, and a commercial synthesis and layout tools are applied to obtain the circuit with multi-stage clock gating. For a set of benchmark circuits and a Low Density Parity Check (LDPC) Decoder (6.6k gates, 212 F.F.s), the proposed method is applied and actual power consumption is estimated using Synopsys NanoSim after layout. On average, 31% actual power reduction has been obtained compared with original designs with structural clock gating, and more than 10% improvement has been achieved for some circuits compared with single-stage optimization method. CPU time for optimum multi-stage control selection is several seconds for up to 25k variables in LP format. By applying the proposed clock gating, area can also be reduced since the multiplexors controlling register inputs are eliminated.