An adaptive fuzzy network (AFN) is described that can be used to implement most of fuzzy logic functions. We introduce a learning algorithm largely borrowed from backpropagation algorithm and train the AFN system for several typical fuzzy problems. Simulations show that an adaptive fuzzy network can be implemented with the proposed network and algorithm, which would be impractical for a conventional fuzzy system.

A 0.1-µm-gate CMOS/SIMOX has been successfully fabricated using high quality SIMOX substrates. The propagation delay time for the 0.1-µm-gate CMOS/SIMOX is not so noticeable due to the parasitic resistance of the source and drain regions. We anticipate 0.1-µm-gate CMOS/SIMOX devices with a delay time of less than 20 ps at a supply voltage of 1.5 V by reducing the remaining parasitic resistance and capacitances.

Rate based control is a promising way to achieve an efficient packet transmission especially in high speed packet switching networks where round trip delay is much larger than packet transmission time. Although inappropriate tuning for the parameters, increasing and decreasing factors, of the rate control function causes the performance degradation, most of the previous works so far have not studied the effect of the parameters on the performance. In this paper, we investigate the effect of the rate control parameters on the throughput under the condition that the packet loss probability is kept below a specific value, say 10-6. For this purpose, we build a queueing model and carry out a transient analysis to examine the dynamic behavior of the queue length at an intermediate node in a high speed network suffering from large propagation delay. Numerical examples exploit the optimal value of the parameters when one or two source-destination pairs transmit packets. We also discuss the effect of the propagation delay on the performance. Our model can be applicable to investigate the performance of various kinds of rate-based congestion control when the relation between the congestion measure and the rate control mechanism is given explicitly.

Dynamic performance of ultra-thin SIMOX (Separation by IMplanted OXgen) CMOS circuits has been studied using ring oscillators. A novel concept of current-delay product, along with an equivalent linear resistance of MOSFETs, is applied for deriving effective load capacitance of near 0.1 µm gate CMOS circuits. Calculation results showed quatitative agreement with measurement data. It was found that the gate-fringing capacitance limits the delay time is the case of under 0.2 µm gate-length. The lower bound of power-delay product of SIMOX/SOI is expected as low as 0.2 fJ for the gate length of 0.15 µm at the supply voltage of 1.5 V.

In high-speed packet networks, protocol processing overhead time becomes remarkable in determining the system performance. In this paper, we present a new Selective-Repeat ARQ scheme (called Block SR-ARQ sheme), in which a packet is transmitted or retransmitted in the same way as basic SR-ARQ scheme, but a single acknowledgement packet is used to acknowledge a block of packets. The maximum number of packets acknowledged by an acknowledgement packet is defined as block size. We analyze the system throughput and the average packet delay over the system, and the accuracy of approximately analyzed results is validated by simulation. Furthermore, we show that there exists an optimal block size which obtains both the maximum throughput and the minimum average packet delay.

This paper describes a new timing calibration method for IC testers that uses a Timing Calibration Device (TCD). The TCD is a chip fabricated using the same process the device to be tested. Since the TCD has the same assignment pins as the LSI memory device under test (called the "MUT"), it enables an IC tester to evaluate the timing accuracy at the input/output terminal of MUT. The block-select-access time of a 1 K ECL RAM, which is less than 3.0 nanoseconds, has been accurately measured using this device. A timing-calibration subsystem is proposed for IC testers as an application of the TCD. Such a device would achieve precise measurement of high-speed LSI memory devices.

CFGs (context-free grammars) with various types of memory are introduced and their generative capacities are investigated. For an automata-theoretic characterization, a new type of automaton called partitioning automaton is introduced and it is shown that the class of languages generated by CFGs with memory type X is equal to the class of languages accepted by partitioning automata of type X.

Rate-based congestion/flow control is a promising way to achieve high throughput in high speed packet-switching networks. We consider a rate-based congestion control to aim at obtaining high throughput and fair sharing of the communication resources. In the scheme, each intermediate node informs its congestion status to the source node. Two kinds of control packets are used for this mechanism. One (a choke packet) is to throttle the rate and another (a loosen packet) is to allow increase of the rate. The source node initiates transmission with a low rate and increases the rate slowly to avoid a rapid increase of the packet queueing at an intermediate node. When the source node receives a choke packet, it decreases the rate rapidly to relieve congestion as soon as possible. The source node upon receipt a loosen packet increases the rate slowly again. We develop a queueing model to investigate the parameter settings to provide a good performance via simulation. The increasing and decreasing parameters of the rate control function are first investigated in various load conditions. We next examine the effect of the queue-length threshold value for the indication of congestion at the intermediate node. The numerical results indicate that the threshold value should be small to obtain a good performance. We finally introduce a technique which accurately recognizes congestion and inhibits an acceptable queueing of the packets at intermediate nodes.

A newly developed planar inductor and its application to dc-dc converters are described. The planar inductor consists of a planar spiral coil and soft magnetic sheets, it has a small size (11110.8mm), 33µH inductance and a maximum quality factor of 14. The step down chopper dc-dc converter has been developed by using planar inductor, which has small size (20154mm), 5V-2W typical output and output power/volume ratio of 1.7W/cc. The switching converter can be miniaturized by using the planar inductor.

This paper describes the superior performances of the NAND EEPROM. Those are 1) a very small cell area: 4.83 µm2 using 0.7 µm design rule, 2) small block size for erasing: 4 Kbyte block erasing for 4 M-bit NAND EEPROM, 3) high speed programming: 180 nsec per byte for 4 M-bit NAND EEPROM, 4) large number of erase/program endurance cycles: more than 105 cycles for 4 M-bit NAND EEPROM. These extended performances coincide with the requirement for the EEPROM to replace magnetic memories such as hard and floppy disks. Especially, it is shown that NAND EEPROM has the capability to enlarge the erase/program endurance up to 3.6108 cycles. This endurance is a result of the erase and program mechanism of the NAND EEPROM cell. Fowler-Nordheim (F-N) tunneling currents flow from the substrate to the floating gate during programming and opposite currents flow during erasing. This bi-polarity F-N tunneling erase/program operation extends the life time of the tunnel oxide which results in an improved endurance.

This paper describes a high-performance, low-power, mixed-signal Digital Signal Processor (DSP) and its application to a single-chip Vector Sum Excited Linear Prediction (VSELP) speech codec. The DSP consists of a 25MIPS, 24bit floating point core-DSP; 13bit oversampling ADC/DAC; 6 KW data ROM; and 3.5 KW data RAM. The total transistor counts of the DSP is 1.3 million and its chip size is 11.0 mm15.8 mm. Unique design techniques are used to reduce the power dissipation, such as the programmable machine cycle time control and the clock supply control scheme in the core-DSP, the address detection for on-chip data ROM/RAM, and the shared-hardware design for digital filters of ADC and DAC. As an application of the DSP, the VSELP speech codec, which is the standard speech codec for the North American and Japanese digital cellular telephone system, has been implemented in a single-chip. Owing ti the salient architecture design and the program optimization techniques, sufficient quality was obtained in the codec at performance of 16.4 MIPS with low-power dissipation of 490 mW.

GaAs MESFETs with a p-buffer layer (or a buried p-layer) are important devices for high-speed GaAs ICs. To study what conditions are required as a good substrate for ICs, we have investigated, by two-dimensional simulation, small-signal parameters and drain-current transients of GaAs MESFETs with a p-buffer layer on the semi-insulating substrate. It is shown that the introduction of a p-buffer layer is effective to improve the transconductance and the cuttoff frequeycy. These parameters are not degrade even if the p-layer doping is increased and a neurtral p-region exists. It is also shown that drain-current drifts and hysteresis in I-V curves can occur in a case with a p-buffer layer, too. It is concluded that the introduction of a relatively highly-doped p-layer on a substrate with low acceptor and electron trap (EL2) densities is effective to realize the stable and high performance of GaAs MESFETs.

An improved array architecture to realize fast access, low power dissipation, and wide operating margin, for the 16 Mbit DRAM is proposed. A high speed access is obtained by the fully embedded sense drive scheme for the RAS access time (tRAC), and the special page mode with the hierarchical I/O data bus lines and multi-purpose-register (MPR) for the column address access time (tCAA). A low power dissipation and wide operating margin are obtained by the improved twisted-bit-line (TBL) architecture with double dummy canceling. The 16 Mb DRAM using these architectures has 38 ns tRAC, 14 ns tCAA and 75 mA power dissipation at the typical condition.

This paper describes a new 0.5-µm MOS current mode Logic (MCML) circuit that operates at 1.2 V, while maintaining high-speed performance, comparable with that of bipolar current mode circuits. An MCML circuit consists of differentially operating MOS transistors and a constant current source. Its performance at low voltage is compared with that of a CMOS circuit and bipolar current mode circuits. At 1.2 V, the MCML circuit has 90% the delay time of a CMOS circuit at 3.3 V. Delay times of CML and ECL circuits are 80% and 67% of that of the MCML circuit, respectively. Power of a 0.5-µm 500-MHz MCML circuit at 1.2 V, however, is 29%, 67% and 46%, of that of CMOS at 3.3 V, CML at 1.8 V and ECL at 2.6 V, respectively. Power-delay products of 500-MHz CMOS, CML and ECL circuits (normalized by the MCML circuit power-delay product) are 3.8, 1.2 and 1.5, respectively. MCML circuits can be used to construct any logic circuits. High-speed compact circuits are feasible, because MCML circuits output complementary signals. The delay time of an MCML full adder is only 200 ps. This is three times faster than that of a 3.3-V CMOS full adder. An MCML circuit has good characteristics and is widely applicable to logic circuits, so it is a useful circuit for producing sub-GHz processors.

In this paper, a new M-estimation technique for the linear prediction analysis of speech is proposed. Since in the conventional linear prediction (CLP) method the obtained estimates are very much affected by the large amplitude residual parts, in the proposed method we use a loss function which assigns large weighting factor for small amplitude residuals and small weighting factor for large amplitude residuals which is for instance caused by the pitch excitations. The loss function is based on the assumption that the residual signal has an independent and identical t-distribution t(α) with α degrees of freedom. The efficiency of this new estimator depends on α. When α=, we get the CLP method. When the proposed method with small α is applied to the problems of estimating the formant frequencies and bandwidths of the synthetic speech by finding the roots of the prediction polynomial, we can achieve a more accurate and a smaller standard deviation (SD) estimate than that with large α. When the signal is very spiky, the proposed method can ahieve more efficient and accurate estimates than that with robust linear prediction (RBLP) method. The loss function is modified in the similar manner as the autocorrelation method. The solution is calculated by the Newton-Raphson iteration technique. The simulation results show that only few iterations are needed to reach a stationary point, the stationary point is always a local minimum and the obtained prediction filter is always minimum phase. Preliminary experiments on the human speech data indicate that the obtained results are insensitive to the placement of the analysis window and a higher spectral resolution than the CLP and RBLP method can be achieved.

After the intrinsic pulsed light illumination, a transient negative photoconductivity (TRANP) was observed in silicon doped with gold. The ambient temperature dependence of the TRANP-current was measured and compared with the simulated results obtained by solving rate equations. The temperature dependence of the peak value of the TRANP-current was in agreement with the simulated result. The activation energy of gold acceptor level obtained from the time constant in the recovery process was also consistent with the simulation. It was cleared from this result that the recovery process is dominated by the electron re-emission from gold acceptor level to the conduction band. It was concluded that the occurrence of the TRANP is well explained by using our model proposed before.

We will introduce W-trees of a W-graph which is a graph containing wild components. A wild component is an incompletely defined subgraph which is known to be a tree but what kind of the tree is unspecified. W-tree is defined as a set of edges and vertices of wild components obtained from a non-sigular major submatrix of a W-incidence matrix. The properties of a W-tree are useful for studying linear independent W-cutsets and so on in a W-graph.

The mode partition noise of 1.3µm distributed feedback laser diodes (DFB LD's), which is induced by the externally reflected light, is studied experimentally and numerically. The mode partition noise is evaluated by the k-value. It is observed that the mode parition noise monotonically increases with the DC bias current when the reflected light affects DFB LD's and the DC bias current is above the threshold current. From the dependence of the k-value on the external power reflection coefficient, it is observed that the k-value dramatically increases when the external power reflection coefficient is above a value which differs from LD to LD. This is closely related to the fact that the tolerance to the externally reflected light depends on the threshold gain difference between the main mode and the dominant side mode.

In this paper, we analyze a photodetection process of new kind theoretically, which transforms a coherent state of light so as to lead to nonstandard property, namely, sub-Poissonian distribution of its output photoelectron during its photodetection process. The properties of the photoelectron distribution are studied used as preamplifiers of both direct-detection and homodyne detection cases.

A specification formalism for business application software is presented. Our approach is to investigate specification documents which are actually used in development projects of business applications in banking, insurance, and government systems. Since the specification documents are prepared mainly for users' review for the developing software, the representation of the documents is designed to be easy to understand for users, only in business terminology without losing a certain level of formality. Also, to avoid redundancy of the specification, there are some implicit assumptions in the specification. We have analyzed some commonality of these assumptions hidden in specification documents and are trying to construct a language by formalizing the underlying system model.