This paper presents a new structure for noise and echo cancelers based on a combined fast abaptive algorithm. The main purpose of the new structure is to detect both the double-talk and the unknown path change. This goal is accomplished by using two adaptive filters. A main adaptive filter Fn, adjusted only in the non-double-talk period by the normalized LMS algorithm, is used for providing the canceler output. An auxiliary adaptive filter Ff, adjusted by the fast RLS algorithm, is used for detecting the double-talk and obtaining a near optimum tap-weight vector for Fn in the initialization period and whenever the unknown path has a sudden or fast change. The proposed structure is examined through computer simulation on a noise cancellation problem. Good cancellation performance and stable operation are obtained when signal is a speech corrupted by a white noise, a colored noise and another speech signal. Simulation results also show that the proposed structure is capable of distinguishing the near-end signal from the noise path change and quickly tracking this change.

The applicability of Dynamic Channel Assignment methods to a Reuse Partitioning system in cellular radio systems is investigated in this paper. The investigations indicate that such a system has a tendency to increase the difference between blocking probability for the partitioning two coverage areas in comparison with the conventional Reuse Partitioning system employing Fixed Channel Assignment method. Two schemes using new Channel Rearrangement algorithms are also proposed in order to alleviate the difference as a disadvantage which gives unequal service to the system. The simulation results show that the proposed schemes are able to reduce the difference significantly while increasing the carried traffic by 10% as compared with the conventional system.

The subject is the horizontal coil's temperature rise in DY for high frequency by being unavoidable for the tendency of more information on display monitor equipments. Writers made the temperature-balance model from a point of view that this temperature rise is coming from the heat rise and the conductivity, and we expressed the temperature rise of DY by using amount of the heat rise and conductivity characteristics of each element. Also, we indicated the method to decide about the selection of the wire size of coils, the section area and deflection sensitivity, with regard to reducing the temperature rise. We confirmed the effect of the temperature rise reduction by about 9 on products, under the condition of 64 kHz horizontal frequency.

A 3.3 V single power-supply 64 Mb flash memory with a DBL programming scheme has been developed and fabricated with 0.4 µm CMOS technology. 50 ns access time and 256 b erase/programming unit-capacity have been achieved by using hierarchical word- and bit-line structures and DBL programming scheme. Furthermore in order to lower operating voltage the HiCR cell is used. The chip size is 19.3 mm13.3 mm.

Multimedia communication services are being made available with the advent of broadband optical fiber networks. As many different services will be accommodated in such networks, network survivability has been recognized to be a crucial concern. In this paper, we propose a new restoration algorithm for ATM networks providing multimedia services. Our proposed restoration algorithm adopts the message bundling scheme of the Multi-Destination Flooding (MDF) algorithm which was previously proposed for STM-based networks to handle catastrophic failures such as multiple link and node failures. Virtual Paths (VP) with the same communication speed are bundled and Operation Administration and Maintenance (OAM) cells are used for communication of restoration messages. In addition, the following modifications are made on the original MDF to improve restoration performance. The pre-cancellation scheme is adopted to arbitrate reservation contention to realize high restoration ratio. The dual queue scheme is applied to avoid congestion of restoration messages. Moreover, the connection control scheme for VPI connections is proposed to prevent alternative routes from being misconnected. This paper describes the design concept of our restoration algorithm, processes in each restoration phase, and the performance evaluation by computer simulation.

In this paper, we develop parallel scrambling techniques for the distributed sample scrambling (DSS), which are directly applicable to the bit- and multibit-interleaved multiplexing environments. We first consider how to realize PSRGs, parallel samplings and parallel corrections for the multibit-parallel DSS (MPDSS), which are the fundamental problems in realizing the MPDSS scramblers and descramblers. The results are summarized in three sets of theorems, and a corollary is attached to each theorem to specifically handle the case of the parallel DSS (PDSS). The theorems and corollaries are supported by examples that demonstrate the relevant MPDSS scramblers and descramblers.

This paper presents a layered hierarchical switching-software technology, which is based on an object-oriented design approach, that improves software reusability and productivity. This technology enables a non-stop, service-enhanceable software environment (called NOSES), which satisfies customer demands for quick provisioning of new service features without interrupting service, and which improves software reliability. This technology was developed as part of our overall plan to establish a communications software platform that can be customized for use by various communications systems, such as STM, ATM, and IN. The developed non-stop service enhanceable software techniques are call-recovery restart, system file update, and on-line partial file modification; they were achieved by using dynamic program modification. A system file update inevitably affects calls in service, despite efforts to save in-service calls by copying the call data from the old file to the new one. We have therefore developed a different approach: on-line partial-file modification. Our prototype switching system has proven the effectiveness of this modification method and has shown that it can cover a limited range of service feature additions (which meets customer demands for quick service provisioning), as well as all bug fixes (which can lead to higher software reliability due to not using conventional machine code for software patching), without interrupting service. This paper describes on-line partial-file modification, which can be applied to communications systems that require resident program modification or initialization without program loading; that is, the program exists permanently in main memory. An evaluation of this approach also showed that the productivity of service-layer software increases about two times and that the total increase in systems development productivity is about 25%.

Recently, through high speed computer networks, multifarious information such as text, moving and still images, video, voice and control data is available. There is a natural demand to store such multimedia data in databases to facilitate their reuse in a wide variety of applications. Therefore, important research issues pertain to the investigation of appropriate database systems in multimedia computer network environments. In this paper, we first discuss the required technologies for multimedia information systems. Then we look at many multimedia information services through computer networks, and consider the importance of storing and effectively reusing such available multimedia data. To facilitate developing databases for use in these environments, we discuss the evolution of the notion of database systems. Finally, we demonstrate, as practical examples of such database systems, two prototype systems that we are currently implementing, i.e., the campus wide news on demand system and the ASN. 1 database system.

This paper discussed a distributed processing architecture for a virtual space teleconferencing system. Virtual space teleconferencing is a promising application field for networked virtual environments. People in different places will be able to meet each other in a virtual teleconferencing room and proceed with various cooperative tasks. When such a system creates a realistic virtual environment, it can be referred to as a "Teleconferencing with realistic sensations" system. Further more, as the conference environment can be shared by a number of users, it is possible to perform various kinds of cooperative work using the system. In this paper, the architecture for networked multi-user virtual space systems are classified, and then a case study is described for building a proposed teleconferencing system. The system reproduces a 3D image of each conference participant in a virtual meeting room. Compared with the former system, the new system can deal with more than three participants at the same time and can connect them through commercial telephone lines. Based on the virtual world database management structure, the system was classified as a central server system. However, a central server architecture limits the number of conference sites. We confirmed that the system can serve up to 14 sites using multi-modal interaction without significant latency in operation from summational experiments. Then, introducing some assumptions to the results, we have proposed processing model of the system. The results of model could describe the experimental results and we could indicate roughy estimated system capacity to realize a requaied system performance.

This paper gives several explicit formulas for the waiting times in each stage in an alternating-service, two-stage tandem queue (M/G/1 type queue) with a gate in the first stage and server vacations (or setup time). These formula are obtained by using simple conversion relationships between the performance measures. This study has been motivated by the performance evaluation of call (packet or message) processing in telecommunication switching systems.

An adaptive joint-process IIR filter with generalized lattice structure is constructed. This filter can borrow both FIR and IIR features and simultaneously holds the well-known merits of lattice structure.

Current testing has been proposed as an alternative technique for testing fully CMOS digital LSIs. Current testing has higher fault coverage than conventional stuck-at fault (SAF) testing and is more economical because it detects a wide range of faults and requires fewer test vectors than does SAF testing. We have proposed a current testing that measures the integral of the power supply current (IDD) during one clock period including the switching current. Since this method cannot be affected by the switching current, it can be used to test an LSI operating at a relatively high clock freuqnecy. This paper presents an improved current testing method for CMOS digital and analog LSIs. The method uses two current values (i.e., an upper limit and a lower limit) and judges the circuit under test to be faulty if the measured IDD is outside these limits. The proposed current testing is evaluated here for some kinds of faults (e.g., the bridging fault and the breaking fault) in digital and mixed-signal LSIs, and its efficiency of the current testing using SPICE3.

In this paper, we evaluate the performance of handoff schemes in microcellular personal communication systems (PCS) which cater to both pedestrian and vehicular users. Various performance parameters, including blocking of new calls,channel utilization, handoff blocking and call termination probabilities for each user type are evaluated. We study different queuing disciplines for handoff calls and their impact on system performance. We also study the tradeoff in handoff blocking and call termination probabilities between user types as the handoff traffic carried by the system from each user type is varied.

This paper studies the problem of reconstructing a planar surface from stereo images of multiple feature points that are known to be coplanar in the scene. We present a direct method by applying maximum likelihood estimation based on a statistical model of image noise. The significant fact about our method is that not only the 3-D position of the surface is reconstructed accurately but its reliability is also computed quantitatively. The effectiveness of our method is demonstrated by doing numerical simulation.

Concerning the complexity of tree drawing, the following result of Supowit and Reingold is known: the problem of minimum drawing binary trees under several constraints is NP-complete. There remain, however, many open problems. For example, is it still NP-complete if we eliminate some constraints from the above set? In this paper, we treat tree-structured diagrams. A tree-structured diagrm is a tree with variably sized rectangular nodes. We consider the layout problem of tree-structured diagrams on Z2 (the integral lattice). Our problems are different from that of Supowit and Reingold, even if our problems are limited to binary trees. In fact, our set of constraints and that of Supowit and Reingold are incomparable. We show that a problem is NP-complete under a certain set of constraints. Furthermore, we also show that another problem is still NP-complete, even if we delete a constraint concerning with the symmetry from the previous set of constraints. This constraint corresponds to one of the constraints of Supowit and Reingold, if the problem is limited to binary trees.

We developed an on-chip memory tester macro using a microprogram ROM BIST circuit. Only slight modification of address buffers, data bus I/O circuits and control clock generators of the memory core circuits was required to implement this BIST macro. We fabricated a 1 Mb DRAM with the BIST, and experimental results showed that the measured shmoo plot of VCC versus the cycle time by the BIST closely agreed with that of a memory tester. Disagreement was caused by test address signal set-up time delay and VOH/VOL differences in both test conditions. The BIST macro will be especially useful for design-for-testability of embedded memories.

The stability of a high-resistivity load SRAM cell using thin-film SOI MOSFET's was investigated as compared with bulk-Si MOSFET's. In SOI MOSFET's back-gate-bias effect was suppressed by indirect application of back-gate-bias to the channel region through the thick buried oxide. The Vt shifts were reduced to be 10% and 14% of that in bulk-Si MOSFET's in partially and fully depleted devices, respectively. The reduction of back-gate-bias effect provides improvement of "high" output voltage and gain in the enhancement-enhancement (EE) inverter in a high-resistivity load SRAM cell, thereby offering improved cell stability. It was demonstrated by using partially depleted SOI SRAM cells that non-destructive reading was obtained even at a low drain voltage of 1.4 V without gate-potential boost, which was much smaller than the operation limit in a bulk Si SRAM with the same patterns and dimensions used as a reference. This implies that SOI devices can also offer low-voltage operation even in TFT-load cells used in up-to-date high-density SRAM's. These results suggest that thin-film SOI MOSFET's have a superior potential of low-voltage operation expected for further scaled devices and/or for portable systems in a forthcoming multimedia era.

This paper presents the concept of k-FR circuits. The controllability of such a circuit is high due to its special structure. It is shown that all stuck-at faults and stuck-open faults in a k-FR circuit can be detected and located by k(k1)1 test vectors under the highly observable condition which assumes the output of every gate to be observable. k is usually two or three. This paper also presents an algorithm for converting an arbitrary combinational circuit into a k-FR circuit. A k-FR circuit is easy to test when using technologies such as the electron-beam probing, the current measurement, or the CrossCheck testability solution.

This paper deals with the problems in testing large mixed-signal ICs. To help generating test patterns of these larger mixed-signal circuits for a functional test, a fast fault simulation algorithm and a fault model voltage stuck-at fault" which the algorithm is based on, are proposed. A voltage stuck-at fault is that a signal line sticks its voltage level at a certain constant. Under an assumption that blocks in a circuit are designed as identically current-independent, i.e. their input impedance can be regarded as infinite and their output impedance as zero, fault simulation can be realized by the event driven method and the concurrent method and can detect voltage stuck-at faults. These methods are essential for digital fault simulation and very effective to high speed simulation, although they were impossible for an analog or mixed-signal circuit by a conventional algorithm. Furthermore, the efficiency of the simulation is improved because I/O relation of blocks is approximated to a stepwise linear function. The above techniques and methods make fault simulation for a mixed-signal circuit possible in practical use. Actually, a fault simulator was implemented, then some test circuits were simulated. The simulator is really faster than conventional simulation based on circuit simulation. Next, fault analysis was applied to several bipolar ICs to verify the validity of the fault model voltage stuck-at faults". Analyses of open and short faults between terminals of transistors and resistors show that this fault model has sufficient coverage (more than 50%) to test mixed-signal circuit.

This paper presents techniques used in combinational test generation for multiple stuck-at faults using the parallel vector pair analysis. The techniques accelerate a test generation procedure previously proposed and reduce the number of test vectors generated, while higher fault coverage is derived. The first technique proposed in this paper, which is applied at the first phase of test generation, is rules of ordering vector pairs to be analyzed, to derive high fault coverage without repeating the analysis for the same vector pairs. The second one is to generate new vector pairs for undetected faults, instead of random vector pairs. Both techniques are based on the idea that faults close to primary inputs should be detected earlier than close to primary outputs. The third technique proposed here is how to construct vector pairs from one input vector in order to accelerate test generation especially for circuits with many primary inputs and scan flip-flops. Experimental results for bench-mark circuits show the effectiveness of the techniques.