Key fabrication technology for the Pt/TiO2-x/TiO2/TiO2+x/Pt nano-film memristor is investigated, including preparing platinum (Pt) electrodes and TiO2-x/TiO2/TiO2+x nano-films. The effect of oxygen flow rate and deposition rate during fabrication on O:Ti ratio of thin films is demonstrated. The fabricated nano-films with different oxygen concentration are validated by the analyzed results from X-ray photoelectron spectroscopy (XPS). The obtained memristor device shows the typical resistive switching behavior and nonvolatile memory effects. An analytical device model for Pt/TiO2-x/TiO2/TiO2+x/Pt nano-film memristor is developed based on the fundamental linear relationships between drift-diffusion velocity and the electric field, and boundary conditions are also incorporated in this model. This model is able to predict the relation between variables in the form of explicit formula, which is very critical in memristor-based circuit designs. The measurement results from real devices validate the proposed analytical device model. Some deviations of the model from the measured data are also analyzed and discussed.

We have derived the physics-based equivalent circuit model of a semiconductor-integrated bow-tie antenna (BTA) for expressing its impedance and radiation characteristics as a terahertz transmitter. The equivalent circuit branches and components, consisting of 16 RLC parameters are determined based on electromagnetic simulations. All the values of the circuit elements are identified using the particle swarm optimization (PSO) that is one of the modern multi-purpose optimization methods. Moreover, each element value can also be explained by the structure of the semiconductor-integrated BTA, the device size, and the material parameters.

Gallium nitride high electron mobility transistors (GaN HEMTs) were developed for millimeter-wave high power amplifier applications. The device with a gate length of 80 nm and an InAlN barrier layer exhibited high drain current of more than 1.2 A/mm and high breakdown voltage of 73,V. A cut-off frequency $ extrm{f}_{ extrm{T}}$ of 113,GHz and maximum oscillation frequency $ extrm{f}_{ extrm{max}}$ of 230,GHz were achieved. The output power density reached 1 W/mm with a linear gain of 6.4,dB at load-pull measurements at 90,GHz. And we extracted equivalent circuit model parameters of the millimeter-wave InAlN/GaN HEMT and showed that the model was useful in simulating the millimeter-wave power performance. Also, we report a preliminary constant bias stress test result.

E-band communication is allocated to the frequency bands of 71-76 and 81-86GHz. Radio-frequency (RF) front-end components for E-band communication have been realized using compound semiconductor technology. To realize a CMOS LNA for E-band communication, we propose a gain-boosted cascode amplifier (GBCA) stage that simultaneously provides high gain and stability. Designing an LNA from scratch requires considerable time because the tuning of matching networks with consideration of the parasitic elements is complicated. In this paper, we model the characteristics of devices including the effects of their parasitic elements. Using these models, an optimizer can estimate the characteristic of a designed LNA precisely without electromagnetic simulations and gives us the design values of an LNA when the layout constraint is ignored. Starting from the values, a four-stage LNA with a GBCA stage is designed very easily even though the layout constraint is considered and fabricated by a 65nm LP CMOS process. The fabricated LNA is measured, and it is confirmed that it achieves 18.5GHz bandwidth and over 24.3dB gain with 50.6mW power consumption. This is the first LNA to achieve a gain bandwidth of over 300GHz in the E-band among the LNAs utilizing any kind of semiconductor technologies. In this paper, we have proved that CMOS technology, which is suitable for baseband and digital circuitry, is applicable to a communication system covering the entire E-band.

Due to the increasing need for low-power circuits in mobile applications, numerous leakage and performance optimization techniques are being used in modern ICs. In the present paper, we propose a novel transistor-level technique to reduce leakage current while maintaining drive current. By slightly increasing the channel length at the edge of a device that exploits the edge effect, a leakage-optimized transistor can be produced. By using TCAD simulations, we analyze edge-length-biased transistors and then propose the optimal transistor shape for minimizing Ioff with the same or higher Ion current. Results show that by replacing all standard cells with their leakage-optimized counterparts, we can save up to 17% of the leakage in average for a set of benchmark circuits.

This paper presents a precise characterization of high-frequency characteristics of intrinsic channel of FinFET. For the de-embedding of the parasitics attached to the source, drain and gate terminals, it proposes special calibration patterns which can place the reference surface just beside the intrinsic part of the FinFET. It compares the measured S parameter data up to 40 GHz with the device simulation and shows good matching. The experimental data of the through pattern also confirms the accuracy of the de-embedded parasitics and extracted intrinsic part of FinFET.

Device modeling techniques for high-frequency circuits operating at over 100 GHz are presented. We have proposed the bond-based design as an accurate high-frequency circuit design method. Because layout parasitic extractions (LPE) are not required in the bond-based design, it can be applied high-frequency circuit design at over 100 GHz. However, customized device models are indispensable for the bond-based design. In this paper, device modeling techniques for high-frequency circuit design using the bond-based design are proposed. The customized device model for MOSFETs, transmission lines and pads are introduced. By using customized device models, the difference between the simulated and measured gains of an amplifier is improved to less than 0.6 dB at 120 GHz.

An on-chip Charged Device Model (CDM) ESD protection method for RF ICs is proposed in a 0.13 µm RF process and evaluated by using very fast Transmission Line Pulse (vf-TLP) system. Key design parameters such as triggering voltage (Vt1) and the oxide breakdown voltage from the vf-TLP measurement are used to design input ESD protection circuits for a RF test chip. The characterization and the behavior of a Low Voltage Triggered Silicon Controlled Rectifier (SCR) which used for ESD protection clamp under vf-TLP measurements are also reported. The results measured by vf-TLP system showed that the triggering voltage decreased and the second breakdown current increased in comparison with the results measured by a standard 100 ns TLP system. From the HBM/ CDM testing, the RF test chip successfully met the requested RF ESD withstand level, HBM 1 kV, MM 100 V and CDM 500 V.

This paper deals with a simple and practical power loss analysis simulator, which can actually estimate the total power losses of three phase voltage-fed Auxiliary resonant commutation pole snubber assisted soft switching inverter as well as hard-switching inverter. In order to estimate the switching power losses and conduction power losses of switching semiconductor power devices (IGBTs), which are incorporated into the inverters, the proposed practical simulator is making use of feasible switching power loss data tables and conduction power loss data tables, which are accumulated from the measured voltage and current operating waveforms of power semiconductor switching devices. The practical effectiveness of feasible simulation technique and power loss evaluations for power electronic conversion circuits and systems are confirmed by the simulation and experimental results basis under the conditions of soft switching and hard switching sinusoidal PWM schemes.

A simple modeling technique for symmetric inductors is proposed. Using the proposed technique, all model parameters for an equivalent circuit of symmetric inductors are easily calculated from geometric, process and substrate resistance parameters without using electromagnetic (EM) simulators. Comparison of simulated results with measured results verifies the effectiveness of the proposed modeling technique up to 5 GHz with center-tapped or non-center-tapped configurations.

New physical models, algorithms, and parameters are needed to accurately model emerging silicon-on-insulator (SOI) devices. The modeling approaches for various emerging SOI technologies are discussed in this paper.

A compact MMIC power amplifier which delivers P1dB of 25.8 dBm (380 mW) at 40 GHz has been developed. To make the chip width narrower, only one unit block using two parallel HEMTs is applied for a power stage. For achieving broadband interstage matching when using wide gate-width unit devices in the power stage, a new configuration of a unit block which contains a shunt capacitance is proposed.

Simple and scalable device-modeling techniques for inductors and capacitors are described. All model parameters are calculated from geometric parameters of the device, process parameters of the technology, and a substrate resistance parameter. Modeling techniques for other devices, such as resistors, varactor diodes, pads and MOSFETs, are also described. Some simulation results using the proposed device-modeling techniques are compared with measured results and they indicate adequacy of the proposed device-modeling techniques.

This paper reports the application results of the state-of-the-art advanced process/device modeling to the 0.13 [µm] CMOS design solution. It has been demonstrated that the S/D-extension junction depth, the well profile, the channel profile and the drive current of the 0.13 [µm] CMOS can be predicted with reasonable accuracy. Further model improvement is required to predict the ΔL and the Vt-Lg characteristics of the devices with the tilted pocket I/I more accurately. It is quite beneficial to construct several design maps by using the state-of-the-art advanced TCAD in a 'carpet bombing' way in the early stage of the development of new generation CMOS.

After a short introduction to the different requirements to and techniques for wavelength conversion, focus is on cross-gain and cross-phase modulation in SOA based converters. Aspects like jitter accumulation, regeneration and conversion to the same wavelength is discussed. It is predicted that jitter accumulation can be minimised while also assuring a high extinction ratio by using a 9-10 dB ratio between the signal and CW power. Using this guideline simulations show that 20 cross-gain modulation converters can be cascaded at 10 Gbit/s with only 20 ps of accumulated jitter and an extinction ratio of 10 dB. The regenerative capabilities of the cross-phase converters are described and verified experimentally at 20 Gbit/s. By controlling the input power to an EDFA, the noise redistribution and improvement of the signal-to-noise ratio is demonstrated. In a similar experiment at 2.5 Gbit/s, the regeneration causes a reduction of the required input power to an in-line EDFA of 6 dB for a power penalty of 1 dB at a bit error rate of 10-9. If two converters are concatenated the power requirement is reduced 8 dB. Obviously, the power reduction allows for longer spans between in-line EDFAs. A simple scheme for regeneration without wavelength conversion is assessed at 2.5 Gbit/s resulting in 4.5 dB lower required EDFA input power. The scheme is characterised by a quasi-digital transfer function that is ideal for regeneration. A combination of cross-gain and cross-phase conversion is used to perform conversion to the same wavelength at 20 Gbit/s. The insertion penalty for this dual-stage converter is below 2 dB and is mainly caused by extinction ratio degradation from the cross-gain converter. Finally, a new device for all-optical wavelength conversion has been proposed and 2.5 Gbit/s operation has been simulated with good results.

After a short introduction to the different requirements to and techniques for wavelength conversion, focus is on cross-gain and cross-phase modulation in SOA based converters. Aspects like jitter accumulation, regeneration and conversion to the same wavelength is discussed. It is predicted that jitter accumulation can be minimised while also assuring a high extinction ratio by using a 9-10 dB ratio between the signal and CW power. Using this guideline simulations show that 20 cross-gain modulation converters can be cascaded at 10 Gbit/s with only 20 ps of accumulated jitter and an extinction ratio of 10 dB. The regenerative capabilities of the cross-phase converters are described and verified experimentally at 20 Gbit/s. By controlling the input power to an EDFA, the noise redistribution and improvement of the signal-to-noise ratio is demonstrated. In a similar experiment at 2.5 Gbit/s, the regeneration causes a reduction of the required input power to an in-line EDFA of 6 dB for a power penalty of 1 dB at a bit error rate of 10-9. If two converters are concatenated the power requirement is reduced 8 dB. Obviously, the power reduction allows for longer spans between in-line EDFAs. A simple scheme for regeneration without wavelength conversion is assessed at 2.5 Gbit/s resulting in 4.5 dB lower required EDFA input power. The scheme is characterised by a quasi-digital transfer function that is ideal for regeneration. A combination of cross-gain and cross-phase conversion is used to perform conversion to the same wavelength at 20 Gbit/s. The insertion penalty for this dual-stage converter is below 2 dB and is mainly caused by extinction ratio degradation from the cross-gain converter. Finally, a new device for all-optical wavelength conversion has been proposed and 2.5 Gbit/s operation has been simulated with good results.

TCAD (Technology Computer Aided Design) is the simulation of semiconductor processes and devices. Despite twenty years of development, there are still many TCAD skeptics. This paper will discuss some of the problems and limitations of TCAD, present some successful examples of its use, and discuss future simulation needs from a user's perspective. A key point is that the time pressures in modern semiconductor technology development often dictate the use of simple models for approximate results.

Measurement-based mathematical modeling is an attractive approach for simulating, accurately and efficiently, circuits based on active devices from a diverse range of constantly evolving processes and technologies. The principle of the measurement-based approach is that it is often most practical to characterize the device with various high-frequency measurements, and then mathematically transform the data to produce predictive device dynamical models for small-signal (linear) and large-signal (nonlinear) circuit design purposes. There are many mathematical, physical, and measurement considerations, however, that must be incorporated into any sound framework for successful measurement-based modeling. This paper will review some foundations of the subject and discuss some future trends. Review topics include constructing nonlinear constitutive relations from linear data parameterized by operating point and conservation laws including terminal charge conservation and energy conservation. Recent advances and trends will be discussed, such as pulsed I-V and pulsed S-parameter characterization with implications for electro-thermal and dispersive dynamical models, nonlinear wave-form measurements, and the relationship to some black-box behavioral modeling approaches.