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[Keyword] UMP(318hit)

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  • 6T-8T Hybrid SRAM for Lower-Power Neural-Network Processing by Lowering Operating Voltage Open Access

    Ji WU  Ruoxi YU  Kazuteru NAMBA  

     
    LETTER-Computer System

      Pubricized:
    2024/05/20
      Vol:
    E107-D No:9
      Page(s):
    1278-1280

    This letter introduces an innovation for the heterogeneous storage architecture of AI chips, specifically focusing on the integration of six transistors(6T) and eight transistors(8T) hybrid SRAM. Traditional approaches to reducing SRAM power consumption typically involve lowering the operating voltage, a method that often substantially diminishes the recognition rate of neural networks. However, the innovative design detailed in this letter amalgamates the strengths of both SRAM types. It operates at a voltage lower than conventional SRAM, thereby significantly reducing the power consumption in neural networks without compromising performance.

  • Optimization of Multi-Component Olfactory Display Using Inkjet Devices Open Access

    Hiroya HACHIYAMA  Takamichi NAKAMOTO  

     
    PAPER-Multimedia Environment Technology

      Pubricized:
    2023/12/28
      Vol:
    E107-A No:8
      Page(s):
    1338-1344

    Devices presenting audiovisual information are widespread, but few ones presenting olfactory information. We have developed a device called an olfactory display that presents odors to users by mixing multiple fragrances. Previously developed olfactory displays had the problem that the ejection volume of liquid perfume droplets was large and the dynamic range of the blending ratio was small. In this study, we used an inkjet device that ejects small droplets in order to expand the dynamic range of blending ratios to present a variety of scents. By finely controlling the back pressure using an electro-osmotic pump (EO pump) and adjusting the timing of EO pump and inkjet device, we succeeded in stabilizing the ejection of the inkjet device and we can have large dynamic range.

  • Determination Method of Cascaded Number for Lumped Parameter Models Oriented to Transmission Lines Open Access

    Risheng QIN  Hua KUANG  He JIANG  Hui YU  Hong LI  Zhuan LI  

     
    PAPER-Electronic Circuits

      Pubricized:
    2023/12/20
      Vol:
    E107-C No:7
      Page(s):
    201-209

    This paper proposes a determination method of the cascaded number for lumped parameter models (LPMs) of the transmission lines. The LPM is used to simulate long-distance transmission lines, and the cascaded number significantly impacts the simulation results. Currently, there is a lack of a system-level determination method of the cascaded number for LPMs. Based on the theoretical analysis and eigenvalue decomposition of network matrix, this paper discusses the error in resonance characteristics between distributed parameter model and LPMs. Moreover, it is deduced that optimal cascaded numbers of the cascaded π-type and T-type LPMs are the same, and the Γ-type LPM has a lowest analog accuracy. The principle that the maximum simulation frequency is less than the first resonance frequency of each segment is presented. According to the principle, optimal cascaded numbers of cascaded π-type, T-type, and Γ-type LPMs are obtained. The effectiveness of the proposed determination method is verified by simulation.

  • Simulation of Scalar-Mode Optically Pumped Magnetometers to Search Optimal Operating Conditions Open Access

    Yosuke ITO  Tatsuya GOTO  Takuma HORI  

     
    INVITED PAPER

      Pubricized:
    2023/12/04
      Vol:
    E107-C No:6
      Page(s):
    164-170

    In recent years, measuring biomagnetic fields in the Earth’s field by differential measurements of scalar-mode OPMs have been actively attempted. In this study, the sensitivity of the scalar-mode OPMs under the geomagnetic environment in the laboratory was studied by numerical simulation. Although the noise level of the scalar-mode OPM in the laboratory environment was calculated to be 104 pT/$\sqrt{\mathrm{Hz}}$, the noise levels using the first-order and the second-order differential configurations were found to be 529 fT/cm/$\sqrt{\mathrm{Hz}}$ and 17.2 fT/cm2/$\sqrt{\mathrm{Hz}}$, respectively. This result indicated that scalar-mode OPMs can measure very weak magnetic fields such as MEG without high-performance magnetic shield roomns. We also studied the operating conditions by varying repetition frequency and temperature. We found that scalar-mode OPMs have an upper limit of repetition frequency and temperature, and that the repetition frequency should be set below 4 kHz and the temperature should be set below 120°C.

  • A Capacitance Varying Charge Pump with Exponential Stage-Number Dependence and Its Implementation by MEMS Technology

    Menghan SONG  Tamio IKEHASHI  

     
    PAPER-Electronic Circuits

      Pubricized:
    2023/06/26
      Vol:
    E107-C No:1
      Page(s):
    1-11

    A novel charge pump, Capacitance Varying Charge Pump (CVCP) is proposed. This charge pump is composed of variable capacitors and rectifiers, and the charge transfer is attained by changing the capacitance values in a manner similar to peristaltic pumps. The analysis of multi-stage CVCP reveals that the output voltage is exponentially dependent on the stage number. Thus, compared with the Dickson charge pump, this charge pump has an advantage in generating high voltages with small stages. As a practical example of CVCP, we present an implementation realized by a MEMS (Micro-Electro-Mechanical Systems) technology. Here, the variable capacitor is enabled by a comb-capacitor attached to a high-quality factor resonator. As the rectifier, a PN-junction diode formed in the MEMS layer is used. Simulations including the mechanical elements are carried out for this MEMS version of CVCP. The simulation results on the output voltage and load characteristics are shown to coincide well with the theoretical estimations. The MEMS CVCP is suited for MEMS devices and vibration energy harvesters.

  • Adaptive K-Repetition Transmission with Site Diversity Reception for Energy-Efficient Grant-Free URLLC in 5G NR

    Arif DATAESATU  Kosuke SANADA  Hiroyuki HATANO  Kazuo MORI  Pisit BOONSRIMUANG  

     
    PAPER

      Pubricized:
    2023/10/11
      Vol:
    E107-B No:1
      Page(s):
    74-84

    The fifth-generation (5G) new radio (NR) standard employs ultra-reliable and low-latency communication (URLLC) to provide real-time wireless interactive capability for the internet of things (IoT) applications. To satisfy the stringent latency and reliability demands of URLLC services, grant-free (GF) transmissions with the K-repetition transmission (K-Rep) have been introduced. However, fading fluctuations can negatively impact signal quality at the base station (BS), leading to an increase in the number of repetitions and raising concerns about interference and energy consumption for IoT user equipment (UE). To overcome these challenges, this paper proposes novel adaptive K-Rep control schemes that employ site diversity reception to enhance signal quality and reduce energy consumption. The performance evaluation demonstrates that the proposed adaptive K-Rep control schemes significantly improve communication reliability and reduce transmission energy consumption compared with the conventional K-Rep scheme, and then satisfy the URLLC requirements while reducing energy consumption.

  • Evaluating Energy Consumption of Internet Services Open Access

    Leif Katsuo OXENLØWE  Quentin SAUDAN  Jasper RIEBESEHL  Mujtaba ZAHIDY  Smaranika SWAIN  

     
    INVITED PAPER

      Pubricized:
    2023/06/15
      Vol:
    E106-B No:11
      Page(s):
    1036-1043

    This paper summarizes recent reports on the internet's energy consumption and the internet's benefits on climate actions. It discusses energy-efficiency and the need for a common standard for evaluating the climate impact of future communication technologies and suggests a model that can be adapted to different internet applications such as streaming, online reading and downloading. The two main approaches today are based on how much data is transmitted or how much time the data is under way. The paper concludes that there is a need for a standardized method to estimate energy consumption and CO2 emission related to internet services. This standard should include a method for energy-optimizing future networks, where every Wh will be scrutinized.

  • Single-Power-Supply Six-Transistor CMOS SRAM Enabling Low-Voltage Writing, Low-Voltage Reading, and Low Standby Power Consumption Open Access

    Tadayoshi ENOMOTO  Nobuaki KOBAYASHI  

     
    PAPER-Electronic Circuits

      Pubricized:
    2023/03/16
      Vol:
    E106-C No:9
      Page(s):
    466-476

    We developed a self-controllable voltage level (SVL) circuit and applied this circuit to a single-power-supply, six-transistor complementary metal-oxide-semiconductor static random-access memory (SRAM) to not only improve both write and read performances but also to achieve low standby power and data retention (holding) capability. The SVL circuit comprises only three MOSFETs (i.e., pull-up, pull-down and bypass MOSFETs). The SVL circuit is able to adaptively generate both optimal memory cell voltages and word line voltages depending on which mode of operation (i.e., write, read or hold operation) was used. The write margin (VWM) and read margin (VRM) of the developed (dvlp) SRAM at a supply voltage (VDD) of 1V were 0.470 and 0.1923V, respectively. These values were 1.309 and 2.093 times VWM and VRM of the conventional (conv) SRAM, respectively. At a large threshold voltage (Vt) variability (=+6σ), the minimum power supply voltage (VMin) for the write operation of the conv SRAM was 0.37V, whereas it decreased to 0.22V for the dvlp SRAM. VMin for the read operation of the conv SRAM was 1.05V when the Vt variability (=-6σ) was large, but the dvlp SRAM lowered it to 0.41V. These results show that the SVL circuit expands the operating voltage range for both write and read operations to lower voltages. The dvlp SRAM reduces the standby power consumption (PST) while retaining data. The measured PST of the 2k-bit, 90-nm dvlp SRAM was only 0.957µW at VDD=1.0V, which was 9.46% of PST of the conv SRAM (10.12µW). The Si area overhead of the SVL circuits was only 1.383% of the dvlp SRAM.

  • Basic Study of Micro-Pumps for Medication Driven by Chemical Reactions

    Mizuki IKEDA  Satomitsu IMAI  

     
    BRIEF PAPER

      Pubricized:
    2022/11/28
      Vol:
    E106-C No:6
      Page(s):
    253-257

    We have developed and evaluated a prototype micro-pump for a new form of medication that is driven by a chemical reaction. The chemical reaction between citric acid and sodium bicarbonate produces carbon dioxide, the pressure of which pushes the medication out. This micropump is smaller in size than conventional diaphragm-type micropumps and is suitable for swallowing.

  • Evaluation of Performance and Power Consumption on Supercomputer Fugaku Using SPEC HPC Benchmarks

    Yuetsu KODAMA  Masaaki KONDO  Mitsuhisa SATO  

     
    PAPER

      Pubricized:
    2022/12/12
      Vol:
    E106-C No:6
      Page(s):
    303-311

    The supercomputer, “Fugaku”, which ranked number one in multiple supercomputing lists, including the Top500 in June 2020, has various power control features, such as (1) an eco mode that utilizes only one of two floating-point pipelines while decreasing the power supply to the chip; (2) a boost mode that increases clock frequency; and (3) a core retention feature that turns unused cores to the low-power state. By orchestrating these power-performance features while considering the characteristics of running applications, we can potentially gain even better system-level energy efficiency. In this paper, we report on the performance and power consumption of Fugaku using SPEC HPC benchmarks. Consequently, we confirmed that it is possible to reduce the energy by about 17% while improving the performance by about 2% from the normal mode by combining boost mode and eco mode.

  • Clustering-Based Neural Network for Carbon Dioxide Estimation

    Conghui LI  Quanlin ZHONG  Baoyin LI  

     
    LETTER-Intelligent Transportation Systems

      Pubricized:
    2022/08/01
      Vol:
    E106-D No:5
      Page(s):
    829-832

    In recent years, the applications of deep learning have facilitated the development of green intelligent transportation system (ITS), and carbon dioxide estimation has been one of important issues in green ITS. Furthermore, the carbon dioxide estimation could be modelled as the fuel consumption estimation. Therefore, a clustering-based neural network is proposed to analyze clusters in accordance with fuel consumption behaviors and obtains the estimated fuel consumption and the estimated carbon dioxide. In experiments, the mean absolute percentage error (MAPE) of the proposed method is only 5.61%, and the performance of the proposed method is higher than other methods.

  • APVAS: Reducing the Memory Requirement of AS_PATH Validation by Introducing Aggregate Signatures into BGPsec

    Ouyang JUNJIE  Naoto YANAI  Tatsuya TAKEMURA  Masayuki OKADA  Shingo OKAMURA  Jason Paul CRUZ  

     
    PAPER

      Pubricized:
    2023/01/11
      Vol:
    E106-A No:3
      Page(s):
    170-184

    The BGPsec protocol, which is an extension of the border gateway protocol (BGP) for Internet routing known as BGPsec, uses digital signatures to guarantee the validity of routing information. However, the use of digital signatures in routing information on BGPsec causes a lack of memory in BGP routers, creating a gaping security hole in today's Internet. This problem hinders the practical realization and implementation of BGPsec. In this paper, we present APVAS (AS path validation based on aggregate signatures), a new protocol that reduces the memory consumption of routers running BGPsec when validating paths in routing information. APVAS relies on a novel aggregate signature scheme that compresses individually generated signatures into a single signature. Furthermore, we implement a prototype of APVAS on BIRD Internet Routing Daemon and demonstrate its efficiency on actual BGP connections. Our results show that the routing tables of the routers running BGPsec with APVAS have 20% lower memory consumption than those running the conventional BGPsec. We also confirm the effectiveness of APVAS in the real world by using 800,000 routes, which are equivalent to the full route information on a global scale.

  • Short Lattice Signature Scheme with Tighter Reduction under Ring-SIS Assumption

    Kaisei KAJITA  Go OHTAKE  Kazuto OGAWA  Koji NUIDA  Tsuyoshi TAKAGI  

     
    PAPER

      Pubricized:
    2022/09/08
      Vol:
    E106-A No:3
      Page(s):
    228-240

    We propose a short signature scheme under the ring-SIS assumption in the standard model. Specifically, by revisiting an existing construction [Ducas and Micciancio, CRYPTO 2014], we demonstrate lattice-based signatures with improved reduction loss. As far as we know, there are no ways to use multiple tags in the signature simulation of security proof in the lattice tag-based signatures. We address the tag-collision possibility in the lattice setting, which improves reduction loss. Our scheme generates tags from messages by constructing a scheme under a mild security condition that is existentially unforgeable against random message attack with auxiliary information. Thus our scheme can reduce the signature size since it does not need to send tags with the signatures. Our scheme has short signature sizes of O(1) and achieves tighter reduction loss than that of Ducas et al.'s scheme. Our proposed scheme has two variants. Our scheme with one property has tighter reduction and the same verification key size of O(log n) as that of Ducas et al.'s scheme, where n is the security parameter. Our scheme with the other property achieves much tighter reduction loss of O(Q/n) and verification key size of O(n), where Q is the number of signing queries.

  • mPoW: How to Make Proof of Work Meaningful

    Takaki ASANUMA  Takanori ISOBE  

     
    PAPER

      Pubricized:
    2022/11/09
      Vol:
    E106-A No:3
      Page(s):
    333-340

    Proof of Work (PoW), which is a consensus algorithm for blockchain, entails a large number of meaningless hash calculations and wastage of electric power and computational resources. In 2021, it is estimated that the PoW of Bitcoin consumes as much electricity as Pakistan's annual power consumption (91TWh). This is a serious problem against sustainable development goals. To solve this problem, this study proposes Meaningful-PoW (mPoW), which involves a meaningful calculation, namely the application of a genetic algorithm (GA) to PoW. Specifically, by using the intermediate values that are periodically generated through GA calculations as an input to the Hashcash used in Bitcoin, it is possible to make this scheme a meaningful calculation (GA optimization problem) while maintaining the properties required for PoW. Furthermore, by applying a device-binding technology, mPoW can be ASIC resistant without the requirement of a large memory. Thus, we show that mPoW can reduce the excessive consumption of both power and computational resources.

  • Pumping Lemmas for Languages Expressed by Computational Models with Registers

    Rindo NAKANISHI  Yoshiaki TAKATA  Hiroyuki SEKI  

     
    PAPER

      Pubricized:
    2022/10/14
      Vol:
    E106-D No:3
      Page(s):
    284-293

    Register automaton (RA), register context-free grammar (RCFG) and register tree automaton (RTA) are computational models with registers which deal with data values. This paper shows pumping lemmas for the classes of languages expressed by RA, RCFG and RTA. Among them, the first lemma was already proved in terms of nominal automata, which is an abstraction of RA. We define RTA in a deterministic and bottom-up manner. For these languages, the notion of ‘pumped word’ must be relaxed in such a way that a pumped subword is not always the same as the original subword, but is any word equivalent to the original subword in terms of data type defined in this paper. By using the lemmas, we give examples of languages that do not belong to the above-mentioned classes of languages.

  • Compressed Sensing EEG Measurement Technique with Normally Distributed Sampling Series

    Yuki OKABE  Daisuke KANEMOTO  Osamu MAIDA  Tetsuya HIROSE  

     
    LETTER-Measurement Technology

      Pubricized:
    2022/04/22
      Vol:
    E105-A No:10
      Page(s):
    1429-1433

    We propose a sampling method that incorporates a normally distributed sampling series for EEG measurements using compressed sensing. We confirmed that the ADC sampling count and amount of wirelessly transmitted data can be reduced by 11% while maintaining a reconstruction accuracy similar to that of the conventional method.

  • Improving Practical UC-Secure Commitments based on the DDH Assumption

    Eiichiro FUJISAKI  

     
    PAPER

      Pubricized:
    2021/10/05
      Vol:
    E105-A No:3
      Page(s):
    182-194

    At Eurocrypt 2011, Lindell presented practical static and adaptively UC-secure commitment schemes based on the DDH assumption. Later, Blazy et al. (at ACNS 2013) improved the efficiency of the Lindell's commitment schemes. In this paper, we present static and adaptively UC-secure commitment schemes based on the same assumption and further improve the communication and computational complexity, as well as the size of the common reference string.

  • Trail: An Architecture for Compact UTXO-Based Blockchain and Smart Contract

    Ryunosuke NAGAYAMA  Ryohei BANNO  Kazuyuki SHUDO  

     
    PAPER-Data Engineering, Web Information Systems

      Pubricized:
    2021/11/09
      Vol:
    E105-D No:2
      Page(s):
    333-343

    In Bitcoin and Ethereum, nodes require a large storage capacity to maintain all of the blockchain data such as transactions. As of September 2021, the storage size of the Bitcoin blockchain has expanded to 355 GB, and it has increased by approximately 50 GB every year over the last five years. This storage requirement is a major hurdle to becoming a block proposer or validator. We propose an architecture called Trail that allows nodes to hold all blocks in a small storage and to generate and validate blocks and transactions. A node in Trail holds all blocks without transactions, UTXOs or account balances. The block size is approximately 8 kB, which is 100 times smaller than that of Bitcoin. On the other hand, a client who issues transactions needs to hold proof of its assets. Thus, compared to traditional blockchains, clients must store additional data. We show that proper data archiving can keep the account device storage size small. Then, we propose a method of executing smart contracts in Trail using a threshold signature. Trail allows more users to be block proposers and validators and improves the decentralization and security of the blockchain.

  • Estimating the Birefringence and Absorption Losses of Hydrogen-bonded Liquid Crystals with Alkoxy Chains at 2.5 THz Open Access

    Ryota ITO  Hayato SEKIYA  Michinori HONMA  Toshiaki NOSE  

     
    INVITED PAPER

      Pubricized:
    2021/08/17
      Vol:
    E105-C No:2
      Page(s):
    68-71

    Liquid crystal (LC) device has high tunability with low power consumption and it is important not only in visible region but also in terahertz region. In this study, birefringence and absorption losses of hydrogen-bonded LC was estimated at 2.5 THz. Our results indicate that introduction of alkoxy chain to hydrogen-bonded LC is effective to increase birefringence in terahertz region. These results indicate that hydrogen-bonded LCs are a strong candidate for future terahertz devices because of their excellent properties in the terahertz region.

  • Reducing Energy Consumption of Wakeup Logic through Double-Stage Tag Comparison

    Yasutaka MATSUDA  Ryota SHIOYA  Hideki ANDO  

     
    PAPER-Computer System

      Pubricized:
    2021/11/02
      Vol:
    E105-D No:2
      Page(s):
    320-332

    The high energy consumption of current processors causes several problems, including a limited clock frequency, short battery lifetime, and reduced device reliability. It is therefore important to reduce the energy consumption of the processor. Among resources in a processor, the issue queue (IQ) is a large consumer of energy, much of which is consumed by the wakeup logic. Within the wakeup logic, the tag comparison that checks source operand readiness consumes a significant amount of energy. This paper proposes an energy reduction scheme for tag comparison, called double-stage tag comparison. This scheme first compares the lower bits of the tag and then, only if these match, compares the higher bits. Because the energy consumption of tag comparison is roughly proportional to the total number of bits compared, energy is saved by reducing this number. However, this sequential comparison increases the delay of the IQ, thereby increasing the clock cycle time. Although this can be avoided by allocating an extra cycle to the issue operation, this in turn degrades the IPC. To avoid IPC degradation, we reconfigure a small number of entries in the IQ, where several oldest instructions that are likely to have an adverse effect on performance reside, to a single stage for tag comparison. Our evaluation results for SPEC2017 benchmark programs show that the double-stage tag comparison achieves on average a 21% reduction in the energy consumed by the wakeup logic (15% when including the overhead) with only 3.0% performance degradation.

1-20hit(318hit)