We review recently obtained results for CMOS (Complementary Metal Oxide Semiconductor) imaging devices used in biomedical applications. The topics include dish type image sensors, deep-brain implantation devices for small animals, and retinal prosthesis devices. Fundamental device structures and their characteristics are described, and the results of in vivo experiments are presented.

MOS capacitors with Si-implanted thermal oxide and CVD deposited oxide of 30 nm thickness were fabricated for applications of non-volatile memory and electroluminescence devices. Current-voltage (I-V) and I-V hysteresis characteristics were measured, and the hysteresis window (HW) and the integrated charge of HW (ICHW) extracted from the hysteresis data were discussed. The HW characteristics of high Si dose samples showed the asymmetrical double-peaks curves with the hump in both tails. The ICHW almost converged after the 4th cycle and had the voltage sweep speed dependence. All +ICHW and -ICHW characteristics were closely related to the static (+I)-(+VG) and (-I)-(-VG) curves, respectively. For the high Si dose samples, the clear hump currents in the static I-VG characteristics contribute to lower the rising voltage and to steepen the ICHW increase, which correspond to the large stored charge in the oxide.

In this review paper we showcase recent activities on silicon photonics science and technology research in Hong Kong regarding two important topical areas--microresonator devices and optical nonlinearities. Our work on silicon microresonator filters, switches and modulators have shown promise for the nascent development of on-chip optoelectronic signal processing systems, while our studies on optical nonlinearities have contributed to basic understanding of silicon-based optically-pumped light sources and helium-implanted detectors. Here, we review our various passive and electro-optic active microresonator devices including (i) cascaded microring resonator cross-connect filters, (ii) NRZ-to-PRZ data format converters using a microring resonator notch filter, (iii) GHz-speed carrier-injection-based microring resonator modulators and 0.5-GHz-speed carrier-injection-based microdisk resonator modulators, and (iv) electrically reconfigurable microring resonator add-drop filters and electro-optic logic switches using interferometric resonance control. On the nonlinear waveguide front, we review the main nonlinear optical effects in silicon, and show that even at fairly modest average powers two-photon absorption and the accompanied free-carrier linear absorption could lead to optical limiting and a dramatic reduction in the effective lengths of nonlinear devices.

The historical review of Taiwan's researching activities on the features of PECVD grown SiOx are also included to realize the performance of Si nanocrystal based MOSLED made by such a Si-rich SiOx film with embedded Si nanocrystals on conventional Si substrate. A surface nano-roughened Si substrate with interfacial Si nano-pyramids at SiOx/Si interface are also reviewed, which provide the capabilities of enhancing the surface roughness induced total-internal-reflection relaxation and the Fowler-Nordheim tunneling based carrier injection. These structures enable the light emission and extraction from a metal-SiOx-Si MOSLED.

One of 3-D devices to achieve high density arrays was adopted in this study, where source and drain junctions are formed along the silicon fin. The screening by adjacent high fins for large sensing margin makes it hard to ion-implant with high angle so that vertical ion implantation is inevitable. In this study, the dependency of current characteristics on doping profiles is investigated by 3-D numerical analysis. The position of concentration peak and the doping gradient are varied to look into the effects on driving currents. Through these analyses, the optimum condition of ion implantation for 3-D devices is estimated.

Antimony tilt implantation has been utilized for source and drain extension formation of n-MOSFETs. The tilt implantation is a very convenient method to provide adequate overlap between the extensions and a gate electrode. MOSFET drive current was effectively improved by the tilt implantation without degrading short channel effects.

In this paper, the effect of Halo concentration on performance of 30 nm gate length Double-Gate MOSFET with 30 nm thin body-Si is investigated by using two dimensional device simulator. We quantitatively show the dependency of electrical characteristic (subthreshold-slope, threshold voltage: Vth, drivability and leak current: Ion and Ioff) on the Halo concentration. This dependency can be explained by the reasons why the Halo concentration has directly effect on the potential distribution of the body. It is made clear that from viewpoint of body potential control, the design of Halo concentration is key technology for suppressing short-channel effect and improving subthreshold-slope, Ion and Ioff adjusting the Vth.

We determine the annealing dynamics of AsGa antisite defects in As ion-implanted GaAs. An Arrhenius plot of the carrier decay rate or the defect density vs. the annealing temperature in the high temperature regime gives an energy EPA, which is different from true activation energy. The annealing time dependence of EPA obtained by the two diffusion models (self diffusion of AsGa antisite defects and VGa vacancy assisted diffusion of AsGa antisite defects) are compared with EPA's obtained from already published works. The results prove that the diffusion of AsGa antisite defects is assisted by the VGa vacancy defects that exist in a high density.

We propose linearization techniques for MMIC amplifiers. The key points of these techniques are increased linearity of a newly-developed low-distortion MESFET (LD-FET) and maximized IP3 by combining the LD-FET with a high-gain depletion-mode MESFET (D-FET) with no increase in power consumption. The LD-FET is characterized by its unique channel dopant-profile prepared by a buried p-type ion-implantation and double n-type ion-implantations with high- and low-acceleration energies. This FET achieves flatter behavior in terms of mutual conductance (gm) compared with conventional MESFETs irrespective of changes in the gate bias voltage (Vgs). A self-alignment/selective ion-implantation process enables the LD-FET and D-FET to be fabricated simultaneously. This process encourages IP3 maximization of the multi-stage amplifier by appropriately combining the advantages of the two differently characterized MESFETs. We fabricated and tested a highly linearized two-stage MMIC amplifier utilizing the proposed techniques, and found that its third-order intermodulation ratio (IMR) performance was 8.7 dB better than that of conventional MMIC amplifiers at an input signal level of -20 dBm with no increase in current dissipation. The configuration constructed by using the proposed techniques equivalently reduces the current dissipation of the second stage to 1/2.72 times that of the conventional configuration, which requires a 2.72 times larger D-FET at the second stage to obtain an 8.7-dB IMR improvement. Furthermore, we were able to improve the IMR by 3.5 dB by optimizing the gate bias conditions for the LD-FET. These results confirm the validity of the proposed techniques.

Electroluminescence (EL) under alternating-current (ac) operation is first reported for n+-polysilicon/SiO2/p-Si MOS capacitors with 50 nm Si-implanted SiO2. Visible EL can be observed with the naked eye in the dark. The ac operation by pulse-wave distinctly enhances the EL intensity and its lifetime. The pulse frequency affects the EL spectrum and thus the EL color. A model of EL mechanism is proposed for the Si-implanted MOS EL device, which has a possibility of visible light emitting device.

785 nm (AlGaAs) laser diode (LD) with a window-mirror structure is demonstrated to be a potential candidate as a highly reliable light source of CD-R. The intermixing of a multi-quantum well structure by silicon implantation is used to form the window-mirror structure. Carbon is adopted as an acceptor because of its low thermal diffusion constant in crystals. As a result, the window-mirror-structure 785 nm AlGaAs LDs with ordinary far field patterns suitable for the actual CD-R drives have shown stable single lateral mode operation up to 250 mW. A mirror degradation level is significantly increased by the window-mirror structure. The pulsed operation current at 160 mW, 70 of the carbon doped LD is reduced by about 15% from that of zinc doped one. Highly reliable 160 mW pulsed operation is also realized at 70. This LD believed to be suited for the next generation high-speed (16-24x) CD-R drives necessitating 160 mW class LD.

A nonlinear Volterra-series analysis of multiple ion-implanted GaAs FETs is given that relates carrier profile parameters of ion-implantation to nonlinear rf characteristics of a FET. Expressions for nonlinear coefficients of transconductance are derived from drain current-voltage characteristics of a multiple ion-implanted FET. Nonlinear transfer functions (NLTFs) are then obtained using Volterra series approach. Using these NLTFs third-order intermodulation distortion and power gain are explicitly given. A good agreement has been found between the calculation and the measurement for a medium power GaAs FET with a total gate width of 800 µm operated at 10-dB back off, verifying the usefulness of the present analysis.

The high accuracy which is necessary for modern process simulation often requires the use of Monte-Carlo ion implantation simulation methods with the disadvantage of very long simulation times especially for three-dimensional applications. In this work a new method for an accurate and CPU time efficient three-dimensional simulation of ion implantation is suggested. The approach is based on a combination of the algorithmic capabilities of a fast analytical and the Monte-Carlo simulation method.

Silicon self-interstitial atom diffusion and implantation induced damage were studied by using molecular dynamics methods. The diffusion coefficient of interstitial silicon was calculated using molecular dynamics method based on the Stillinger-Weber potential. A comparison was made between the calculation method based on the Einstein relationship and the method based on a hopping analysis. For interstitial silicon diffusion, atomic site exchanges to the lattice atoms occur, and thus the total displacement-based calculation underestimates the ideal value of the diffusivity of the interstitial silicon. In addition with calculating the diffusion constant, we also identified its migration pathway and barrier energy in the case of Stillinger-Weber potential. Through a study of molecular dynamics calculation for the arsenic ion implantation process, it was found that the damage self-recovering process depends on the extent of damage. That is, damage caused by a single large impact easily disappears. In contrast, the damage leaves significant defects when two large impacts in succession cause an overlapped damage region.

This paper outlines the modeling requirements of integrated circuit (IC) fabrication processes that have lead to and sustained the development of computer-aided design of technology (i. e. TCAD). Over a period spanning more than two decades the importance of TCAD modeling and the complexity of required models has grown steadily. The paper also illustrates typical applications where TCAD has been powerful and strategic to IC scaling of processes. Finally, the future issues of atomic-scale modeling and the need for an hierarchical approach to capture and use such detailed information at higher levels of simulation are discussed.

We report on 1.9-GHz performance of the Buried-Channel self-aligned WN/W-gate GaAs MESFET (BC-MESFET) for use in digital mobile telephone handsets with low power consumption. The BC-MESFET incorporates undoped i-GaAs epitaxial-grown surface layer on the ion-implanted channel. Both the power and noise performance of the BC-MESFET are superior to the conventional MESFET. The 0.6-µm gate power BC-MESFET exhibits a high power-added efficiency of 57% at 1-dB gain compression, which leads to low power dissipation of the handset. This power performance is attributed to high breakdown voltage which the undoped i-GaAs surface layer has brought about. The BC-MESFET has also shown a minimum noise figure of below 0.4 dB. Taking the IC-oriented fabrication process of the BC-MESFET into consideration, these FET performances demonstrate that the BC-MESFET is suitable for the single-chip MMIC that integrates RF front-end blocks for the 1.9-GHz small-size mobile telephone handset with long battery lifetime.

A 33-cm-Diagonal High-Resolution(1280 1024RGB, which stands for red, green, and blue) TFT-LCD with low, uniform parasitic capacitance between gate electrodes and source/drain electrodes has been developed using Fully Self-Aligned a-Si TFTs. The fabricated TFT-LCD shows no visible seams between block shot exposure regions, even in the display of gray images. In this paper, we describe(1) our full self-alignment technology for the TFTs, including the fabrication process and the technology for reducing OFF current in the TFTs under illumination, (2) SPICE simulation for estimating pixel voltage shift in the fabricated TFT-LCD, and (3) performance results for the fabricated TFT-LCD.

A novel method has been developed to improve the dry etching selectivity of aluminum alloy with respect to photoresist by implanting ions into the patterned photoresist. The selectivity becomes 7.5, which is 5 times higher than that of the unimplanted case. Accordingly, this technology is very promising for fabricating multi-level interconnections in sub-half micron LSIs.

A novel technique for evaluation of charge build-up in semiconductor wafer processing such as ion implantation, plasma etching and plasma enhanced chemical vapor deposition by using the breakdown of MOS capacitors with charge collecting electrodes (antenna) is proposed. The charge build-up during high beam current ion implantation is successfully evaluated by using this technique. The breakdown sensitivity of a MOS capacitor is improved by using a small area MOS capacitor with a large area antenna electrode. To estimate charge build-up on wafers quantitatively, the best combination of gate oxide thickness, substrate type, MOS capacitor area and antenna ratio should be carefully chosen for individual charge build-up situation. The optimum structured antenna MOS capacitors which relationship between QBD and stressing current density was well characterized give us very simple and quantitative charge build-up evaluation. This technique is very simple and useful to estimate charge build-up as compared with conventional technique by suing EEPROM devices or large area MOS capacitors.

The Double-Sided Rugged poly Si (DSR) technology has been developed for high density DRAMs. The DSR technology was achieved using transformation of rugged poly Si caused by ion implantation. The DSR can increase the surface area of the storage electrode, because it has rugged surfaces on both upper and lower sides. The 2-FINs STC (STacked Capacitor cell) with DSR was fabricated in the cell size of 0.72 µm2, and it is confirmed that the DSR can increase the surface area 1.8 times larger than that of smooth poly Si. It is expected that 25 fF/bit is obtained with a 300 nm-thick storage electrode. These effects show that sufficient capacitance for 256 Mb DRAMs is obtained with a low storage electrode. It is confirmed that there is no degradation in C-V and I-V characteristics. Moreover, the DSR needs neither complicated process steps nor special technologies. Therefore, the DSR technology is one of the most suitable methods for 256 Mb DRAMs and beyond.