This paper presents MDX-Mixer, which improves music demixing (MDX) performance by leveraging source signals separated by multiple existing MDX models. Deep-learning-based MDX models have improved their separation performances year by year for four kinds of sound sources: “vocals,” “drums,” “bass,” and “other”. Our research question is whether mixing (i.e., weighted sum) the signals separated by state-of-the-art MDX models can obtain either the best of everything or higher separation performance. Previously, in singing voice separation and MDX, there have been studies in which separated signals of the same sound source are mixed with each other using time-invariant or time-varying positive mixing weights. In contrast to those, this study is novel in that it allows for negative weights as well and performs time-varying mixing using all of the separated source signals and the music acoustic signal before separation. The time-varying weights are estimated by modeling the music acoustic signals and their separated signals by dividing them into short segments. In this paper we propose two new systems: one that estimates time-invariant weights using 1×1 convolution, and one that estimates time-varying weights by applying the MLP-Mixer layer proposed in the computer vision field to each segment. The latter model is called MDX-Mixer. Their performances were evaluated based on the source-to-distortion ratio (SDR) using the well-known MUSDB18-HQ dataset. The results show that the MDX-Mixer achieved higher SDR than the separated signals given by three state-of-the-art MDX models.

When we use a Programmable Microfluidic Device (PMD), we need to wash some contaminated area to use the chip for further experiments. Recently, a novel washing technique called Block-Flushing has been proposed. Block-Flushing washes contaminated area in PMDs by using buffer flows. In Block-Flushing, we need to keep a buffer flow from an input port to an output port of a PMD for a long period to dissolve residual contaminants. Thus, we may need a lot of buffer fluids and washing time even if the contaminated area is small. Another disadvantage of the washing method by Block-Flushing is such that we may not able to clean residual contaminants at valves completely by only buffer flows. To address the above-mentioned issues, this paper proposes a totally new idea to wash PMDs; our method does not use buffer flows, but washes contaminated area by using mixers. By using a mixer, we can dissolve residual contaminants at valves in the area of the mixer very efficiently. In this paper, we propose two methods to wash PMDs by using mixers. The first method can wash the whole chip area by using only four times of a single 2x2-mixer time. We also propose the second method which is a heuristic to reduce the number of moving valves because valves may wear down if they are used many times. We also show some experimental results to confirm that the second method can indeed decrease the number of used valves.

This paper presents a fully integrated yet compact receiver front-end for Sub-GHz applications such as Internet-of-Things (IoT). The low noise amplifier (LNA) matching network leverages an inductance boosting technique. A relatively small on-chip inductor with a compact area achieves impedance matching in such a low frequency. Moreover, a passive-mixer-first mode bypasses the LNA to extend the receiver dynamic-range. The passive mixer provides matching to the 50Ω antenna interface to eliminate the need for additional passive components. Therefore, the receiver can be fully-integrated without any off-chip matching components. The flipped-voltage-follower (FVF) cell is adopted in the low pass filter (LPF) and the variable gain amplifier (VGA) for its high linearity and low power consumption. Fabricated in 65nm LP CMOS process, the proposed receiver front-end occupies 0.37mm2 core area, with a tolerable input power ranging from -91.5dBm to -1dBm for 500kbps GMSK signal at 924MHz frequency. The power consumption is 1mW power under a 1.2V supply.

This paper demonstrates that a 360° radio-frequency phase detector consisting of a combination of symmetrical mixers and 45° phase shifters with tunable devices can achieve a low phase-detection error over a wide frequency range. It is shown that the phase detection error does not depend on the voltage gain of the 45° phase shifter. This allows the usage of tunable devices as 45° phase shifters for a wide frequency range with low phase-detection errors. The fabricated phase detector having tunable low-pass filters as the tunable device demonstrates phase detection errors lower than 2.0° rms in the frequency range from 3.0 GHz to 10.5 GHz.

This paper describes the development of superconductor-insulator-superconductor (SIS) mixers for the Atacama Large Millimeter/submillimeter Array (ALMA) from the device point of view. During the construction phase of ALMA, the National Astronomical Observatory of Japan (NAOJ) successfully fabricated SIS mixers to meet the stringent ALMA noise temperature requirements of less than 230 K (5 times the quantum noise) for Band 10 (787-950 GHz) in collaboration with the National Institute of Information and Communications Technology. Band 10 covers the highest frequency band of ALMA and is recognized as the most difficult band in terms of superconducting technology. After the construction, the NAOJ began development studies for ALMA enhancement such as wideband and multibeam SIS mixers according to top-level science requirements, which are also presented.

In this letter, a flexible and compatible with fine resolution radar frequency measurement receiver is designed. The receiver is implemented on the platform of Virtex-5 Field Programmable Grid Array (FPGA) from Xilinx. The Digital Down Conversion (DDC) without mixer based on polyphase filter has been successfully introduced in this receiver to obtain lower speed data flow and better resolution. This receiver can adapt to more modulation types and higher density of pulse flow, up to 200000 pulses per second. The measurement results indicate that the receiver is capable of detecting radar pulse signal of 0.2us to 2.5ms width with a major frequency root mean square error (RMSE) within 0.44MHz. Moreover, the wider pulse width and the higher decimation rate of DDC result in better performance. This frequency measurement receiver has been successfully used in a spaceborne radar system.

A design method of the differential N-path filter with sampling computation is proposed. It enables the scale of the whole filter to be reduced by approximately half for easier realization. On top of that, the proposed method offers the ability to eliminate the harmonic passbands of the clock frequency and an increase of harmonic rejection. By using the proposed method, previous work involving an 8-path filter can be reduced to 5-path. The proposed differential 5-path filter reduces the scale of the circuit and at the same time has the performance of a 10-path filter from previous work. An example of differential 7-path filter using the same proposed design method is also stated in comparison of the differential 5-path filter. The differential 7-path filter offers the ability to eliminate all the passbands below 10 times the clock frequency with a tradeoff of an increase in circuit scale.

A frequently occurring subcircuit consists of a loop of a resistor (R), a field-effect transistor (FET), and a capacitor (C). The FET acts as a switch, controlled at its gate terminal by a clock voltage. This subcircuit may be acting as a sample-and-hold (S/H), as a passive mixer (P-M), or as a bandpass filter or bandpass impedance. In this work, we will present a useful analysis that leads to a simple signal flow graph (SFG), which captures the FET-R-C circuit's action completely across a wide range of design parameters. The SFG dissects the circuit into three filtering functions and ideal sampling. This greatly simplifies analysis of frequency response, noise, input impedance, and conversion gain, and leads to guidelines for optimum design. This paper focuses on the analysis of a single-path FET-R-C circuit's signal transfer characteristics including the reconstruction of the complete waveform from the discrete-time sampled voltage.

This paper presents low-noise amplifier (LNA)-less 300-GHz CMOS receivers that operate above the NMOS unity-power-gain frequency, fmax. The receivers consist of a down-conversion mixer with a doubler- or tripler-last multiplier chain that upconverts an LO1/n signal into 300 GHz. The conversion gain of the receiver with the doubler-last multiplier is -19.5 dB and its noise figure, 3-dB bandwidth, and power consumption are 27 dB, 27 GHz, and 0.65 W, respectively. The conversion gain of the receiver with the tripler-last multiplier is -18 dB and its noise figure, 3-dB bandwidth, and power consumption are 25.5 dB, 33 GHz, and 0.41 W, respectively. The receivers achieve a wireless data rate of 32 Gb/s with 16QAM. This shows the potential of the moderate-fmax CMOS technology for ultrahigh-speed THz wireless communications.

The mixer is a crucial circuit block in a WiMax system receiver. The performance of a mixer depends on three specifications: conversion gain, linearity and noise figure. Many mixers have been recently proposed for UWB and wideband systems; however, they either cannot achieve the high conversion gain required for a WiMAX system or they are prone to high power consumption. In this paper, a folded mixer with a high conversion gain is designed for a 2-11GHz WiMAX system and it can achieve a 20MHz IF output signal. From the simulation results, the proposed folded mixer achieves a conversion gain of 18.9 to 21.5dB for the full bandwidth. With a 0.2 to 4.4dBm IIP3, the NF is 13.5 to 17.6dB. The folded mixer is designed using TSMC 0.18µm CMOS technology. The core power consumption of the mixer is 11.8mW.

A wide-bandwidth fundamental mixer operating at a frequency above 110GHz for precise spectrum analysis was developed using the InP HEMT technology. A single-ended resistive mixer was adopted for the mixer circuit. An IF amplifier and LO buffer amplifier were also developed and integrated into the mixer chip. As for packaging into a metal block module, a flip-chip bonding technique was introduced. Compared to face-up mounting with wire connections, flip-chip bonding exhibited good frequency flatness in signal loss. The mixer module with a built-in IF amplifier achieved a conversion gain of 5dB at an RF frequency of 135GHz and a 3-dB bandwidth of 35GHz. The mixer module with an LO buffer amplifier operated well even at an LO power of -20dBm.

RF under sampling is more suitable for Satellite receiver systems in comparison to terrestrial systems. In conventional RF under sampling the minimum sampling frequency (fs) should be atleast twice the system bandwidth; therefore for a system with a wide bandwidth, a relatively high fs is necessary. In this paper we propose a direct RF under sampling reception method that halves fs. The proposed f's is achieved by folding in band noise in half. A method of adapting f's for the reception of signals in different channels is also proposed; this ensures that the SNR is not degraded for any channel. To evaluate the proposed technique's performance and compare it to the conventional case a 3 channel, 1 GHz band test receiver and it's key device (i.e. S/H circuit) are developed. Using SNR and EVM as performance indexes, the performance of the proposed technique has been evaluated and compared to that of the conventional technique. The evaluation results show that the proposed technique can achieve the same performance as conventional RF under sampling for all 3 channels, using only half of the sampling frequency of the conventional technique.

Novel multi-band mixers that can receive multiple band signals concurrently are proposed and evaluated. The mixers achieve independent gain control through novel relative power control method of the multiple local oscillator (LO) signals. Linear control is also achieved through multiple LO signal input with total LO power control. Theoretical analysis shows that odd-order nonlinearity components of the multiple LO signals support linear conversion gain control. Dual- and triple-band tests are conducted using typical three MOSFET mixers fabricated by a 0.25 µm SiGe BiCMOS process. Measurements confirm over 40 dB independent control of conversion gain, linear control achieved through LO input power control. The proposed mixers have high input linearity with a 5 dBm output third intercept point. A method is also proposed to reduce interference caused by mixing between multiple LO signals.

In this paper we describe and experimentally validate a dual-band digital predistortion (DPD) model we propose that takes account of the intermodulation and harmonic distortion produced when the center frequencies of input bands have a harmonic relationship. We also describe and experimentally validate our proposed novel dual-band power amplifier (PA) linearization architecture consisting of a single feedback loop employing a dual-band mixer. Experiment results show that the DPD linearization the proposed model provides can compensate for intermodulation and harmonic distortion in a way that the conventional two-dimensional (2-D) DPD approach cannot. The proposed feedback architecture should make it possible to simplify analog-to-digital converter (ADC) design and eliminate the time lag between different feedback paths.

Recently, a next-generation heterodyne mixer detector---a hot electron bolometer (HEB) mixer employing a superconducting microbridge---has gradually opened up terahertz-band astronomy. The surrounding state-of-the-art technologies including fabrication processes, 4 K cryostats, cryogenic low-noise amplifiers, local oscillator sources, micromachining techniques, and spectrometers, as well as the HEB mixers, have played a valuable role in the development of super-low-noise heterodyne spectroscopy systems for the terahertz band. The current developmental status of terahertz-band HEB mixer receivers and their applications for spectroscopy and astronomy with ground-based, airborne, and satellite telescopes are presented.

A monolithic frequency synthesizer with wide tuning range, low phase noise and spurs was realized in 0.13,$mu$m CMOS technology. It consists of an analog PLL, a harmonic-rejection mixer and injection-locked frequency doublers to cover the whole 6--18,GHz frequency range. To achieve a low phase noise performance, a sub-sampling PLL with non-dividers was employed. The synthesizer can achieve phase noise $-$113.7,dBc/Hz@100,kHz in the best case and the reference spur is below $-$60,dBc. The core of the synthesizer consumes about 110,mA*1.2,V.

The linearity analysis of a passive mixer is presented. The distortion mechanism caused by switching operation of a MOS transistor is elucidated from the static and dynamic analysis of passive mixers. Furthermore, the maximum input and output level to keep linear operation and its required bias conditions are expressed by simple equations. The maximum linear output amplitude of the passive mixer is determined only by the local signal amplitude and it does not depend on input and output impedance. The calculated linearity performances agree well with simulated and measured results.

In this paper, the research advances in silicon based millimeter wave and THz ICs in the State Key Laboratory of Millimeter Waves is reviewed, which consists of millimeter wave amplifiers, mixers, oscillators at Q, V and W and D band based on CMOS technology, and several research approaches of THz passive ICs including cavity and filter structures using SIW-like (Substrate Integrated Waveguide-like) guided wave structures based on CMOS and MEMs process. The design and performance of these components and devices are presented.

The Direct Sampling Mixer (DSM) with a complex coefficient transfer function is demonstrated. The operation theory and the detail design methodology are discussed for the high order complex DSM, which can achieve large image rejection ratio by introducing the attenuation pole at the image frequency band. The proposed architecture was fabricated in a 65 nm CMOS process. The measured results agree well with the theoretical calculation, which proves the validity of the proposed architecture and the design methodology. By using the proposed design method, it will be possible for circuit designers to design the DSM with large image rejection ratio without repeated lengthy simulations.

We have developed a process for the fabrication of high-quality Nb/AlOx/Nb tunnel junctions with small area and high current densities for the heterodyne mixers at millimeter and submillimeter wavelengths. Their dc I-V curves are numerically studied, including the broadening of quasiparticle density of states resulting from the existence of an imaginary part of the gap energy of Nb. We have found both experimentally and numerically that the subgap current is strongly dependent on bias voltage at temperatures below 4.2 K unlike the prediction of the BCS tunneling theory. It is shown that calculated dc I-V curves taking into account the complex number of the gap energy agree well with those of Nb/AlOx/Nb junctions measured at temperatures from 0.4 to 4.2 K. We have successfully built receivers at millimeter and submillimeter wavelengths with the noise temperature as low as 4 times the quantum photon noise, employing those high-quality Nb/AlOx/Nb junctions. Those low-noise receivers are to be installed in the ALMA (Atacama Large Millimeter/Submillimeter Array) telescope and they are going into series production now.