This paper presents a 7 GHz differential current-reused voltage-controlled oscillator (CR-VCO) with low power consumption and low phase noise using 0.18-µm CMOS technology. The output power of this CR-VCO is enhanced by utilizing a trifilar-transformer-feedback technique. The lower phase noise is achieved by the more symmetric voltage swings resulting from the improved balance of switching current. At a 1.5-V DC supply voltage, the power dissipation is only 3.4 mW. The total tuning range is 1.4 GHz (17.9%) as the tuning voltage ranges from 0 V to 1.8 V. The optimum phase noise is around -117.3 dBc/Hz at a frequency offset of 1 MHz from the center frequency of 7.07 GHz. The corresponding output power is around -6.8 dBm. For the proposed CR-VCO, the calculated figures-of-merit, FOM and FOMT , are -188.9 and -193.9 dBc/Hz, respectively.

Power-aware scheduling of periodic tasks in real-time systems has been extensively studied to save energy while still meeting the performance requirement. Many previous studies use the probability information of tasks' execution cycles to assist the scheduling. However, most of these approaches adopt heuristic algorithms to cope with realistic CPU models with discrete frequencies and cannot achieve the globally optimal solution. Sometimes they even show worse results than non-stochastic DVS schemes. This paper presents an optimal DVS scheme for frame-based real-time systems under realistic power models in which the processor provides only a limited number of speeds and no assumption is made on power/frequency relation. A suboptimal DVS scheme is also presented in this paper to work out a solution near enough to the optimal one with only polynomial time expense. Experiment results show that the proposed algorithm can save at most 40% more energy compared with previous ones.

AC-waveform synthesis with quantum-mechanical accuracy has been attracting many researchers, especially metrologists in national metrology institutes, not only for its scientific interest but its potential benefit to industries. We describe the current status at National Metrology Institute of Japan of development of a Josephson arbitrary waveform synthesizer based on programmable and pulse-driven Josephson junction arrays.

A novel one-transistor dynamic random access memory (1T DRAM) cell has been proposed for a low-voltage operation and longer data retention time. The proposed 1T DRAM cell has three features compared with a conventional 1T DRAM cell: low body doping concentration, a recessed gate structure, and a P + poly-Si gate. Simulation results show that the proposed 1T DRAM cell has < 1-ns program time and > 100-ms data retention time under the condition of sub-1-V operating voltage.

This paper presents a voltage reference that utilizes the virtually diode-connected MOS transistors, biased in the weak-inversion region. The proposed architecture increases the gain of the feedback loop that consequently reduces the system sensitivity, and hence improves the PSRR. The circuit is designed and simulated in a standard 0.18 µm CMOS technology. The simulation results in HSPICE indicate the successful operation of the circuit as follows: the PSRR at DC frequency is 86 dB and for the temperature range from -55C to 125C, the variation of the output reference voltage is less than 66 ppm/C.

A low voltage operational active inductor circuit is attractive for spiral-inductor-less LNA because of realizing high gain and low voltage operation simultaneously. In this paper, a simply structured low-voltage operational active inductor to enhance the amplifier gain is introduced and analyzed. This active inductor, which utilizes a transistor load operated in the triode region and a source follower, features a small DC voltage drop suitable for low voltage LNAs. An LNA using the active inductor load was designed with an input matching circuit using 90 nm CMOS technology. The LNA tuned to 2.4 GHz operation has 19.5 dB of the internal gain. In addition, the frequency characteristics are easily varied by changing the capacitance value in the active inductor circuit. The core circuit occupies only 0.0026 mm2 and consumes 2.8 mW with 1.2 V supply voltage.

This paper describes the design methodology of a low dropout regulator (LDO). It was used to develop a power management sub-system IC for CDMA handsets which is also described in this paper. This IC contains 11 LDOs, bandgap reference, battery charger, control logic and some other peripheral circuits. For CDMA applications, very small ground current in the order of µA in standby mode is required for LDOs. An LDO architecture to meet this requirement and achieve stable operation over the process variation was developed. The on-chip logic efficiently controls all LDOs and battery charger to reduce the power dissipation as much as possible. This mixed signal subsystem has been implemented in the in-house 0.6-µm BCDMOS process. The very low LDO ground current down to 3 µA has been achieved with stable operation.

CMOS SoCs can reduce power consumption by adopting voltage scaling (VS) technologies, where the level converter (LC) is required between voltage domains to avoid dc current. However, the LC often induces high delay penalty and usually results in non-balanced rise and fall delays. Therefore, the performance of the LC strongly affects the effectiveness of VS technologies. In this paper, heuristic sizing methodology for designing a state-of-the-art LC is developed and proposed. Using the proposed methodology, we can design the LC to achieve high performance with balanced rise and fall delay times in a deterministic way.

The principles for good design of battery-aware voltage scheduling algorithms for both aperiodic and periodic task sets on dynamic voltage scaling (DVS) systems are presented. The proposed algorithms are based on greedy heuristics suggested by several battery characteristics and Lagrange multipliers. To construct the proposed algorithms, we use the battery characteristics in the early stage of scheduling more properly. As a consequence, the proposed algorithms show superior results on synthetic examples of periodic and aperiodic tasks from the task sets which are excerpted from the comparative work, on uni- and multi-processor platforms, respectively. In particular, for some large task sets, the proposed algorithms enable previously unschedulable task sets due to battery exhaustion to be schedulable.

Single event transient (SET) effects on original static cascade voltage switch logic (CVSL) exclusive-OR (EX-OR) circuits have been investigated using SPICE. SET simulation results have confirmed that the static CVSL EX-OR circuits have increased tolerance to SET. The static CVSL EX-OR circuit is more than 200 times harder than the conventional CMOS circuit.

High efficiency power feeding systems are effective solutions for reducing the ICT power consumption with reducing power consumption of the ICT equipment and cooling systems. A higher voltage direct current (HVDC) power feeding system prototype was produced. This system is composed of a rectifier equipment, power distribution unit, batteries, and the ICT equipment. The configuration is similar to a -48 V DC power supply system. The output of the rectifier equipment is 100 kW, and the output voltage is 401.4 V. This paper present the configuration of the HVDC power feeding system and discuss its basic characteristics in the prototype system.

Gas flow in arc quenching chamber has an important effect on the interruption capability of low voltage circuit breakers. In this paper, based on a simplified model of arc chamber with a single break, which can be opened by the electro-dynamics repulsion force automatically, the effect of different vent configurations including middle vent and side vent on the interruption performance is investigated. First, the experiments are carried out to compare the different performance in the interruption process between middle vent type and side vent type. In addition, according to the experimental model, a 3-D magneto-hydrodynamic model was developed by adapting and modified the commercial computational fluid dynamics software FLUENT. The simulation results show the same trend in arc motion as explained in the experimental conclusions in theory.

Effects of stress in passivation films on the electrical properties of (0001) AlGaN/GaN HEMTs are numerically analysed in the framework of the edge force model with anisotropical characteristics in elastic properties of group-III nitrides explicitly considered. Practical compressive stresses in passivation films induce negative piezoelectric charges below the gates and bring forth a-few-volt shallower threshold voltages. In addition, the shift in the threshold voltage due to the compressive stress is proportional to LG-1.1-1.5 with gate length LG, which is comparable to the expectation based on the charge balance scheme. These result suggest that passivation films with designed stress might play a crucial role in realising AlGaN/GaN HEMTs with shallow or positive threshold voltages.

A unipolar n-n heterostrucuture diode is developed in the InP material system. The electronic barrier is formed by a saw tooth type of conduction band bending which consists of a quaternary In0.52(AlyGa1-y)0.48As layer with 0 < y < ymax. This barrier is lattice matched for all y to InP and is embedded between two n+-InGaAs layers. By varying the maximum Al-content from ymax,1 = 0.7 to ymax,2 = 1 a variable barrier height is formed which enables a diode-type I-V characteristic by epitaxial design with an adjustable current density within 3 orders of magnitude. The high current density of the diode with the lower barrier height (ymax,1 = 0.7) makes it suitable for high frequency applications at low signal levels. RF measurements reveal a speed index of 52 ps/V at VD = 0.15 V. The device is investigated for RF-to-DC power conversion in UHF RFID transponders with low-amplitude RF signals.

A low-voltage class-AB CMOS output stage with a tunable quiescent current control circuit is presented. It is based on a complementary common source. The quiescent current is detected by a compact circuit and can be adjusted by means of a control current without need to modify the transistor dimensions. The minimum supply voltage can be down to one threshold voltage plus two saturation voltages. It is suitable to drive low resistive loads. Simulation results are provided that are in agreement with expected characteristics.

A high-throughput on-chip monitoring circuit with a digital output is proposed for the variations of the NMOS and PMOS threshold voltages. A voltage-controlled delay line (VCDL) and a time-to-digital converter (TDC) are used to convert a small difference in analog voltage into a large difference in time delay. This circuit was applied to the transistors of W = 10 µm and L = 0.18 µm in a 1616 array matrix fabricated with a 0.18-µm process. The measurement of the threshold voltage shows that the maximum peak-to-peak intra-chip variation of NMOS and PMOS transistors are about 31.7 mV and 32.2 mV, respectively, for the temperature range from -25 to 75. The voltage resolutions of NMOS and PMOS transistors are measured to be 1.10 mV/bit and 3.53 mV/bit at 25, respectively. The 8-bit digital code is generated for the threshold voltage of a transistor in every 125 ns, which corresponds to the 8-MHz throughput.

In order to quickly discharge the electrostatic discharge (ESD) energy, an unassisted low-voltage-trigger ESD protection structure is proposed in this work. Under transmission line pulsing (TLP) stress, the trigger voltage, turn-on speed and second breakdown current can be obviously improved, as compared with the traditional protection structure. Moreover there is no need to add any extra mask or do any process modification for the new structure. The proposed structure has been verified in foundry's 0.18-µm CMOS process.

We derive physics-based formula of current-voltage characteristic for resonant tunneling diodes (RTDs) by using the Voigt function. The Voigt function describes the mixing condition of homogeneous and inhomogeneous broadenings of peak energy width in transmission probability, which is sensitively reflected to nonlinear negative differential resistance of RTDs. The obtained formula is applicable to the SPICE model of RTD without performing numerical integrals. We indicate validity of the formula by comparing to measured data for double-barrier and triple-barrier RTDs.

The data dispersion of the measurement of electromagnetic disturbance above 1 GHz is mainly affected by site imperfections (expressed by the site voltage standing wave ratio (SVSWR)). To confirm the relationship between site imperfections and the measured field strength, we measured the SVSWR and the field strength radiated from the equipment under test (EUT) by changing the area covered by the RF absorber on the metal ground plane. From the results, we found that the data dispersion of measured field strength can be estimated from the measured SVSWR, and therefore, we can determine the measurement uncertainty of the measured field strength at the test site.

An on-chip process, supply voltage, and temperature (PVT) compensation technique for low-voltage CMOS digital circuits was proposed. Because the degradation of circuit performance originates from the variation of the saturation current in transistors, we developed a compensation circuit consisting of a reference current that is independent of PVT variations. The circuit is operated so that the saturation current in digital circuits is equal to the reference current. The operations of the circuit were confirmed by SPICE simulation with a set of 0.35-µm standard CMOS parameters. Monte Carlo simulations showed that the proposed technique effectively improves circuit performance by 71%. The circuit is useful for on-chip compensation to mitigate the degradation of circuit performance with PVT variation in low-voltage digital circuits.