Cell voltage equalizers are necessary to ensure years of operation and maximize the chargeable/dischargeable energy of series-connected supercapacitors (SCs). A two-switch voltage equalizer using a series-resonant voltage multiplier operating in frequency-multiplied discontinuous conduction mode (DCM) is proposed for series-connected SCs in this paper. The frequency-multiplied mode virtually increases the operation frequency and hence mitigates the negative impact of the impedance mismatch of capacitors on equalization performance, allowing multi-layer ceramic capacitors (MLCCs) to be used instead of bulky and costly tantalum capacitors, the conventional approach when using voltage multipliers in equalizers. Furthermore, the DCM operation inherently provides the constant current characteristic, realizing the excessive current protection that is desirable for SCs, which experience 0V and equivalently become an equivalent short-circuit load. Experimental equalization tests were performed for eight SCs connected in series under two frequency conditions to verify the improved equalization performance at the increased virtual operation frequencies. The standard deviation of cell voltages under the higher-frequency condition was lower than that under the lower-frequency condition, demonstrating superior equalization performance at higher frequencies.

This paper presents the electrical contact behaviors of Au-plated material at super low making and breaking velocity conditions by introducing our new designed test rig. The fundamental phenomena in the contact voltage and contact force versus piezoactuator displacement curves were investigated under the load current of 1A and velocity of 50,nm/s. From the repetitive experimental results, we found that the adhesion phenomena during the unloading process are closely correlative with the initial contact stage in the loading process. Furthermore, a mathematical model which is relative to the variation of contact force in loading is built, thus the physical mechanism of adhesion and principal factors of gold-plated materials are discussed. Finally, the physical process of molten bridge under the no mechanical contact situation is also analyzed in detail.

A primary-side regulation AC--DC constant voltage control chip is designed, which employs a novel cable compensation technique to improve the precision of the output voltage and pursue a wider load range for regulation. In the proposed controller, constant voltage (CV) is achieved by OSC charging current and current-limiting point adjustment. Meantime, according to different cable lengths, the sampled voltage is regulated by injecting current to pull-down resistance of the system to obtain an accurate output voltage. The proposed chip is implemented in TSMC 0.35,$mu $m 5,V/40,V BCD process, and a 12,V/1,A circuit prototype has been built to verify the proposed control method. Experimental results show that the maximum cable compensation current reaches 43,$mu $A, and the precision of the output voltage is within $pm$ 3% in a wide range of output current from 0 to 1,A.

An all-digital time-domain ADC, abbreviated as TAD, is presented in this paper. All-digital structure is intrinsically compatible with the scaling of CMOS technology, and can satisfy the great demand of miniaturized and low-voltage sensor interface. The proposed TAD uses an inverter-based Ring-Delay-Line (RDL) to transform the input signal from voltage domain to time domain. The voltage-modulated time information is then digitized by a composite architecture namely “4-Clock-Edge-Shift Construction” (4CKES). TAD features superior voltage sensitivity and 1st-order noise shaping, which can significantly simplify the power-hungry pre-conditioning circuits. Reconfigurable resolution can be easily achieved by applying different sampling rates. A TAD prototype is fabricated in 65nm CMOS, and consumes a small area of 0.016mm2. It achieves a voltage resolution of 82.7µV/LSB at 10MS/s and 1.96µV/LSB at 200kS/s in a narrow input range of 0.1Vpp, merely under 0.6V supply. The highest SNR of TAD prototype is 61.36dB in 20kHz bandwidth at 10MS/s. This paper also analyzes the nonideal effects of TAD and discusses the potential solutions. As the principal drawback, nonlinearity of TAD can be compensated by the differential-setup and digital calibration.

This paper describes a simple-yet-effective control method for a DC-DC buck converter with voltage mode control (VMC), with a triangular wave generator (TWG) which regulates the slope of triangular wave based on the input and output voltages of the converter. Using the proposed TWG, both the load and line transient responses are improved. Since the TWG provides a line feed-forward control for the line transient response, it increases the open-loop bandwidth, and then better dynamic performance is obtained. Additional required circuit components are only a voltage controlled linear resistor (VCR) and a voltage controlled current source (VCCS). Compared with the conventional voltage control, the proposed method significantly improves the line and load transient responses. Furthermore this triangular wave slope regulation scheme is simple compared to digital feed-forward control scheme that requires non-linear calculation. Simulation results shows the effectiveness of the proposed method.

We propose that the current distribution along a dipole can be divided into a component proportional to the port current, a component proportional to the port voltage, and an antisymmetrical component. In this paper, we perform numerical computations to verify that the component proportional to the port voltage always lags the port voltage by 90°, and the ratio of its amplitude to that of the port voltage is not significantly affected by the arrangement of other dipoles located nearby or by circuits connected to the ports of the dipoles if the dipoles have lengths not exceeding one wavelength.

This paper proposes an ultra-low-voltage, wide signal swing, and clock-scalable differential dynamic amplifier using a common-mode voltage detection technique. The essential characteristics of an amplifier, such as gain, linearity, power consumption, noise, etc., are analyzed. In measurement, the proposed dynamic amplifier achieves a 13dB gain with less than 1dB drop over a differential output signal swing of 340mVpp with a supply voltage of 0.5V. The attained maximum operating frequency is 700MHz. With a 0.7V supply, the gain increases to 16dB with a signal swing of 700mVpp. The prototype amplifier is fabricated in 90nm CMOS technology with the low threshold voltage and the deep N-well options.

This paper reports a 65nm 8Mb spin transfer torque magnetoresistance random access memory (STT-MRAM) operating at a single supply voltage with a process-variation-tolerant sense amplifier. The proposed sense amplifier comprises a boosted-gate nMOS and negative-resistance pMOSs as loads, which maximizes the readout margin at any process corner. The STT-MRAM achieves a cycle time of 1.9µs (=0.526MHz) at 0.38V. The operating power is 1.70µW at this voltage. The minimum energy per access is 1.12 pJ/bit when the supply voltage is 0.44V. The proposed STT-MRAM operates at a lower energy than an SRAM when the utilization of the memory bandwidth is 14% or less.

This paper proposes low-power voltage-mode/current-mode hybrid circuits to realize an arbitrary two-variable logic function and a full-adder function. The voltage and current mode can be selected for low-power operations at low and high frequency, respectively, according to speed requirement. An nMOS pass transistor network is shared to realize voltage switching and current steering for the voltage- and current-mode operations, respectively, which leads to high utilization of the hardware resources. As a result, when the operating frequency is more than 1.15,GHz, the current mode of the hybrid logic circuit is more power-efficient than the voltage mode. Otherwise, the voltage mode is more power-efficient. The power consumption of the hybrid two-variable logic circuit is lower than that of the conventional two-input look-up table (LUT) using CMOS transmission gates, when the operating frequency is more than 800,MHz. The delay and area of the hybrid two-variable logic circuit are increased by only 7% and 13%, respectively

Since electromagnetic (EM) noise resulting from an arc discharge disturbs other electric devices, parameters on electromagnetic compatibility, as well as lifetime and reliability, are important properties for electrical contacts. To clarify the characteristics and the mechanism of the generation of the EM noise, the arc column and voltage fluctuations generated by slowly breaking contacts with external direct current (DC) magnetic field, up to 20,mT, was investigated experimentally using Ag$_{90.7{ m wt%}}$SnO$_{2,9.3{ m wt}%}$ material. Firstly the motion of the arc column is measured by high-speed camera. Secondary, the distribution of the motion of the arc and contact voltage are discussed. It was revealed that the contact voltage fluctuation in the arc duration is related to the arc column motion.

The data rate of VLSI interconnections has been increasing according to the demand for high-speed operation of semiconductors such as CPUs. To realize high performance VLSI systems, high-speed data communication has become an important factor. However, at high-speed data rates, it is difficult to achieve accurate communication without bit errors because of inter-symbol interference (ISI). This paper presents high-speed data communication techniques for VLSI systems using Tomlinson-Harashima Precoding (THP). Since THP can eliminate the ISI with limiting average and peak power of transmitter signaling, THP is suitable for implementing advanced low-voltage VLSI systems. In this paper, 4-PAM (Pulse amplitude modulation) with THP has been employed to achieve high-speed data communication in VLSI systems. Simulation results show that THP can remove the ISI without increasing peak and average power of a transmitter. Moreover, simulation results clarify that multiple-valued data communication is very effective to reduce implementation costs for realizing high-speed serial links.

This paper proposes a new address method to reduce the address power consumption in an AC plasma panel display (AC-PDP). We apply an overlap scan method, in which the scan pulse overlaps with those of the previous scan time and the next scan time. The overlap scan method decreases the address voltage and consequently reduces the address power consumption. However, the drawback of this method is the narrow address voltage margin. This occurs because the maximum address voltage decreases much more than the minimum address voltage does. In order to increase the address voltage margin, we apply a two-step address voltage waveform, in the overlap scan method. In this case, the maximum address voltage increases; however, the minimum address voltage is almost the same. This leads to a wide address voltage margin. Moreover, the two-step address voltage waveform reduces the address power consumption, because the address voltage rises and falls in two steps using an energy recovery capacitor. Consequently, the experimental results show that the new address method reduces the address power consumption by 19.6,Wh (58%) when compared with the conventional method.

A scalable low voltage signaling (SLVS) transmitter, with asymmetric impedance calibration, is proposed for mobile applications which require low power consumption. The voltage swing of the proposed SLVS transmitter is scalable from 40,mV to 440,mV. The proposed asymmetric impedance calibration asymmetrically controls the pull-up and pull-down drivers for the SLVS transmitter with an impedance of 50,$Omega$. This makes it possible to remove the additional regulator used to calibrate the impedance of an output driver by controlling the swing level of a pre-driver. It also maintains the common mode voltage at the center voltage level of the transmitted signal. The proposed SVLS transmitter is implemented using a 0.18-$mu $m 1-poly 6-metal CMOS process with a 1.2-V supply. The active area and power consumption of the transmitter are $250 imes 123 mu$ m$^{2}$ and 2.9,mW/Gb/s, respectively.

Extremely low voltage operation near or below threshold voltage is a key circuit technology to improve the energy efficiency of information systems and to realize ultra-low power sensor nodes. However, it is difficult to operate conventional analog circuits based on amplifier at low voltage. Furthermore, PVT (Process, Voltage and Temperature) variation and random Vth variation degrade the minimum operation voltage and the energy efficiency in both digital and analog circuits. In this paper, extremely low power analog circuits based on comparator and switched capacitor as well as extremely low power digital circuits are presented. Many kinds of circuit technologies are applied to cope with the variation problem. Finally, image processing SoC that integrates digital and analog circuits is presented, where improvement of total performance by a cooperation of analog circuits and digital circuits is demonstrated.

This paper proposes an ultra-low-power 5.5-GHz PLL which employs the new divide-by-4 injection-locked frequency divider (ILFD) and a class-C VCO with linearity-compensated varactor for low supply voltage operation. A forward-body-biasing (FBB) technique can decrease threshold voltage of MOS transistors, which can improve operation frequency and can widen the lock range of the ILFD. The FBB is also employed for linear-frequency-tuning of VCO under low supply voltage of 0.5V. The double-switch injection technique is also proposed to widen the lock range of the ILFD. The digital calibration circuit is introduced to control the lock-range of ILFD automatically. The proposed PLL was fabricated in a 65nm CMOS process. With a 34.3-MHz reference, it shows a 1-MHz-offset phase noise of -106dBc/Hz at 5.5GHz output. The supply voltage is 0.54V for divider and 0.5V for other components. Total power consumption is 0.95mW.

Voltage Regulator Module, called VRM is a dedicated module for supplying power to microprocessor units. Recently, significant improvement of microprocessor units arises new challenges for supplying stable power. For stable and efficient control, multiphase interleaved topology is often used in today's VRM. To achieve high performance VRM, a current sensing circuit with both high efficiency and high accuracy is demanded. To achieve high accuracy, thermal dependency is a problem to be solved. In this paper, a novel alternating voltage controlled current sensing method is proposed for suppressing thermal dependency. In the proposed method, a high frequency AC voltage is superposed on the gate-ON-voltage. Then, the AC channel current is generated, and its amplitude becomes proportional to inductor current. The AC channel current is detected through a LC filter. The proposed current sensing method is very effective for realizing a current mode control DC-DC converter. In first, we simulated the relationship between our proposed current sensing method and a electrical characteristic of a power MOSFET. We used a power MOSFET device model published by a manufacture in this simulation. From the results, we find the gate parasitic capacitance of power MOSFET effects on the sensitivity of the current sensing circuit. Besides, the power dissipation in a power MOSFET increases by the frequency of applied gate ac voltage. Moreover, the proposed current sensing circuit based on the proposed method was designed and simulated the operations by Hspice. From the results, the designed current sensing circuit based on the proposed method has enough wide sensing window from 3A to 30A for VRM applications. Moreover, comparing to the conventional current sensing circuits with the MOSFET ON-resistance, the error of the proposed current sensing circuit can be decreased over 25% near 100°C.

This paper gives a write voltage and read reference current generator considering temperature characteristics for multi-level Ge2Sb2Te5-based phase change memories. Since the optimum SET and RESET voltages linearly changes by the temperature, the voltage supply circuit must track this characteristic. In addition, the measurement results show that the read current depends on both read temperature and the write temperature and has exponential dependence on the read temperature. Thus, the binning technique is applied for each read and write temperature regions. The proposed variable TC generator can achieve below ±0.5 LSB precision from the measured differential non-linearity and integral non-linearity. As a result, the temperature characteristics of both the linear write voltage and the exponential read current can be tracked with the proposed variation tolerant linear temperature coefficient current generator.

For battery based real-time embedded systems, high performance to meet their real-time constraints and energy efficiency to extend battery life are both essential. Real-Time Dynamic Voltage Scaling (RT-DVS) has been a key technique to satisfy both requirements. This paper presents EccEDF (Enhanced ccEDF), an efficient algorithm based on ccEDF. ccEDF is one of the most simple but efficient RT-DVS algorithms. Its simple structure enables it to be easily and intuitively coupled with a real-time operating system without incurring any significant cost. ccEDF, however, overlooks an important factor in calculating the available slacks for reducing the operating frequency. It calculates the saved utilization simply by dividing the slack by the period without considering the time needed to run the task. If the elapsed time is considered, the maximum utilization saved by the slack on completion of the task can be found. The proposed EccEDF can precisely calculate the maximum unused utilization with consideration of the elapsed time while keeping the structural simplicity of ccEDF. Further, we analytically establish the feasibility of EccEDF using the fluid scheduling model. Our simulation results show that the proposed algorithm outperforms ccEDF in all simulations. A simulation shows that EccEDF consumes 27% less energy than ccEDF.

We report the successful operation of a low-power arithmetic logic unit (ALU) based on a low-voltage rapid single-flux-quantum (LV-RSFQ) logic circuit, whereby a dc bias current is fed to circuits from lowered constant-voltage sources through small resistors. Both the static and dynamic energy consumptions are reduced because of the reduction in the amplitudes of voltage pulses across the Josephson junctions, with a trade-off of slightly slower switching speeds. The designed bias voltage was set to 0.25mV, which is one-tenth that of our standard RSFQ circuit design. We investigated several issues related to such low-voltage operation, including margins and timing design. To achieve successful operation, we tuned the circuit parameters in the logic gate design and carefully controlled the timing by considering the interference of pulse signals. We show test results for the low-voltage ALU in on-chip high-speed testing. The circuit was fabricated using the AIST Nb/AlOx/Nb Advanced Process with a critical current density of 10kA/cm2. We verified that arithmetic and logical operations were correctly implemented and obtained dc bias margins of 18% at a target clock frequency of 20GHz and achieved a maximum clock frequency of 28GHz with a power consumption of 28µW. These experimental results indicate energy efficiency of 3.6 times that of the standard RSFQ circuit design.

A body bias generator (BBG) for fine-grained body biasing (FGBB) is proposed. The FGBB is effective to reduce variability and power consumption in a system-on-chip (SoC). Since FGBB needs a number of BBGs, the BBG is preferred to be implemented in cell-based design procedure. In the cell-based design, it is inefficient to provide an extra supply voltage for BBGs. We invented a BBG with switched capacitor configuration and it enables BBG to operate with wide range of the supply voltage from 0.6V to 1.2V. We fabricated the BBG in a 65nm CMOS process to control 0.1mm2 of core circuit with the area overhead of 1.4% for the BBG.