By using a quadratic compensation slope, a CMOS current-mode buck DC-DC converter with constant frequency characteristics over wide input and output voltage ranges has been developed. The use of a quadratic slope instead of a conventional linear slope makes both the damping factor in the transfer function and the frequency bandwidth of the current feedback loop independent of the converter's output voltage settings. When the coefficient of the quadratic slope is chosen to be dependent on the input voltage settings, the damping factor in the transfer function and the frequency bandwidth of the current feedback loop both become independent of the input voltage settings. Thus, both the input and output voltage dependences in the current feedback loop are eliminated, the frequency characteristics become constant, and the frequency bandwidth is maximized. To verify the effectiveness of a quadratic compensation slope with a coefficient that is dependent on the input voltage in a buck DC-DC converter, we fabricated a test chip using a 0.18 µm high-voltage CMOS process. The evaluation results show that the frequency characteristics of both the total feedback loop and the current feedback loop are constant even when the input and output voltages are changed from 2.5 V to 7 V and from 0.5 V to 5.6 V, respectively, using a 3 MHz clock.

In this paper, a theoretical analysis of current-controlled (CC-) MOS current mode logic (MCML) is reported. Furthermore, the circuit performance of the CC-MCML with the auto-detection of threshold voltage (Vth) fluctuation is evaluated. The proposed CC-MCML with the auto-detection of Vth fluctuation automatically suppresses the degradation of circuit performance induced by the Vth fluctuations of the transistors automatically, by detecting these fluctuations. When a Vth fluctuation of ± 0.1 V occurs on the circuit, the cutoff frequency of the circuit is increased from 0 Hz to 3.5 GHz by using the proposed CC-MCML with the auto-detection of Vth fluctuation.

524,288 NbN-based Josephson junctions were integrated to produce a programmable Josephson voltage standard (PJVS) on a die of 15 mm 15 mm, and the PJVS circuit was cooled to 10 K using a cryocooler and operated with a current margin of about 1.0 mA. Although an output voltage of 10 V was required for a voltage standard, the circuit was designed to generate the maximum output voltage of 17 V because it was difficult to avoid a reduction of the output voltage due to defects. Although a perfect chip without any defect was rarely fabricated, the high voltage chip that generated at least 10 V was fabricated with the fabrication yield of larger than 30%. The fabrication yield was also improved by optimizing the film growth conditions to reduce the film stress and the number of particles. Applications for a secondary voltage standard and an ac Josephson voltage standard are also described.

This paper proposes a dual-conduction class-C VCO for ultra-low supply voltages. Two cross-coupled NMOS pairs with different bias points are employed. These NMOS pairs realize an impulse-like current waveform to improve the phase noise in the low supply conditions. The proposed VCO was implemented in a standard 0.18 µm CMOS technology, which oscillates at a carrier frequency of 4.5 GHz with a 0.2-V supply voltage. The measured phase noise is -104 dBc/Hz@1 MHz-offset with a power consumption of 114 µW, and the FoM is -187 dBc/Hz.

We propose a capacitive averaging technique applied to a double-tail latched comparator without a preamplifier for an offset reduction technique. Capacitive averaging can be introduced by considering the first stage of the double-tail latched comparator as a capacitive loaded amplifier. This makes it possible to reduce the offset voltage while preventing an increase in power dissipation. A positive feedback technique is also used for the first stage, which maximizes the effectiveness of the capacitive averaging. The capacitive averaging mechanism and the relationship between the offset reduction and the linearity of the amplifier is discussed in detail. Simulation results for a 90-nm CMOS process show that the proposed technique can reduce the offset voltage by 1/3.5 (3 mV) at a power dissipation of only 45 µW.

A 6–10-GHz broadband low noise amplifier (LNA) and transmitting amplifier (TA) for direct sequence ultra-wideband (DS-UWB) are presented. The LNA and TA are fabricated with the 0.18-µm 1P6M standard CMOS process. The CMOS LNA and TA are checked by on-wafer measurement with the DC supply voltage of 1.5 V. From 6–10 GHz, the broadband LNA exhibits a noise figure of 5.3–6.2 dB, a gain of 11–13.8 dB, a P1 dB of -15.7 - -10.8 dBm, a IIP3 of -5.5 - -1 dBm, a DC power consumption of 12 mW, and an input/output return loss higher than 11/12 dB, respectively. From 6–10 GHz, the broadband TA exhibits a gain of 7.6–10.5 dB, a OP1 dB of 2.8–6.1 dBm, a OIP3 of 12.3–15.1 dBm, and a PAE of 8.8–17.6% @ OP1 dB, and a η of 9.7–21.1% @ OP1 dB, and an input/output return loss higher than 6.8/3.2 dB, respectively.

An on-chip temperature compensation active bias circuit having tunable temperature slope has been proposed, and its application to an X-band GaAs FET monolithic microwave integrated circuit (MMIC) power amplifier (PA) is described. The proposed bias circuit can adjust the temperature slope of gate voltage according to the bias condition of the PA, and also realizes the higher temperature slope of the gate voltage by employing the diode and the FET which operates at near threshold voltage (Vt) in the bias circuit. As a result, the gain of PAs operated at any bias conditions is kept almost constant against temperature by applying the proposed bias circuit. Moreover, the proposed bias circuit can be integrated in the same chip with the MMIC PA since it does not need off-chip components, and operates with only negative voltage source. The fabricated results of the on-chip temperature compensation active bias circuit shows that the temperature slope of the gate voltage varies from 2.1 to 6.3 mV/, which is enough to compensate the gain of not only class-B PA but also class-A PA. The gain deviation of the developed GaAs FET MMIC PA with the proposed bias circuit has been reduced from 3.3 dB to 0.6 dB in the temperature range of 100.

In this paper, to clarify the thermal effect of the bridge for long lifetime contacts, the effects of heat conductivity on bridge break at different material contact pairs were discussed experimentally. To examine the relationship between the bridge and material, the electrode materials of the anode and the cathode were chosen as the same and the different material pairs in this experiment. Ag, AgPd60 and Pd were chosen as the electrode materials, because Ag, AgPd60 and Pd had the different thermal diffusivity. Firstly, the voltage waveforms in the bridge with different material pair were compared to the voltage waveform with the same material pair case. Secondary, the effects of heat conductivity on the break of bridge were discussed. In the results, the bridge voltage waveform depends on the electrode material at anode side. The length of the bridge at bridge break depends on the heat conductivity of the electrode material at anode side. This study provides the basic considerations on the thermal condition of the bridge break.

The address discharge characteristics formed when an address pulse is applied in AC plasma display panels are investigated by changing the ramp-down voltage during the reset period. The address discharge time lag can be reduced when the difference between the ramp-down voltage and the scan-low voltage is set at a high value during the ramp-down period because the loss of the wall charges accumulated between the scan (Y) and address (A) electrodes during the reset period is minimized. In addition, the voltage applied to the X electrode during the ramp-down period can prevent the voltage margin from reduction even though applying high voltage difference on the Y electrodes.

The past decade has seen a surge of research activities in the fields of mobile computing and wireless communication. In particular, recent technological advances have made portable devices, such as PDA, laptops, and wireless modems to be very compact and affordable. To effectively operate portable devices, energy efficiency and Quality of Service (QoS) provisioning are two primary concerns. Dynamic Voltage Scaling (DVS) is a common method for energy conservation for portable devices. However, due to the amount of data that needs to be dynamically handled in varying time periods, it is difficult to apply conventional DVS techniques to QoS sensitive multimedia applications. In this paper, a new adaptive DVS algorithm is proposed for QoS assurance and energy efficiency. Based on the repeated learning model, the proposed algorithm dynamically schedules multimedia service requests to strike the appropriate performance balance between contradictory requirements. Experimental results clearly indicate the performance of the proposed algorithm over that of existing schemes.

An analog controlled Variable Gain LNA (VGLNA) with tunable operating frequency bands is reported. The analog control circuit for the continuous gain variation is proposed as a low voltage version. The fabricated LNA based on 0.18 µm CMOS shows a gain range of 15-12 dB (27 dB gain control), a noise figure (NF) of 2 dB, and an IIP3 of -10 dBm while 5 mA is drawn from a 1.2 V supply over the frequency range of 470880 MHz.

In this paper, a novel switched-capacitor DC-DC converter with pulse density and width modulation (PDWM) is proposed with reduced output ripple at variable output voltages. While performing pulse density modulation (PDM), the proposed PDWM modulates the pulse width at the same time to reduce the output ripple with high power efficiency. The prototype chip was implemented using 65 nm CMOS process. The switched-capacitor DC-DC converter has 0.2-V to 0.47-V output voltage and delivers 0.25-mA to 10-mA output current from a 1-V input supply with a peak efficiency of 87%. Compared with the conventional PDM scheme, the proposed switched-capacitor DC-DC converter with PDWM reduces the output ripple by 57% in the low output voltage region with the efficiency penalty of 2%.

Dependence of within-die delay variations on power supply voltage (VDD) is measured down to 0.4 V. The VDD dependence of the within-die delay variation of manual layout and irregular auto place and route (P&R) layout are compared for the first time. The measured relative delay (=sigma/average) variation difference between the manual layout and the P&R layout decreases from 1.56% to 0.07% with reducing VDD from 1.2 V to 0.4 V, because the random delay variations due to the random transistor variations dominate total delay variations instead of the delay variations due to interconnect length variations at low VDD.

Clocked cascade voltage switch logic (C2VSL) circuits with gated feedback were newly designed for synchronous systems. In order to investigate single event transient (SET) effects on the C2VSL circuits, SET effects on C2VSL EX-OR circuits were analyzed using SPICE. Simulation results have indicated that the C2VSL have increased tolerance to SET.

We propose a subthreshold Static Random Access Memory (SRAM) circuit architecture with improved write ability. Even though the circuits can achieve ultra-low power dissipation in subthreshold digital circuits, the performance is significantly degraded with threshold voltage variations due to the fabrication process and temperature. Because the write operation of SRAM is prone to failure due to the unbalance of threshold voltages between the nMOSFET and pMOSFET, stable operation cannot be ensured. To achieve robust write operation of SRAM, we developed a compensation technique by using an adaptive voltage scaling technique that uses an on-chip threshold voltage monitoring circuit. The monitoring circuit detects the threshold voltage of a MOSFET with the on-chip circuit configuration. By using the monitoring voltage as a supply voltage for SRAM cells, write operation can be compensated without degrading cell stability. Monte Carlo simulations demonstrated that the proposed SRAM architecture exhibits a smaller write operation failure rate and write time variation than a conventional 6T SRAM.

A 0.6-V voltage shifter and a 0.6-V clocked comparator are presented for sampling correlation-based impulse radio UWB receiver. The voltage shifter is used for a novel split swing level scheme-based CMOS transmission gate which can reduce the power consumption by four times. Compared to the conventional voltage shifter, the proposed voltage shifter can reduce the required capacitance area by half and eliminate the non-overlapping complementary clock generator. The proposed 0.6-V clocked comparator can operate at 100-MHz clock with the voltage shifter. To reduce the power consumption of the conventional continuous-time comparator based synchronization control unit, a novel clocked-comparator based control unit is presented, thereby achieving the lowest energy consumption of 3.9 pJ/bit in the correlation-based UWB receiver with the 0.5 ns timing step for data synchronization.

In this paper, Digital Low Dropout Regulator (LDO) is proposed to provide the low noise and tunable power supply voltage to the 0.5-V near-threshold logic circuits. Because the conventional LDO feedback-controlled by the operational amplifier fail to operate at 0.5 V, the digital LDO eliminates all analog circuits and is controlled by digital circuits, which enables the 0.5-V operation. The developed digital LDO in 65 nm CMOS achieved the 0.5-V input voltage and 0.45-V output voltage with 98.7% current efficiency and 2.7-µA quiescent current at 200-µA load current. Both the input voltage and the quiescent current are the lowest values in the published LDO's, which indicates the good energy efficiency of the digital LDO at 0.5-V operation.

We fabricated metal-oxide-semiconductor (MOS) devices with Pt/Ta2O5 gate stacks and investigated their electrical and structural properties. As increasing RF magnetron sputter-deposition time of Ta2O5 film, the values of equivalent oxide thickness (EOT) and flat band voltage (VFB) increase whilst the density of interfacial trap (Dit) gradually decreases. The effective metal work function (Φm,eff) of Pt metal gate, extracted from the relations of EOT versus VFB are calculated to be ∼5.29 eV, implying that Fermi-level pinning in Ta2O5 gate dielectric is insignificant.

CMOS SoCs can reduce power consumption while maintaining performance by adopting voltage scaling (VS) technologies. The operating speed of the level converter (LC) strongly affects the effectiveness of VS technologies. However, PVT variations can cause serious problems to the LC, because the state-of-the-art LC designs do not give enough attention to this issue. In this work, we proposed to analyze the impact of PVT variations on the performance of the LC using a previously developed heuristic sizing methodology. Based on the evaluation results from different operating corners with different offset voltages and temperatures, we proposed a variation-tolerant LC that achieves both high performance and low energy with a high tolerability for PVT variations.

This paper presents a 7 GHz differential current-reused voltage-controlled oscillator (CR-VCO) with low power consumption and low phase noise using 0.18-µm CMOS technology. The output power of this CR-VCO is enhanced by utilizing a trifilar-transformer-feedback technique. The lower phase noise is achieved by the more symmetric voltage swings resulting from the improved balance of switching current. At a 1.5-V DC supply voltage, the power dissipation is only 3.4 mW. The total tuning range is 1.4 GHz (17.9%) as the tuning voltage ranges from 0 V to 1.8 V. The optimum phase noise is around -117.3 dBc/Hz at a frequency offset of 1 MHz from the center frequency of 7.07 GHz. The corresponding output power is around -6.8 dBm. For the proposed CR-VCO, the calculated figures-of-merit, FOM and FOMT , are -188.9 and -193.9 dBc/Hz, respectively.