Air discharge immunity testing for electronic equipment is specified in the standard 61000-4-2 of the International Eelectrotechnical Commission (IEC) under the climatic conditions of temperature (T) from 15 to 35 degrees Celsius and relative humidity (RH) from 30 to 60%. This implies that the air discharge testing is likely to provide significantly different test results due to the wide climatic range. To clarify effects of the above climatic conditions on air discharge testing, we previously measured air discharge currents from an electrostatic discharge (ESD) generator with test voltages from 2kV to 15kV at an approach speed of 80mm/s under 6 combinations of T and RH in the IEC specified range and non-specified climatic range. The result showed that the same absolute humidity (AH), which is determined by T and RH, provides almost the identical waveforms of the discharge currents despite different T and RH, and also that the current peaks at higher test voltages decrease as the AH increases. In this study, we further examine the combined effects of air discharges on test voltages, T, RH and AH with respect to two different approach speeds of 20mm/s and 80mm/s. As a result, the approach speed of 80mm/s is confirmed to provide the same results as the previous ones under the identical climatic conditions, whereas at a test voltage of 15kV under the IEC specified climatic conditions over 30% RH, the 20mm/s approach speed yields current waveforms entirely different from those at 80mm/s despite the same AH, and the peaks are basically unaffected by the AH. Under the IEC non-specified climatic conditions with RH less than 20%, however, the peaks decrease at higher test voltages as the AH increases. These findings obtained imply that under the same AH condition, at 80mm/s the air discharge peak is not almost affected by the RH, while at 20mm/s the lower the RH is, the higher is the peak on air discharge current.

The authors have been investigating the deterioration process of Au-plated slip-ring and Ag-Pd brush system with lubricant to realize stable and long lifetime. Through the past tests, it can be made clear that lubricant is very important for long lifetime, and a simple model of the deterioration process was proposed. However, it is still an issue how the lubricant is deteriorated and also what the relation between lubricant deterioration and contact voltage behavior is. In this paper, the contact voltage waveforms were regularly recorded during the test, and analyzed to obtain the time change of peak voltage and standard deviation during one rotation. Based on these results, it is discussed what happens at the interface between ring and brush with the lubricant. And the following results are made clear. The fluctuation of voltage waveforms, especially peaks of pulse-like fluctuation more easily occurs for minus rings than for plus rings. Further, peak values of the pulse-like fluctuation rapidly decreases and disappear at lower rotation speed as mentioned in the previous works. In addition, each peaks of the pulse-like fluctuation is identified at each position of the ring periphery. From these results, it can be assumed that lubricant film exists between brush and ring surface and electric conduction is realized by tunnel effect. In other words, it can be made clear that the fluctuation would be caused by the lubricant layer, not only by the ring surface. Finally, an electric conduction model is proposed and the above results can be explained by this model.

With increasing technology scaling and the use of lower voltages, more research interest is being shown in variability-tolerant analog front end design. In this paper, we describe an adaptive amplitude control transmitter that is operated using differential signaling to reduce the temperature variability effect. It enables low power, low voltage operation by synergy between adaptive amplitude control and Vth temperature variation control. It is suitable for high-speed interface applications, particularly cable interfaces. By installing an aggressor circuit to estimate transmitter jitter and changing its frequency and activation rate, we were able to analyze the effects of the interface block on the input buffer and thence on the entire system. We also report a detailed estimation of the receiver clock-data recovery (CDR) operation for transmitter jitter estimation. These investigations provide suggestions for widening the eye opening of the transmitter.

This paper discusses and elaborates an analytical model of a multi-stage switched-capacitor (SC) voltage boost converter (VBC) for low-voltage and low-power energy harvesting systems, because the output impedance of the VBC, which is derived from the analytical model, plays an important role in the VBC's performance. In our proposed method, we focus on currents flowing into input and output terminals of each stage and model the VBCs using switching frequency f, charge transfer capacitance CF, load capacitance CL, and process dependent parasitic capacitance's parameter k. A comparison between simulated and calculated results showed that our model can estimate the output impedance of the VBC accurately. Our model is useful for comparing the relative merits of different types of multi-stage SC VBCs. Moreover, we demonstrate the performance of a prototype SC VBC and energy harvesting system using the SC VBC to show the effectiveness and feasibility of our proposed design guideline.

This paper presents two ultra-low voltage and high performance VCO ICs with two novel transformer-based harmonic tuned tanks. The first proposed harmonic tuned tank effectively shapes the pseudo-square drain-node voltage waveform for close-in phase noise reduction. To compensate the voltage drop caused by the transformer, an improved second tank is proposed. It not only has tuned harmonic impedance but also provides a voltage gain to enlarge the output voltage swing over supply voltage limitation. The VCO with second tank exhibits over 3 dB better phase noise performance in 1/f2 region among all tuning range. The two VCO ICs are designed, fabricated and measured on wafer in 45-nm SOI CMOS technology. With only 0.3 V supply voltage, the proposed two VCO ICs exhibit best phase noise of -123.3 and -127.2 dBc/Hz at 10 MHz offset and related FoMs of -191.7 and -192.2 dBc/Hz, respectively. The frequency tuning ranges of them are from 14.05 to 15.14 GHz and from 14.23 to 15.68 GHz, respectively.

This paper describes a method of measuring the unsymmetric voltage of conducted noise using a floating measurement system. Here, floating means that there is no physical connection to the reference ground. The method works by correcting the measured voltage to the desired unsymmetric voltage using the capacitance between the measurement instrument and the reference ground plane acting as the return path of the conducted electromagnetic noise. The existing capacitance measurement instrument needs a probe in contact with the ground, so it is difficult to use for on-site measurement of stray capacitance to ground at troubleshooting sites where the ground plane is not exposed or no ground connection point is available. The authors have developed a method of measuring stray capacitance to ground that does not require physical connection of the probe to the ground plane. The developed method can be used to estimate the capacitance between the measurement instrument and ground plane even if the distance and relative permittivity of the space are unknown. And a method is proposed for correcting the voltage measured with the floating measurement system to obtain the unsymmetric voltage of the noise by using the measured capacitance to ground. In the experiment, the unsymmetric voltage of a sinusoidal wave transmitting on a co-axial cable was measured with a floating oscilloscope in a shield room and the measured voltage was corrected to within 2dB of expected voltage by using the capacitance measured with the developed method. In addition, the voltage of a rectangular wave measured with the floating oscilloscope, which displays sag caused by the stray capacitance to ground, was corrected to a rectangular wave without sag. This means that the phase of the unsymmetric voltage can also be corrected by the measured stray capacitance. From these results, the effectiveness of the proposed methods is shown.

In this paper, an enhanced well-changed GGNMOS (EW-GGNMOS) is proposed and demonstrated. The new device has the same topology as the conventional 3.3V GGNMOS, except that its well has been changed to the 1.2V p-well. Attributed to higher doping concentration, resulting in a much lower trigger voltage and desirable turn-on uniformity compared to conventional 3.3V GGNMOS. Therefore, we can use EW-GGNMOS as a 3.3V ESD protection device without any additional process.

A fully integrated 16-phase 8-branch Dickson charge pump is proposed and implemented to decrease the power dissipation due to parasitic capacitance at the bottom plate of the boost capacitor. By using the charge recycling concept, 87% of the power consumption related to parasitic capacitance is saved. In a 4-stage version of this charge pump, a maximum power efficiency of 41% is achieved at 35µA output current and 11V output voltage from a 3.3V supply voltage. The proposed multi-branch charge pump can also reach a very low output voltage ripple of only 0.146% at a load resistance of 1MΩ, which is attributed to the fact that the 8-branch charge pump can transfer charges to the output node eight times consecutively during one clock period. In addition, a high voltage gain of 4.6 is achieved in the 4-stage charge pump at light load conditions. The total chip area is 0.57mm2 in a 0.35µm HV CMOS technology.

In partially depleted SOI (PD-SOI) technology, the SCR-based protection device is desired due to its relatively high robustness, but be restricted to use because of its inherent low holding voltage (Vh) and high triggering voltage (Vt1). In this paper, the body-tie side triggering diode inserting silicon controlled rectifier (BSTDISCR) is proposed and verified in 180 nm PD-SOI technology. Compared to the other devices in the same process and other related works, the BSTDISCR presents as a robust and latchup-immune PD-SOI ESD protection device, with appropriate Vt1 of 6.3 V, high Vh of 4.2 V, high normalized second breakdown current (It2), which indicates the ESD protection robustness, of 13.3 mA/µm, low normalized parasitic capacitance of 0.74 fF/µm.

In this paper, we propose the low voltage CMOS current mode reference circuit using self-regulator with adaptive biasing technique. It drastically reduces the line sensitivity (LS) of the output voltage and the power supply voltage dependence of the temperature coefficient (TC). The self-regulator used in the proposed circuit adaptively generates the minimum voltage required the reference core circuit following the PVT (process, voltage and temperature) conditions. It makes possible to improve circuit performances instead of slightly increasing minimum power supply voltage. This proposed circuit has been designed and evaluated by SPICE simulation using TSMC 65nm CMOS process with 3.3V (2.5V over-drive) transistor option. From simulation results, LS is reduced to 0.0065%/V under 0.8V < VDD < 3.0V. TC is 67.6ppm/°C under the condition that the temperature range is from -40°C to 125°C and VDD range is from 0.8V to 3.0V. The power supply rejection ratio (PSRR) is less than -80.4dB when VDD is higher than 0.8V and the noise frequency is 100Hz. According to the simulation results, we could confirm that the performances of the proposed circuit are improved compared with the conventional circuit.

This paper presents two ultra-low voltage and high performance VCO ICs with novel harmonic tuned LC tank which provides different harmonic impedance and shapes the pseudo-square drain voltage waveform of transistors. In the novel tank, two additional inductors are connected between the drains of the cross-coupled pMOSFETs and the conventional LC tank, and they effectively decrease second harmonic load impedance and increase third harmonic load impedance of the transistors. In this paper, the novel harmonic tuned LC tank is applied to two different structure VCOs. These two VCOs exhibit over 2 dB better phase noise performance than conventional LC tank VCOs among all tuning range. The conventional and proposed VCO ICs are designed, fabricated and measured on wafer in 45-nm SOI CMOS technology. With novel harmonic tuned LC tank, the novel two VCOs exhibit measured best phase-noise of -125.7 and -129.3 dBc/Hz at 10 MHz offset and related FoM of -190.2 and -190.5 dBc/Hz at a supply voltage of 0.3 V and 0.35 V, respectively. Frequency tuning range of the two VCOs are from 13.01 to 14.34 GHz and from 15.02 to 16.03GHz, respectively.

Ring voltage-controlled-oscillators (VCOs) are increasingly being used to design ΔΣ ADCs. They have the merits of simple, highly digital and low-voltage tolerant, making them attractive alternatives for the classic scaling-unfriendly operational-amplifier-based methodology. This paper aims to provide a summary on the advancement of VCO-based ΔΣ ADCs. The scope of this paper includes the basics and motivations behind the VCO-based ADCs, followed by a survey covering a wide range of architectures and circuit techniques in both continuous-time (CT) and discrete-time (DT) implementation, and will discuss the key insights behind the contributions and drawbacks of these architectures.

A low voltage stochastic flash ADC (analog-to-digital converter) is presented, with an inverter-based comparative unit which is used to replace comparator for comparison. Aiming at the low voltage and low power consumption, a key of our design is in the simplicity of the structure. The inverter-based comparative unit replacing a comparator enables us to decrease the number of transistors for area saving and power reduction. We insert the inverter-chain in front of the comparative unit for the signal stability and discuss an appropriate circuit structure for the resolution by analyzing three different ones. Finally, we design the whole stochastic flash ADC for verifying our idea, where the supply voltage can go down to 0.6V on the 65nm CMOS process, and through post-layout simulation result, we can observe its advantage visually in voltage, area and power consumption.

Adaptive voltage scaling is a promising approach to overcome manufacturing variability, dynamic environmental fluctuation, and aging. This paper focuses on error prediction based adaptive voltage scaling (EP-AVS) and proposes a mean time to failure (MTTF) aware design methodology for EP-AVS circuits. Main contributions of this work include (1) optimization of both voltage-scaled circuit and voltage control logic, and (2) quantitative evaluation of power saving for practically long MTTF. Experimental results show that the proposed EP-AVS design methodology achieves 38.0% power saving while satisfying given target MTTF.

Design of an equivalent slew-rate monolithic pulse generator using bipolar-CMOS-DMOS (BCD) technology for medical ultrasound transmitters is presented in this paper. The pulse generator employs a floating capacitive coupling level-shifter architecture to produce a high-voltage (Vpp=80V) output. The performance of equivalent slew-rate in the rising and falling edge is achieved by carefully choosing the value of coupling capacitors and the size of the final stage high-voltage MOSFETs of the pulse generator. The measured output pulses show the rising and falling time of 8.6nsec and 8.5nsec, respectively with second harmonic distortion down to -40dBc, indicating the designed pulse generator can be used for advanced ultrasonic harmonic imaging systems.

We fabricate and characterize a GaAsSb/InGaAs backward diode (BWD) toward a realization of high sensitivity zero bias microwave rectification for RF wave energy harvest. Lattice-matched p-GaAsSb/n-InGaAs BWDs were fabricated and their current-voltage (I-V) characteristics and S-parameters up to 67 GHz were measured with respect to several sorts of mesa diameters in μm order. Our theoretical model and analysis are well fitted to the measured I-Vs on the basis of WKB approximation of the transmittance. It is confirmed that the interband tunneling due to the heterojunction is a dominant transport mechanism to exhibit the nonlinear I-V around zero bias regime unlike recombination or diffusion current components on p-n junction contribute in large current regime. An equivalent circuit model of the BWD is clarified by confirming theoretical fitting for frequency dependent admittance up to 67 GHz. From the circuit model, eliminating the parasitic inductance component, the frequency dependence of voltage sensitivity of the BWD rectifier is derived with respect to several size of mesa diameter. It quantitatively suggests an effectiveness of mesa size reduction to enhance the intrinsic matched voltage sensitivity with increasing junction resistance and keeping the magnitude of I-V curvature coefficient.

We report the control of threshold voltage (Vth) for low voltage (5V) operation in OFET by using double gate dielectric layers composed of poly (vinyl cinnamate) and SiO2. We succeeded in realizing a driving voltage of -5V and Vth shift by c.a. 1.0V. And programmed Vth was almost unchanged for 104s, where the relative change of Vth remains more than 99%.

Forward converter is most suitable for low voltage and high current applications such as LEDs, battery chargers, EHV etc. The active clamp transformer reset technique offers many advantages over conventional single-ended reset techniques, including lower voltage stress on the main switch, the ability to switch at zero voltage and duty cycle operation above 50 percent. Several papers have compared the functional merits of the active clamp over the more extensively used RCD clamp, third winding and resonant reset techniques. This paper discusses about a center clamp technique with one common core reset circuit making it suitable for wide input voltage applications with extended duty cycle.

This paper describes a broadband low phase noise VCO implemented in 0.13 µm CMOS process. A 1-bit switched varactor and a 4-bit capacitor array are adopted in cooperation with the automatic frequency calibration (AFC) circuit to lower the VCO tuning gain (KVCO), with a measured AFC time of 6 µs. Several noise reduction techniques are exploited to minimize the phase noise of the VCO. Measurement results show the VCO generates a high frequency range from 11.37 GHz to 14.8 GHz with a KVCO of less than 270 MHz/V. The prototype exhibits a phase noise of -114.6 dBc/Hz @ 1 MHz at 14.67 GHz carrier frequency and draws 10.5 mA current from a 1.2 V supply. The achieved figure-of-merits (FoM=-186.9dBc/Hz, FoMT=-195.3dBc/Hz) favorably compares with the state-of-the-art.

This paper presents a high step-up DC-DC converter for low voltage sources such as solar cells, fuel cells and battery banks. A novel non isolated Zero-Voltage Switching (ZVS) interleaved DC-DC boost converter condition is introduced. In this converter, by using coupled inductor and active clamp circuit, the stored energy in leakage inductor is recycled. Furthermore, ZVS turn on condition for both main and clamp switches are provided. The active clamp circuit suppresses voltage spikes across the main switch and the voltage of clamp capacitor leads to higher voltage gain. In the proposed converter, by applying interleaved technique, input current ripple and also conduction losses are decreased. Also, with simple and effective method without applying any additional element, the input ripple due to couple inductors and active clamp circuit is cancelled to achieve a smooth low ripple input current. In addition, the applied technique in this paper leads to increasing the life cycle of circuit components which makes the proposed converter suitable for high power applications. Finally an experimental prototype of the presented converter with 40 V input voltage, 400 V output voltage and 200 W output power is implemented which verifies the theoretical analysis.