The proposed built-in Power-Cut scheme intended for a wide range of dynamically data retaining memories including embedded SoC memories enables the system-level power management to handle SoC on which the several high density and low voltage scalable memory macros are embedded. This scheme handles the deep standby mode in which the SoC memories keep the stored data in the ultra low standby current, and quick recovery to the normal operation mode and precise power management are realized, in addition to the conventional full power-off mode in which the SoC memories stay in the negligibly low standby current but allow the stored data to disappear. The unique feature of the statically or dynamically changeable internal voltages of memory in the deep standby mode brings about much further reduction of the standby current. This scheme will contribute to the further lowering power of the mobile applications requiring larger memory capacity embedded SoC memories.

A wide range CMOS voltage detector with low current consumption consisting of CMOS inverters operating in both weak inversion and saturation region is proposed. A terminal of power supply for CMOS inverter can be expanded to a signal input terminal. A voltage-detection point and hysteresis characteristics of the proposed circuit can be designed by geometrical factor in MOSFET and an external bias voltage. The core circuit elements are fabricated in standard 0.18 µm CMOS process and measured to confirm the operation. The detectable voltage is from 0.3 V to 1.8 V. The current consumption of voltage detection, standby current, is changed from 65 pA for Vin = 0.3 V to 5.5 µA for Vin = 1.8 V. The thermal characteristics from 250 K to 400 K are also considered. The measured temperature coefficient of the proposed voltage-detector core operating in weak inversion region is 4 ppm/K and that in saturation region is 10 ppm/K. The proposed voltage detector can be implemented with tiny chip area and is expected to an on-chip voltage detector of power supply for mobile application systems.

The sub-threshold R-MOSFET resistor structure which enables tuning range extension below the threshold voltage in the MOSFET with moderate to weak inversion operation is analyzed in detail. The principal operation of the sub-threshold resistor is briefly described. The analysis of its characteristic based on approximations of a general MOS equation valid for all regions is given along with discussion on design implication and consideration. Experiments and simulations are provided to validate the theoretical analysis and design, and to verify the feasibility at a supply voltage as low as 0.5 V using a low-threshold devices in a 1.8-V 0.18 µm CMOS process.

A novel voltage level controller for low-power charge pump converters will be presented in this paper. The proposed voltage level controller would react according to the pumped voltage in the charge-transfer-switch (CTS) converter. For the CTS circuit, the pumping operation would be degraded by the charge sharing effect in the auxiliary switch path. In this study, a voltage shifter was used as the voltage level controller to overcome this serious problem without consuming too much chip area. The simulation results showed that the converter can accept a rated input of 1.5 V and generated an output up to 8 V based on the TSMC 0.35-µm CMOS technology. The layout consumed an area of 125*160 µm2. The highest output obtained in measuring the real chip was 5.5 V which is primarily due to the limitation that the transistor could tolerated. The largest load was estimated as high as 6 mW which is large enough for on-chip application.

The control of the organic field-effect transistor characteristics is necessary to produce the integrated circuits using organic semiconductors. Variations in the poly (3-hexylthiophene) field-effect transistor characteristics upon post-treatment such as thermal treatment and voltage treatment in N2 atmosphere have been investigated. The controllability and reproducibility of the threshold voltage and mobility were achieved as a result of the post-treatments.

In this letter, two OTAs with MOSFETs operating in the weak inversion region are proposed. One of the OTAs uses the exponential-logarithm transformation algorithm. Furthermore, the other realizes the high-linearity characteristics due to a small fluctuation of the common-terminal voltage of differential pair. The performance of the proposed OTAs was confirmed by HSPICE simulation.

In real-time embedded systems, there is requirement for adapting both energy consumption and Quality of Services (QoS) of tasks according to their importance. This paper proposes an adaptive power-aware resource allocation method to resolve a trade-off between the energy consumption and QoS levels according to their importance with guaranteeing fairness. The proposed resource allocator consists of two components: the total resource optimizer to search for the optimal total resource and QoS-fairness-based allocator to allocate resource to tasks guaranteeing the fairness. These components adaptively achieve the optimal resource allocation formulated by a nonlinear optimization problem with the time complexity O(n) for the number of tasks n even if tasks' characteristics cannot be identified precisely. The simulation result shows that the rapidness of the convergence of the resource allocation to the optimal one is suitable for real-time systems with large number of tasks.

A novel electronically tunable high input impedance voltage-mode multifunction filter with single inputs and three outputs employing two single-output-operational transconductance amplifiers, one differential difference current conveyor and two capacitors is proposed. The presented filter can be realized the highpass, bandpass and lowpass functions, simultaneously. The input of the filter exhibits high input impedance so that the synthesized filter can be cascaded without additional buffers. The circuit needs no any external resistors and employs two grounded capacitors, which is suitable for integrated circuit implementation.

The polycrystalline silicon (poly-Si) TFT has two insulator interfaces between the polycrystalline silicon and front and back insulators. These interfaces have trap states, which affect the characteristics of poly-Si TFT. In the silicon-on-insulator (SOI) technology area, using the dual-gated, fully-depleted SOI MOSFET under the depleted back-channel condition, the back-interface trap density can be calculated through the front-channel threshold voltage and film thicknesses. The front-interface trap density is also evaluated changing the roles of both gates. This evaluation method for front- and back- interface trap densities is called the threshold-voltage method. To apply this threshold-voltage method to the "medium-thickness" poly-Si TFT, of which the channel is not fully depleted in normal single gate bias operation, the biases for both front and back gates are controlled to realize full depletion. Under the fully-depleted condition, the front- or back- threshold voltage of poly-Si TFT is carefully extracted by the second-derivative method changing back- and front- gate biases. We evaluated the front- and back- interface trap densities not only for normal operation but also under stress. To evaluate the bias and temperature stress effect, we used two types of samples, which are made by different processes. The evaluated front- and back- interface trap densities for both samples in initial state are around 51011 to 1.31012 cm-2eV-1, which are almost the same as the reported values. Applying bias and temperature stress shows the variation of these interface-trap densities. Samples with large shifts of the front-channel threshold voltage show large trap density variation. On the other hand, samples with small threshold voltage shifts show small trap density variation. The variation of the back-interface trap density during the stress application showed a correlation to the front-channel threshold voltage shift.

Source-drain follower has been designed and implemented for monolithically integrated biosensor array. The circuit acts as a voltage follower, in which a sensing transistor is operated at fixed gate-source and gate-drain voltages. It operates at 10 nW power dissipation. The wide-swing cascode configurations are investigated in constant and non-constant biasing methods. The constant biased cascode source-drain follower has the merit of small cell size. The chip was fabricated using 1.2 µm standard CMOS technology, and a wide range of operation between 1 nW and 100 µW was demonstrated. The accuracy of the voltage follower was 30 mV using minimum sized transistors, due to the variation of threshold voltage. The error in the output except for the threshold voltage mismatch was less than 10 mV. The temperature dependence of the output was 0.11 mV/. To improve the input voltage range and accuracy, non-constant biased cascode source-drain follower is examined. The sensor cell is designed for 10 mV accuracy and the cell size is 105.3µm 81.4 µm in 1.2 µm CMOS design rules. The sensor cell was fabricated and showed that the error in the output except for the threshold voltage mismatch was less than 2 mV in a range of total current between 3 nA and 10 µA and in a temperature range between 30 and 100.

This paper proposes a low-voltage high-speed sample-and-hold (S/H) structure with excellent power efficiency. Based on the switched-opamp technique, an inverse-flip-around architecture which maximizes the feedback factor is employed in the proposed S/H. A skew-insensitive double-sampling mechanism is presented to increase the throughput by a factor of two while eliminating the timing mismatch associated with double-sampling circuits. Furthermore, a dual-input dual-output opamp is proposed to incorporate double-sampling into the switched-opamp based S/H. This opamp also removes the memory effect in double-sampling circuitry and features fast turn-on time to improve the speed performance in switched-opamp circuits. Simulation results using a 0.13-µm CMOS process model demonstrates the proposed S/H circuit has a total-harmonic-distortion of -67.3 dB up to 250 MSample/s and a 0.8 VPP input range at 0.8 V supply. The power consumption is 3.5 mW and the figure-of-merit is only 7.4 fJ/step.

Multiple supply voltage (MSV) is an effective scheme to achieve low power. Recent works in MSV are based on physical level and aim at reducing physical overheads, but all of them do not consider level converter, which is one of the most important issues in dual-vdd design. In this work, a logic and layout aware methodology and related algorithms combining voltage assignment and placement are proposed to minimize the number of level converters and to implement voltage islands with minimal physical overheads. Experimental results show that our approach uses much fewer level converters (reduced by 83.23% on average) and improves the power savings by 16% on average compared to the previous approach [1]. Furthermore, the methodology is able to produce feasible placement with a small impact to traditional placement goals.

In this letter a new structure of multifunctional frequency filter using a universal voltage conveyor (UVC) is presented. The multifunctional circuit can realize a low-pass, high-pass and band-pass filter. All types of frequency filter can be realized as inverting or non-inverting. Advantages of the proposed structure are the independent control of the quality factor at the cut-off frequency and the low output impedance of output terminals. The computer simulations and measuring of particular frequency filters are depicted.

This letter presents a 0.5 V low-voltage op-amp in a standard 0.18 µm CMOS process for switched-capacitor circuits. Unlike other two-stage 0.5 V op-amp architectures, this op-amp consists of CMOS inverters that utilize floating voltage sources and forward body bias for obtaining high-speed operation. And two improved common-mode rejection circuits are well combined to achieve low power and chip area reduction. Simulation results indicate that the op-amp has an open-loop gain of 62 dB, and a high unity gain bandwidth of 56 MHz. The power consumption is only 350 µW.

Arc discharge generated by breaking electrical contact is considered as a main source of an undesired electromagnetic (EM) noise. To clarify mechanism of generation of the EM noise, feature extraction of bridge and short-time arc waveforms generated by slowly breaking Ag contact was discussed experimentally. The short-duration time arc before the ignition of the continuous metallic arc discharge was observed. The highest probability density voltage is defined as short-arc sustainable voltage (SASV). The relationship between SASV and duration of short-time arc was quantified experimentally. It is revealed that as the arc voltage of the short-time arc is higher, its duration becomes longer.

A fuzzy logic control battery equalizing controller (FLC-BEC) is adopted to control the cell voltage balancing process for a series connected Li-ion battery string. The proposed individual cell equalizer (ICE) is based on the bidirectional Cuk converter operated in the discontinuous capacitor voltage mode (DCVM) to reduce the switching loss and improve equalization efficiency. The ICE with the proposed FLC-BEC can reduce the equalizing time, maintain safe operations during the charge/discharge state and increase the battery string capacity.

This paper presents a real-time decision support system (RDSS) based on artificial intelligence (AI) for voltage collapse avoidance (VCA) in power supply networks. The RDSS scheme employs a fuzzy hyperrectangular composite neural network (FHRCNN) to carry out voltage risk identification (VRI). In the event that a threat to the security of the power supply network is detected, an evolutionary programming (EP)-based algorithm is triggered to determine the operational settings required to restore the power supply network to a secure condition. The effectiveness of the RDSS methodology is demonstrated through its application to the American Electric Power Provider System (AEP, 30-bus system) under various heavy load conditions and contingency scenarios. In general, the numerical results confirm the ability of the RDSS scheme to minimize the risk of voltage collapse in power supply networks. In other words, RDSS provides Power Provider Enterprises (PPEs) with a viable tool for performing on-line voltage risk assessment and power system security enhancement functions.

Open circuit voltage (OCV) of electrical devices is an issue in various fields, whose numerical evaluation needs careful treatment. The open-circuited structure is ill-conditioned because of the singular electric field at the corners, and the TEM component of the electric field has to be extracted before integrated to give the voltage in the direct method of obtaining the OCV. This paper introduces the indirect methods to calculate the OCV, the admittance matrix method and the Norton theorem method. Both methods are based on the short-circuited structure which is well-conditioned. The explicit expressions of the OCV are derived in terms of the admittance matrix elements in the admittance matrix method, and in terms of the short circuit current and the antenna impedance of the electrical device under consideration in the Norton theorem method. These two methods are equivalent in theory, but the admittance matrix method is suitable for the nearby transmitter cases while the Norton theorem method is suitable for the distant transmitter cases. Several examples are given to show the usefulness of the present theory.

PIN diodes for digital X-ray detection as a single photon counting sensor were fabricated on a floating-zone (FZ) n-type (111), high resistivity (5-10 kΩcm) silicon substrates (500 µm thickness). Its electrical properties such as the leakage current and the breakdown voltage were characterized. The size of pixels was 100 µm100 µm. The p+ guard-ring was formed around the active area to reduce the leakage current. After the p+ active area and guard-ring were fabricated by the ion-implantation, the extrinsic-gettering on the wafer backside was performed to reduce the leakage current by n+ ion-implantation. PECVD oxide was deposited as an IMD layer on front side and then, metal lines were formed on both sides of wafers. The leakage current of detectors was significantly reduced with a guard-ring when compared with that without a guard ring. The leakage current showed the strong dependency on the gap distance between the active area and the guard ring. It was possible to achieve the leakage current lower than 0.2 nA/cm2.

This paper reports the new gate and recess structure design of millimeter-wave, high power pHEMTs, which highly improves humidity resistance and reliability. By using tantalum nitride as the refractory gate metal and a silicon nitride layer prepared by a catalytic chemical vapor deposition technique for passivation of this transistor, strong moisture resistance was obtained without degradation of the device characteristics. Moreover, we have designed a stepped recess structure to increase the on-state breakdown voltage without degradation of the power density of the millimeter-wave pHEMT, according to the analysis based on the new nonlinear drain resistance model. Consequently, the developed pHEMT has shown strong humidity resistance with no degradation of the DC characteristics even after 1000 hours storage at 400 K and 85% humidity, and the high on-state breakdown voltage of over 30 V while keeping the high power density of 0.65 W/mm in the Ka band. In addition, the proposed nonlinear drain resistance model effectively explains this power performance.