An on-chip process, supply voltage, and temperature (PVT) compensation technique for low-voltage CMOS digital circuits was proposed. Because the degradation of circuit performance originates from the variation of the saturation current in transistors, we developed a compensation circuit consisting of a reference current that is independent of PVT variations. The circuit is operated so that the saturation current in digital circuits is equal to the reference current. The operations of the circuit were confirmed by SPICE simulation with a set of 0.35-µm standard CMOS parameters. Monte Carlo simulations showed that the proposed technique effectively improves circuit performance by 71%. The circuit is useful for on-chip compensation to mitigate the degradation of circuit performance with PVT variation in low-voltage digital circuits.

A low-voltage operational capability near 1 V along with low noise and distortion characteristics have been realized in a passive sigma-delta modulator. To achieve low-voltage operation, the dc voltage in signal paths in the switched-capacitor-filter section was set to be 0.2 V so that sufficient gate-to-source voltages were obtained for metal-oxide-semiconductor (MOS) switches in signal paths without using a gate-voltage boosting technique. In addition, the input switch that connects the input signal from the outside to the inside of an integrated circuit chip was replaced by a passive resistor to eliminate a floating switch, and gain coefficients in the feedback and input paths were modified so that the bias voltage of the digital-to-analog converter could be set to VDD and 0 V to easily activate MOS switches. As the signal swing becomes small under low-voltage operational circumstances, correlated double sampling was used to suppress the offset voltage and the 1/f noise that appeared at the input of a comparator. The modulator was fabricated using a standard CMOS 0.18-µm process, and the measured results show that the modulator realized 77 dB of dynamic range for 40 kHz of signal bandwidth with a 40 MHz sampling rate while dissipating 2 mW from a 1.1 V supply voltage.

In this paper, an efficient method is proposed to accurately analyze large-scale power/ground (P/G) networks, where inductive parasitics are modeled with the partial reluctance. The method is based on frequency-domain circuit analysis and the technique of vector fitting, and obtains the time-domain voltage response at given P/G nodes. The frequency-domain circuit equation including partial reluctances is derived, and then solved with the GMRES algorithm with rescaling, preconditioning and recycling techniques. With the merit of sparsified reluctance matrix and iterative solving techniques for the frequency-domain circuit equations, the proposed method is able to handle large-scale P/G networks with complete inductive modeling. Numerical results show that the proposed method is orders of magnitude faster than HSPICE, several times faster than INDUCTWISE, and capable of handling the inductive P/G structures with more than 100,000 wire segments.

We propose a dynamic voltage scaling algorithm to exploit the temporal locality called TLDVS (Temporal Locality DVS) that can achieve significant energy savings while simultaneously preserving timeliness guarantees made by real-time scheduling. Traditionally hard real-time scheduling algorithms assume that the actual computation requirement of tasks would be varied continuously from time to time, but most real-time tasks have a limited number of operational modes changing with temporal locality. Such temporal locality can be exploited for energy savings by scaling down the operating frequency and the supply voltage accordingly. The proposed algorithm does not assume task periodicity, and requires only previous execution time among a priori information on the task set to schedule. Simulation results show that TLDVS achieves up to 25% energy savings compared with OLDVS, and up to 42% over the non-DVS scheduling.

In this paper, a low-voltage, wide-common-mode-range and high-CMRR OTA is presented. The proposed OTA consists of two circuit blocks; one is the input stage and operates as a differential level shifter, and the other is a highly linear output stage. Furthermore, the OTA can be operated in both weak and strong inversion regions. The proposed OTA is evaluated through Star-HSPICE with 0.18 µm CMOS device parameters (LEVEL53). Simulation results demonstrate a CMRR of 158 dB, a common-mode-input-range of 65 mV to 720 mV and a current consumption of 1.2 µA when VDD=0.8 V.

A low-voltage quadrature up-conversion CMOS mixer for 5-GHz wireless communication applications is designed with a TSMC 0.18-µm process. The fold-switching technique is used to implement the low-voltage double balanced quadrature mixer. A miniature lumped-element microwave broadband rat-race hybrid and RLC shift network are used for the local oscillator and the intermediate frequency port design, respectively. The measured results demonstrate that the mixer can reach a high conversion gain, a low noise figure (NF), and a high linearity. The mixer exhibits improvement in noise, conversion gain, and image rejection. The mixer shows a conversion gain of 16 dB, a noise figure of 12.8 dB, an image rejection of 45 dB, while dissipating 15.5 mW for an operating voltage at 1 V.

An on-chip Charged Device Model (CDM) ESD protection method for RF ICs is proposed in a 0.13 µm RF process and evaluated by using very fast Transmission Line Pulse (vf-TLP) system. Key design parameters such as triggering voltage (Vt1) and the oxide breakdown voltage from the vf-TLP measurement are used to design input ESD protection circuits for a RF test chip. The characterization and the behavior of a Low Voltage Triggered Silicon Controlled Rectifier (SCR) which used for ESD protection clamp under vf-TLP measurements are also reported. The results measured by vf-TLP system showed that the triggering voltage decreased and the second breakdown current increased in comparison with the results measured by a standard 100 ns TLP system. From the HBM/ CDM testing, the RF test chip successfully met the requested RF ESD withstand level, HBM 1 kV, MM 100 V and CDM 500 V.

Design of the 30 nm FinFETs and Double Gate MOSFETs with the halo structure for suppressing the threshold voltage roll-off and improving the subthreshold swing at the same time is proposed for the first time. The performances of nano scale FinFETs and Double Gate MOSFETs with the halo structure are analyzed using a two-dimensional device simulator. The device characteristics, focusing especially on the threshold voltage and subthreshold slope, are investigated for the different gate length, body thickness, and halo impurity concentration. From the viewpoint of body potential control, it is made clear on how to design the halo structure to suppress the short channel effects and improve the subthreshold-slope. It is shown that by introducing the halo structure to FinFETs and Double Gate MOSFETs, nano-scale FinFETs and Double Gate MOSFETs achieve an improved S-factor and suppressed threshold voltage Vth roll-off simultaneously.

A new mixed-voltage I/O buffer for low-voltage low-latency operation is proposed in this paper. The proposed buffer adopts a novel delay-based timing-control scheme to efficiently avoid problems like gate-oxide stress and hot-carrier degradation. The proposed timing-control scheme also allows the buffer to have a lower latency for transmitting data by avoiding the use of timing-critical circuits like series-connected transmission gates (TGs) and triple-stacked transistors. The latency for receiving data at low supply voltage is also reduced by employing a variable stacked transistor gate-biasing scheme. Comparison results in an 80-nm CMOS process indicated that the proposed mixed-voltage I/O buffer improved up to 79.3% for receiving the external data and up to 23.8% for transmitting the internal data at a supply voltage of 1.2 V.

Multiple supply voltage (MSV) assignment is a highly effective means of reducing power consumption. Many existing algorithms perform very well for power reduction. However, they do not handle the area issue of level shifters. In some cases, although one gets a superior result to reduce the power consumption, but many extra level shifters are needed to add so that the circuit area will be over the specification. In this paper, we present an effective integer linear programming (ILP)-based MSV assignment approach to solve two problems with different objectives. For the objective of power reduction under timing constraint, compared with GECVS algorithm, the power consumption obtained by our proposed approach can be further reduced 0 to 5.46% and the number of level shifters is improved 16.31% in average. For the objective of power reduction under constraints of both timing and area of level shifters, the average improvement of power consumption obtained by our algorithm is still better than GECVS while reducing the number of level shifters by 22.92% in average. In addition, given a constraint of total power consumption, our algorithm will generate a design having minimum circuit delay. Experimental results show that the proposed ILP-based MSV assignment algorithm solves different problems flexibly.

The minimum operating voltage, Vmin, of nanoscale CMOS LSIs is investigated to breach the 1-V wall that we are facing in the 65-nm device generation, and open the door to the below 0.5-V era. A new method using speed variation is proposed to evaluate Vmin. It shows that Vmin is very sensitive to the lowest necessary threshold voltage, Vt0, of MOSFETs and to threshold-voltage variations, Δ Vt, which become more significant with device scaling. There is thus a need for low-Vt0 circuits and ΔVt-immune MOSFETs to reduce Vmin. For memory-rich LSIs, the SRAM block is particularly problematic because it has the highest Vmin. Various techniques are thus proposed to reduce the Vmin: using RAM repair, shortening the data line, up-sizing, and using more relaxed MOSFET scaling. To effectively reduce Vmin of other circuit blocks, dual-Vt0 and dual-VDD circuits using gate-source reverse biasing, temporary activation, and series connection of another small low-Vt0 MOSFET are proposed. They are dynamic logic circuits enabling the power-delay product of the conventional static CMOS inverter to be reduced to 0.09 at a 0.2-V supply, and a DRAM dynamic sense amplifier and power switches operable at below 0.5 V. In addition, a fully-depleted structure (FD-SOI) and fin-type structure (FinFET) for ΔVt-immune MOSFETs are discussed in terms of their low-voltage potential and challenges. As a result, the height up-scalable FinFETs turns out to be quite effective to reduce Vmin to less than 0.5 V, if combined with the low-Vt0 circuits. For mixed-signal LSIs, investigation of low-voltage potential of analog circuits, especially for comparators and operational amplifiers, reveals that simple inverter op-amps, in which the low gain and nonlinearity are compensated for by digitally assisted analog designs, are crucial to 0.5-V operations. Finally, it is emphasized that the development of relevant devices and fabrication processes is the key to the achievement of 0.5-V nanoscale LSIs.

A time-slicing ring oscillator (TSRO) which captures time-dependent delay degradation due to periodic transient voltage drop on a power supply network is proposed. An impact of the supply voltage fluctuations, including voltage drop and overshoot, on logic circuit delay is evaluated as a change of oscillation frequency. The TSRO is designed using standard logic cells so that it can be placed almost anywhere in a digital circuit wherein supply voltage fluctuation is concerned. We also propose a new procedure for reconstructing supply voltage waveform. The procedure enables us to accurately monitor time-dependent, effective supply voltages. The -1 dB bandwidth of the TSRO is simulated to be 15.7 GHz, and measured time resolution is 131 ps. Measurement results of a test chip using 90-nm standard CMOS process successfully proved the feasibility of both delay degradation and effective supply voltage fluctuation measurements. Measurement of spatial voltage drop fluctuation is achieved.

This paper presents a Time Difference Amplifier (TDA) that amplifies the input time difference into the output time difference. Cross coupled chains of variable delay cells with the same number of stages are applicable for TDA, and the gain is adjusted via the closed-loop control. The TDA was fabricated using 65 nm CMOS and the measurement results show that the time difference gain is 4.78 at a nominal power supply while the designed gain is 4.0. The gain is stable enough to be less than 1.4% gain shift under 10% power supply voltage fluctuation.

Dynamic Voltage Scaling (DVS) is a well-known low-power design technique, which adjusts the clock speed and supply voltage dynamically to reduce the energy consumption of real-time systems. Previous studies considered the probabilistic distribution of tasks' workloads to assist DVS in task scheduling. These studies use probability information for intra-task frequency scheduling but do not sufficiently explore the opportunities for the system workload to save more energy. This paper presents a novel DVS algorithm for periodic real-time tasks based on the analysis of the system workload to reduce its power consumption. This algorithm takes full advantage of the probabilistic distribution characteristics of the system workload under priority-driven scheduling such as Earliest-Deadline-First (EDF). Experimental results show that the proposed algorithm reduces processor idle time and spends more busy time in lower-power speeds. The measurement indicates that compared to the relative DVS algorithms, this algorithm saves energy by at least 30% while delivering statistical performance guarantees.

In order to explore the feasibility of large-scale subthreshold logic circuits and to clarify the lower limit of supply voltage (VDD) for logic circuits, the dependence of the minimum operating voltage (VDD min ) of CMOS logic gates on the number of stages, gate types and gate width is systematically measured with 90 nm CMOS ring oscillators (RO's). The measured average VDD min of inverter RO's increased from 90 mV to 343 mV when the number of RO stages increased from 11 to 1 Mega, which indicates the difficulty of VDD scaling in large-scale subthreshold logic circuits. The dependence of VDD min on the number of stages is calculated using the subthreshold current model with random threshold voltage (VTH) variations and compared with the measured results, and the tendency of the measurement is confirmed. The effect of adaptive body bias control to compensate purely random VTH variation is also investigated. Such compensation would require impractical inverter-by-inverter adaptive body bias control.

A new low voltage operation of high voltage switching technique, which is capable of reducing leakage current by an order of three compared to conventional circuits, has been developed for sub-1.8 V low voltage mobile NAND flash memory. In addition, by using the proposed high voltage switch, chip size scaling can be realized due to reduced a minimum required space between the N-wells of selected and unselected blocks for isolation. The proposed scheme is essential to achieve low power operation NAND Flash memory, especially for mobile electronics.

This paper proposes a voltage-to-current converter with nested feedback loop configuration to achieve high loop gain without reducing the bandwidth. Simulation results using 0.18-µm CMOS process parameters show that the proposed circuit has a good linearity performance. The simulated bandwidth is 350 MHz. The THD improvement of the proposed circuit is more than 60 dB compared to the one of a common gate circuit under a same total current consumption of 10.4 mA.

In this paper, new structure of Voltage-Mode MAX-MIN circuit are presented for nonlinear systems, fuzzy applications, neural network and etc. A differential pair with improved cascode current mirror is used to choose the desired input. The advantages of the proposed structure are high operating frequency, high precision, low power consumption, low area and simple expansion for multiple inputs by adding only three transistors for each extra input. The proposed circuit which is simulated by HSPICE in 0.35 µm CMOS process shows the total power consumption of 85 µW in 5 MHz operating frequency from a single 3.3-V supply. Also, the total area of the proposed circuit is about 420 µm2 for two input voltages, and would be negligibly increased for each extra input.

This paper presents a wide tuning range VCO with an automatic frequency, gain, and two-step amplitude calibration loop for Digital TV (DTV) tuner applications. To cover the wide tuning range, the fully digital automatic frequency calibration (AFC) loop is used. In addition to the AFC loop, a two-step negative-Gm tuning loop is proposed to provide the optimum negative-Gm to the LC tank in a wide frequency range with a fine resolution. In the coarse negative-Gm tuning loop, the number of active negative-Gm cells is selected digitally based on the target frequency. In the fine negative-Gm tuning loop, the negative-Gm is tuned finely with the bias voltage of the VCO. Also, the digital VCO gain calibration scheme is proposed to compensate for the gain variation in a wide tuning range. The VCO tuning range is 2.6 GHz, from 1.7 GHz to 4.3 GHz, and the power consumption is 2 mA to 4 mA from a 1.8 V supply. The measured VCO phase noise is -120 dBc/Hz at 1 MHz offset.

Low Power Design has become a significant requirement when the CMOS technology entered the nanometer era. Multiple-Supply Voltage (MSV) is a popular and effective method for both dynamic and static power reduction while maintaining performance. Level shifters may cause area and Interconnect Length Overhead (ILO), and should be considered at both floorplanning and post-floorplanning stages. In this paper, we propose a two phases algorithm framework, called VLSAF, to solve voltage and level shifter assignment problem. At floorplanning phase, we use a convex cost network flow algorithm to assign voltage and a minimum cost flow algorithm to handle level-shifter assignment. At post-floorplanning phase, a heuristic method is adopted to redistribute white spaces and calculate the positions and shapes of level shifters. The experimental results show VLSAF is effective.