We propose a design methodology of a low-voltage CMOS low-noise amplifier (LNA) consisting of a common-source and a common-gate stages. We first derive equations of power gain, noise figure (NF) and input third-order intercept point (IIP3) of the two-stage LNA. A design methodology of the LNA is presented by using graphs based on analytical equations. A 1-V 5.4-GHz LNA was implemented in 0.15-µm fully-depleted silicon-on-insulator (FD-SOI) CMOS technology. Measurement results show a power gain of 23 dB, NF of 1.7 dB and IIP3 of -6.1 dBm with a power consumption of 8.3 mW. These measured results are consistent with calculated results, which ensures the validity of the derived equations and the proposed design methodology.

This paper describes a 1.2-V, 12-bit, 200-MSample/s current-steering CMOS digital-to-analog (D/A) converter for wireless-communication terminals. To our knowledge, the supply voltage of this converter is the lowest for high-speed applications. To overcome increasing device mismatch in low-voltage operation, we propose an H-shaped, 3-dimensional structure for reducing influence of voltage drops (IR drops) along power supplies. This technique relaxes mismatch requirements and allows use of small devices with small parasitics. By using this technique, a low-voltage, high-speed D/A converter was realized. The converter was implemented in a 90-nm CMOS technology. The modulator achieves the intrinsic accuracy of 12 bits and a spurious-free dynamic range (SFDR) above 55 dB over a 100-MHz bandwidth.

A new current reused quadrature voltage controlled oscillator (QVCO) is proposed and implemented using UMC 0.18 µm CMOS 1P6M process. The proposed circuit topology is made up two low voltage LC-tank VCOs, where the QVCO is obtained using the transformer coupling and current reuse technique. At 1.8 V supply voltage, the phase noise of the VCO is -117.13 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 2.18 GHz, the core power consumption is 4.14 mW, the total power consumption is 6.48 mW and tuning range is about 160 MHz.

This paper proposes a synthesis method of all low-voltage CMOS instantaneous-companding log domain integrators. The method is based on the exhaustive search of all low-voltage CMOS instantaneous-companding log domain integrators. All the integrators are derived from a general block diagram. A function of each block can be realized by any of a family of circuits and elemental circuits chosen from such families are combined to build an integrator. It is clarified that each family contains a few circuit topologies. All topologies of integrators including new ones are obtained from combinational procedure. Comparing characteristics of all generated integrators, ones satisfying required performances are found out.

The voltage island style has been widely accepted as an effective way to design low power high performance chips. This paper proposes an automated voltage island generation flow in standard cell based designs. Two important objectives in voltage island designs are addressed in this flow: 1) reducing power dissipation under given performance constraints; 2) reducing implementation overheads, mainly layout overheads caused by cell clustering to form islands. The first objective is handled with timing and power driven netweighting and timing analysis in voltage assignment. For the second objective, we propose layout aware voltage assignment, i.e., voltage assignment during placement. We iteratively perform the following to adjustments: adjustment on voltage assignment to facilitate voltage island generation, and adjustment on cell locations to cluster cells in voltage islands. These iterations lead to a flow featured with tightly integrated voltage assignment and cell placement. Experimental results have demonstrated the advantages of our approach.

A novel CMOS level converter with balanced rise and fall delays for arbitrary voltage conversion is presented. The proposed level converter was designed using a 90 nm CMOS process technology. The comparison result indicates that the maximum difference between the rise and fall delays of the proposed level converter was reduced by up to 92% compared to the conventional CMOS level converters.

Viable techniques such as dynamic voltage scaling (DVS) provide a new design technique to balance system performance and energy saving. In this paper, we extend previous works on task assignment problems for a set of linear-pipeline tasks over a set of processors. Different from previous works, we revisit the problems with two additional system factors: deadline and energy-consumption, which are key factors in real-time and power-aware computation. We propose an O(nm2) time complexity algorithm to determine optimal task-assignment and speed-setting schemes leading to minimal energy consumption, for a given set of m real-time tasks running on n identical processors (with or without DVS supports). The same result can be extended to a restricted form of heterogeneous processor model. Meanwhile, we show that on homogeneous processor model more efficient algorithms can be applied and result in time complexity of O(m2) when m ≤ n. For completeness, we also discuss cases without contiguity constraints. We show under such cases the problems become at least as hard as NP-hard.

We propose an elastic pipeline that can apply dynamic voltage scaling (DVS) to hardwired logic circuits. In order to demonstrate its feasibility, a hardwired H.264/AVC HDTV decoder is designed as a real-time application. An entropy decoding process is divided into context-based adaptive binary arithmetic coding (CABAC) and syntax element decoding (SED), which has advantages of smoothing workload for CABAC and keeping efficiency of the elastic pipeline. An operating frequency and supply voltage are dynamically modulated every slot depending on workload of H.264 decoding to minimize power. We optimize the number of slots per frame to enhance power reduction. The proposed decoder achieves a power reduction of 50% in a 90-nm process technology, compared to the conventional clock-gating scheme.

This paper presents the design, fabrication and characterization of a low actuation voltage capacitive shunt RF-MEMS switch for microwave and millimeter-wave applications based on a corrugated electrostatic actuated bridge suspended over a concave structure of coplanar waveguide (CPW), with sputtered nickel as the structural material for the bridge and gold for CPW line, fabricated on high-resistivity silicon (HRS) substrate using IC compatible processes for modular integration in a communication devices. The residual stress is very low because having both ends corrugated structure of the bridge in concave structure. The residual stress is calculated about 3-15 MPa in corrugated bridge and 30 MPa in flat bridge. The corrugated bridge of the concave structure requires lower actuation voltages 20-80 V than 50-100 V of the flat bridge of the planar structure in 0.3 to 1.0 µm thick Ni capacitive shunt RF-MEMS switch, in insertion loss 1.0 dB, return loss 12 dB, power loss 10 dB and isolation 28 dB from 0.5 up to 40 GHz. The residual stress of the bridge material and structure is critical to lower the actuation voltage.

A linear CMOS transconductor is presented. PMOS transistors are employed in the resistor-replacement and voltage-level shifting to avoid the body effect. To annihilate the non-linear voltage terms, the substrate-bias effect of MOS transistors is treated more accurately in our design. Consequently, the non-linearity of the large-signal transconductance is reduced. The fabricated circuit occupies an area of 245 µm176 µm ( ≈approx 0.043 mm2) and dissipates 0.87 mW from a 3.3 V supply. For an input of 1 Vp-p, the measured output total harmonic distortion is less than 1.2%. The transconductance varies by less than 0.5% in the input range.

To give comprehensive and consecutive understanding about load line regulation in the previous companion paper [1], more generalized expansion and theoretical derivation will be proposed in this paper. The paper provides an alternative current control approach to control the bias voltage compensation for full-color LED display based on the load-line approach. Modeling and formulation of the driver circuit system will be discussed in detail. Bias voltage compensation based on three load-lines regulation will keep the operating point fixed for the three color cells. Many properties can be observed based on the proposed model. Parasite effect such as the stray resistor and the stray capacitor will be considered in this paper. The associated standard RGB color testing for color cells and white color testing will be illustrated to verify the proposed compensation for the display driver circuit. The objectives of the luminance uniformity and the gray scale control can be achieved by using circuit approach. It is believed that this paper will be helpful to the driver circuit technology for the full-color LED display.

In this paper, we report a manufacturable InP DHBT technology, suitable for medium scale mixed-signal and monolithic microwave integrated circuits. The InGaAs/InP DHBTs were grown by MBE and fabricated using conventional process techniques. Devices with an emitter junction area of 4.8 µm2 exhibited peak cutoff frequency (fT) and maximum oscillation frequency (fMAX) values of 265 and 305 GHz, respectively, and a breakdown voltage (BVCEo) of over 5 V. Using this technology, a set of mixed-signal IC building blocks for ≥ 80 Gbit/s fibre optical links, including distributed amplifiers (DA), voltage controlled oscillators (VCO), and multiplexers (MUX), have been successfully fabricated and operated at 80 Gbit/s and beyond.

Based on fluoride-based plasma treatment of the gate region in AlGaN/GaN HEMTs and post-gate rapid thermal annealing (RTA), enhancement mode (E-mode) AlGaN/GaN HEMTs with low on-resistance and low knee-voltage were fabricated. The fabricated E-mode AlGaN/GaN HEMT with 1 µm-long gate exhibits a threshold voltage of 0.9 V, a knee-voltage of 2.2 V, a maximum drain current density of 310 mA/mm, a peak gm of 148 mS/mm, a current gain cutoff frequency fT of 10.1 GHz and a maximum oscillation frequency fmax of 34.3 GHz. In addition, the fluoride-based plasma treatment was also found to be effective in lowering the gate leakage current, in both forward and reverse bias. Two orders of magnitude reducation in gate leakage current was observed in the fabricated E-mode HEMTs compared to the conventional D-mode HEMTs without fluoride-based plasma treatment.

This investigation of the temperature and illumination effects on the AlGaN/GaN HFET threshold voltage shows that it shifts about -1 V under incandescent lamp or blue LED illumination, while almost no shift takes place under red LED illumination. The temperature coefficient for the threshold voltage shift is +3.44 mV/deg under the illuminations and +0.28 mV/deg in darkness. The threshold voltage variation can be attributed to a virtual back-gate effect caused by light-generated buffer layer potential variations. The expressions for the potential variation are derived using Shockley-Read-Hall (SRH) statistics and the Maxwell-Boltzmann distribution for the carriers and deep traps in the buffer layer. The expressions indicate that large photoresponses will occur when the electron concentration in the buffer layer is extremely small, that is, highly resistive. In semi-insulating substrates, the substrate potential varies so as to keep the trap occupation function constant. The sign and the magnitude of the threshold voltage variation are explained by the shift of the pinning energy calculated from the Fermi-Dirac distribution function.

Phase pure cubic (c-) GaN/AlGaN heterostructures on 3C-SiC free standing (001) substrates have successfully been developed. Almost complete (100%) phase pure c-GaN films are achieved with 2-nm surface roughness on 3C-SiC substrate and stoichiometric growth conditions. The polarization effect in c-GaN/AlGaN has been evaluated, based on measuring the transition energy of GaN/AlGaN quantum wells (QWs). It is demonstrated that the polarization electric fields are negligible small in c-GaN/AlGaN/3C-SiC compared with those of hexagonal (h-)GaN/AlGaN, 710 kV/cm for Al content x of 0.15, and 1.4 MV/cm for x of 0.25. A sheet carrier concentration of c-GaN/AlGaN heterojunction interface is estimated to 1.61012 cm-2, one order of magnitude smaller than that of h-GaN/AlGaN. The band diagrams of c-GaN/AlGaN HEMTs have been simulated to demonstrate the normally-off mode operation. The blocking voltage capability of GaN films was demonstrated with C-V measurement of Schottky diode test vehicle, and extrapolated higher than 600 V in c-GaN films at a doping level below 51015 cm-3, to show the possibility for high power electronics applications.

Experimental result and theoretical analysis are reported for bias-voltage dependence of oscillation frequency in resonant tunneling diodes (RTDs) integrated with slot antennas. Frequency change of 18 GHz is obtained experimentally for a device with the central oscillation frequency of 470 GHz. The observed frequency change is attributed to the bias-voltage dependence of the transit time of electrons across the RTD layers, which results in a voltage-dependent capacitance added to RTD. Theoretical analysis taking into account this transit time is in reasonable agreement with the observed results. Voltage-controlled RTD oscillators in the terahertz range are expected from the theoretical results. A structure suitable for large frequency change is also discussed briefly.

The operation of analog circuits from ultra low supply voltages becomes necessary due to semiconductor technology scaling. Yet traditional design techniques cannot be used. In this paper, we review techniques that allow analog circuits to operate with supply voltages as low as 0.5 V. Biasing considerations are given, and robust bias circuits are discussed. For frequency-tunable circuits, a low-voltage MOS varactor tuning technique is presented. The techniques discussed are applied to two different OTA topologies, as well as to an automatically tuned, fifth-order active RC filter. This material is largely based on the work of the authors as described in [1]-[5].

A method using an averaging technique for the analysis and evaluation of real quasi-resonant converters (QRC's) is proposed in this paper. To reduce the great difference between the real characteristics and those of ideal circuits, a modeling technique is developed by considering the effect of parasitic power losses. Then, using the averaging approach reasonably simplifies the process of solving equations to obtain the steady-state solutions of state variables. Also, an updating algorithm is constructed to take all the power losses such as core losses, which are often absent in the conventional analysis, into account to improve the accuracy of the steady-state solutions. By these efforts, the evaluation of characteristics for QRC's is realized.

This letter presents two high-performance level-converting flip-flops (LCFF) for multi-VDD systems, indirect precharging flip-flop (IPFF) and multi-supply complementary pass-transistor flip-flop (MCPFF). Employing a simple precharging scheme, IPFF provides high operating speed. MCPFF, on the other hand, provides low power operations by implementing the edge-triggering function with complementary pass transistors. Performance comparison indicates that IPFF operates at the highest speed and MCPFF consumes the lowest power among the seven LCFFs under evaluation.

A low-noise CMOS amplifier operating at a low supply voltage is developed using the two noise reduction techniques of autozeroing and chopper stabilization. The proposed amplifier utilizes a feedback with virtual grounded input-switches and a multiple-output switched op-amp. The low-noise amplifier fabricated in a 0.18-µm CMOS technology achieved 50-nV/Hz input noise at 1-MHz chopping and 0.5-mW power consumption at 1-V supply voltage.