This paper is focused on discussing a low-voltage system for lightning, and in particular the testing equipment of surge arresters. Only by demonstrating the performance and applicability of arresters can we seek the most feasible and economic low-voltage solutions. After performing repeated experiments with the same testing samples, using different testing equipment, we compare the different test results in order to select the most suitable and applicable testing equipment. In addition, the basis of a surge current parameter design theory is confirmed and verified through the test results using a simple and compact Impulse Current Generator to test a wide range of samples. By performing the actual analyzes and experiments, we can understand deeply how R, L, and C affect surge current, current wave, and current wave time. The ideal testing equipment standards have been set as follows: (1) Test Voltage up to 20 kV; (2) Expand current range from 1.5 kA to 46.5 kA, with resolution 1.5 kA; and (3) Simple operational procedures.

This paper presents a high-efficiency boost converter with voltage clamp function. It clarifies how to design the inductance of the coupled inductor used in the converter, and derives characteristic equations that associate the fluctuation in the input voltage with the output ripple current. For this converter, a theoretical analysis, simulation and experimentation (prototype output: 98 V, 13 A) are performed. As a result, the converter is achieved high efficiency (Maximum efficiency: 98.1%) in the rated output condition, indicating that the voltage stress on the switching power semiconductors can be mitigated by using the voltage clamp function. And it is verified that the snubber circuit can be eliminated in the switching power semiconductors. In addition, the theoretical output ripple current characteristics are corresponded well with simulation and experimental results, and the validity of the design method is proved.

We investigate a design strategy for subthreshold circuits focusing on energy-consumption minimization and yield maximization under process variations. The design strategy is based on the following findings related to the operation of low-power CMOS circuits: (1) The minimum operation voltage (VDDmin) of a circuit is dominated by flip-flops (FFs), and VDDmin of an FF can be improved by upsizing a few key transistors, (2) VDDmin of an FF is stochastically modeled by a log-normal distribution, (3) VDDmin of a large circuit can be efficiently estimated by using the above model, which eliminates extensive Monte Carlo simulations, and (4) improving VDDmin may substantially contribute to decreasing energy consumption. The effectiveness of the proposed design strategy has been verified through circuit simulations on various circuits, which clearly show the design tradeoff between voltage scaling and transistor sizing.

Dual-vdd has been proposed to optimize the power of circuits without violating the performance. In this paper, different from traditional methods which focus on making full use of slacks of non-critical gates, an efficient min-cut based voltage assignment algorithm concentrating on critical gates is proposed. And then this algorithm is integrated into a searching engine to auto-select rational voltages for dual-vdd system. Experimental results show that our search engine can always achieve good pair of dual-vdd, and our min-cut based algorithm outperformed previous works for voltage assignment both on power consumption and runtime.

In LDMOS devices for high-voltage applications, there appears a notable fingerprint of current-voltage characteristics known as soft breakdown. Its mechanism is analyzed and modeled on LDMOS devices where a high resistive drift region exists. This analysis has revealed that the softness of breakdown, known as the expansion effect, withholding a run-away of current, is contributed by the flux of holes underneath the gate-overlap region originated by impact-ionization. The mechanism of the expansion effect is modeled and implemented into the compact model HiSIM_HV for circuit simulation. A good agreement between simulated characteristics and 2D-device simulation results is verified.

This paper introduces novel high-speed and low-power boosted level converters for use in dual-supply systems. The proposed level converters adopt a voltage boosting at the gate of pull-down transistors to improve driving speed and reduce contention problem. Comparison results in a 0.13-µm CMOS process indicated that the proposed level converters provided up to 70% delay reduction with up to 57% power-delay product (PDP) reduction as compared to conventional level converters.

A 60 GHz direct conversion transceiver which employs amplitude/phase imbalance cancellation technique is newly proposed. By using the proposed technique, the receive path of the transceiver achieves less than 0.2 dB of amplitude error and less than 3 of phase error at 60 GHz bands over a 10 GHz bandwidth, which relaxes the design accuracy required for baluns used in the transceiver. It also employs a simple and fast calibration algorithm to adjust the locking range of the divide-by-3 injection locked divider in the phase locked loop. Fabricated in 90 nm CMOS technology, the transceiver achieves a low power consumption of 230 mW in transmit mode and 173 mW in receive mode. The output spectrum of 1.76 Gsps π/2-BPSK/QPSK modulation shows the excellent distortion and spurious suppression that meet the IEEE802.11ad draft standard.

An on-chip soft-start circuit based on a switched-capacitor for DC-DC switching regulator is presented. A ramp-voltage, which is generated by a switched-capacitor, is used to make pulse width slowly increase from zero, in order to eliminate the inrush current and the overshoot voltage during start-up. The post simulation results show that the regulator soft starts well with the proposed soft-start circuit.

The circuit switching device by the electrical contact needs the high reliability and long lifetime. The very important factor for the high reliability, long lifetime and electromagnetic noise of the electrical contact is to suppress the duration and electromagnetic noise of arc discharge. Usually, the suppression of arc duration method is applying the external magnetic field. But, this method was not able to suppress the metallic arc duration and increased the voltage fluctuation at arc duration. Therefore, the new method for suppressing the duration and noise for electrical contact is expected. In this paper, a new method for suppressing duration and EM noise of arc discharge by applying housing pressure is proposed. To investigate the availability of proposed method, the measurement and some considerations on arc duration, voltage-fluctuation and current noise up to GHz frequency band generated by breaking contact in the applied pressure relay housing are reported. Firstly, voltage waveform and duration of the arc are measured. The effects of the pressure in the relay housing on the duration of the metallic and gaseous phase arcs are discussed. Secondary, voltage fluctuation, the spectrogram of contact voltage and current noise up to GHz frequency band are discussed. In the results, the proposed method with applying pressure makes shorter both durations of metallic and gaseous phases. The shorter duration of metallic phase is an advantage of the proposed method beyond the applying external magnetic field. As the housing pressure is increase, the voltage fluctuation and current noise becomes smalls. The proposed method can suppress the voltage fluctuation as well as arc duration. Consequently, the proposed method is on of the good solution to suppress the duration and electromagnetic noise of the arc discharge from electrical contact and result of this study indicates the basic considerations necessary to ensure good lifetime and EMC designs for electrical contacts.

This paper investigates the effects of n-type doping in the emitter-base heterojunction vicinity on the DC and high-frequency characteristics of InP/InGaAs heterojunction bipolar transistors (HBTs). The n-type doping is shown to be very effective for enhancing the tunneling-injection current from the emitter and thus for reducing the collector-current turn-on voltage. However, it is also revealed that an unnecessary increase in the doping level only degrades the current gain, especially in the low-current region. A higher doping level also increases the emitter junction capacitance. The optimized HBT structures with a 0.5-µm-wide emitter exhibit turn-on voltage as low as 0.78 V and current gain of around 80 at JC = 1 mA/µm2. They also provide a current-gain cutoff frequency, ft, of 280 GHz and a maximum oscillation frequency, fmax, of 385 GHz at VCE = 1 V and JC = 3 mA/µm2. These results indicate that the proposed HBTs are very useful for high-speed and low-power IC applications.

Although the Tunnel Field-Effect Transistor (TFET) is a promising device for ultra-low power CMOS technology due to the ability to reduce power supply voltage and very small off-current, there have been few reports on the control of VT for TFETs. Unfortunately, the TFET needs a different technique to adjust VT than the MOSFET by channel doping because most of TFETs are fabricated on SOI substrates. In this paper, we propose a technique to control VT of the TFET by putting an additional VT-control doping region (VDR) between source and channel. We examine how much VT is changed by doping concentration of VDR. The change of doping concentration modulates VT because it changes the semiconductor work function difference, ψs,channel-ψs,source, at off-state. Also, the effect of the size of VDR is investigated. The region can be confined to the silicon surface because most of tunneling occurs at the surface. At the same time, we study the optimum width of this region while considering the mobility degradation by doping. Finally, the effect of the SOI thickness on the VDR adjusted VT of TFET is also investigated.

Effects of conductive defects on unipolar resistive random access memory (RRAM) are investigated in order to reduce the operation current for high density and low power RRAM applications. It is clarified that forming voltage decreases with increasing charged conductive defects which are a source of conductive filament (CF) path and with decreasing cell thickness. Random circuit breaker (RCB) network simulation model which is a dynamic percolation simulation model is used to elucidate these effects. From this simulation results, the optimal cell thickness with sufficient conductive defect shows improved resistive switching characteristics such as low forming voltage, small set voltage distribution and low reset current. From the deep understanding of relationship between conductive defect in various cell thickness and other resistive switching parameters, RRAM with low forming voltage and reset current can be obtained and it will be one of the most promising next generation nonvolatile memories.

In order to improve the address discharge characteristics, we propose the modified selective reset waveform utilizing the address-bias voltage (Va-bias) during the ramp-up period. It is revealed that the proper Va-bias makes the weak discharge between the address and scan electrodes which plays a role in sufficiently removing the wall charge, thereby contributing to minimizing the wall-voltage variation during the address-period. As a result of adopting the Va-bias in the conventional selective reset driving waveform, it was found that the address discharge delay time can be shortened by approximately 40 ns and the address period of each subfield can be significantly reduced by about 43 µs.

Thin-film 2-arm Archimedean spiral antenna coupled with a bismuth (Bi) microbolometer was fabricated on a fused quartz substrate backed by cupper (Cu) plate reflector. Antenna patterns of the device agreed with the theoretical patterns derived from the imaging force model at 100 GHz band. The detected voltages of the antenna exhibited a periodic variation with changing the thickness of the substrate. The maximum and minimum detected voltages were obtained when the substrate thickness was odd and even integer multiples of a quarter of the wavelength in the substrate, respectively. Furthermore, the detected voltages were almost constant within the change of 3 dB ranging from 76.9 to 106.8 GHz. The wide band characteristic of the antenna was obtained.

This paper proposes a new biquad structure based on a flipped voltage follower (FVF) for low-power and wide-bandwidth (BW) low pass filter. The proposed biquad structure consists of an FVF and a source follower (SF) for complex pole pair generation and zero cancellation. The presented design provides good linearity at low power consumption, owing to the voltage follower structures. A power/BW ratio (PBWR) is suggested as a performance metric to compare power efficiency to bandwidth, and the proposed biquad structure shows excellent PBWR, especially for low quality factor (Q) design. As a prototype, a fourth order Bessel filter was fabricated in 0.18 µm CMOS technology. The measured BW, power consumption, IIP3, and FoM are 120 MHz, 180 µW, 15 dBm, and 0.34 fJ, respectively.

This paper demonstrates a FinFET operational amplifier (opamp), which is suitable to be integrated with digital circuits in a scaled low-standby-power (LSTP) technology and operates at extremely low voltage. The opamp is consisting of an adaptive threshold-voltage (Vt) differential pair and a low-voltage source follower using independent-double-gate- (IDG-) FinFETs. These two components enable the opamp to extend the common-mode voltage range (CMR) below the nominal Vt even if the supply voltage is less than 1.0 V. The opamp was implemented by our FinFET technology co-integrating common-DG- (CDG-) and IDG-FinFETs. More than 40-dB DC gain and 1-MHz gain-bandwidth product in the 500-mV-wide input CMR at the supply voltage of 0.7 V was estimated with SPICE simulation. The fabricated chip successfully demonstrated the 0.7-V operation with the 480-mV-wide CMR, even though the nominal Vt was 400 mV.

A small-sized leakage-controlled gated sense amplifier (SA) and relevant circuits are proposed for 0.5-V multi-gigabit DRAM arrays. The proposed SA consists of a high-VT PMOS amplifier and a low-VT NMOS amplifier which is composed of high-VT NMOSs and a low-VT cross-coupled NMOS, and achieves 46% area reduction compared to a conventional SA with a low-VT CMOS preamplifier. Separation of the proposed SA and a data-line pair achieves a sensing time of 6 ns and a writing time of 0.6 ns. Momentarily overdriving the PMOS amplifier achieves a restoring time of 13 ns. The gate level control of the high-VT NMOSs and the gate level compensation circuit for PVT variations reduce the leakage current of the proposed SA to 2% of that without the control, and its effectiveness was confirmed using a 50-nm test chip.

By using a quadratic compensation slope, a CMOS current-mode buck DC-DC converter with constant frequency characteristics over wide input and output voltage ranges has been developed. The use of a quadratic slope instead of a conventional linear slope makes both the damping factor in the transfer function and the frequency bandwidth of the current feedback loop independent of the converter's output voltage settings. When the coefficient of the quadratic slope is chosen to be dependent on the input voltage settings, the damping factor in the transfer function and the frequency bandwidth of the current feedback loop both become independent of the input voltage settings. Thus, both the input and output voltage dependences in the current feedback loop are eliminated, the frequency characteristics become constant, and the frequency bandwidth is maximized. To verify the effectiveness of a quadratic compensation slope with a coefficient that is dependent on the input voltage in a buck DC-DC converter, we fabricated a test chip using a 0.18 µm high-voltage CMOS process. The evaluation results show that the frequency characteristics of both the total feedback loop and the current feedback loop are constant even when the input and output voltages are changed from 2.5 V to 7 V and from 0.5 V to 5.6 V, respectively, using a 3 MHz clock.

A gated sense amplifier (GSA) consisting of a low-Vt gated preamplifier (LGA) and a high-Vt sense amplifier (SA) is proposed. The gating scheme of the LGA enables quick amplification of an initial cell signal voltage (vS0) because of its low Vt and prevents the cell signal from degrading due to interference noise between data lines. As for a conventional sense amplifier (CSA), this new type of noise causes sensing error, and the noise-generation mechanism was clarified for the first time by analysis of vS0. The high-Vt SA holds the amplified signal and keeps subthreshold current low. Moreover, the gating scheme of the low-Vt MOSFETs in the LGA drives the I/O line quickly. The GSA thus simultaneously achieves fast sensing, low-leakage data holding, and fast I/O driving, even for sub-1-V mid-point sensing. The GSA is promising for future sub-1-V gigabit dynamic random-access memory (DRAM) because of reduced variations in the threshold voltage of MOSFETs; thus, the offset voltage of the LGA is reduced. The effectiveness of the GSA was verified with a 70-nm 512-Mbit DRAM chip. It demonstrated row access time (tRCD) of 16.4 ns and read access (tAA) of 14.3 ns at array voltage of 0.9 V.

This paper presents analysis and design of a new ultra-low voltage analog front end (AFE) dedicated to strain sensor applications. The AFE, designed in 0.18 µm CMOS process, features a chopper-stabilized instrumentation amplifier (IA), a balanced active MOSFET-C 2nd order low pass filter (LPF), a clock generator and a voltage booster which operate at supply voltage (Vdd) of 0.6 V. The designed IA achieves 30 dB of closed-loop gain, 101 dB of common-mode rejection ratio (CMRR) at 50 Hz, 80 dB of power-supply rejection ratio (PSRR) at 50 Hz, thermal noise floor of 53.4 nV/, current consumption of 14 µA, and noise efficiency factor (NEF) of 9.7. The high CMRR and rail-to-rail output swing capability is attributed to a new low voltage realization of the active-bootstrapped technique using a pseudo-differential gain-boosting operational transconductance amplifier (OTA) and proposed current-driven bulk (CDB) biasing technique. An output capacitor-less low-dropout regulator (LDO), with a new fast start-up LPF technique, is used to regulate this 0.6 V supply from a 0.8–1.0 V energy harvesting power source. It achieves power supply rejection (PSR) of 42 dB at frequency of 1 MHz. A cascode compensated pseudo differential amplifier is used as the filter's building block for low power design. The filter's single-ended-to-balanced converter is implemented using a new low voltage amplifier with two-stage common-mode cancellation. The overall AFE was simulated to have 65.6 dB of signal-to-noise ratio (SNR), total harmonic distortion (THD) of less than 0.9% for a 100 Hz sinusoidal maximum input signal, bandwidth of 2 kHz, and power consumption of 51.2 µW. Spectre RF simulations were performed to validate the design using BSIM3V3 transistor models provided by GLOBALFOUNDRIES 0.18 µm CMOS process.