Voltage multiplier (VM) circuits for RF (2.45GHz)-to-DC conversion are developed for battery-less sensor nodes. Converted DC power is charged on a storage capacitor before driving a wireless sensor module. A charging time of the storage capacitor of the proposed VM circuits is reduced 1/10 of the conventional VM circuits, because they have constant current characteristics owing to self-control of body bias in diode-connected SOI MOSFETs. The wireless sensor system composed of the fabricated VM chip and a commercially available sensor module is operated using an RF signal of a wireless LAN modem (2.45GHz) as a power source.

In this paper, we propose an adaptive voltage huddle-based distributed-register architecture (AVHDR architecture), which integrates dynamic multiple supply voltages and interconnection delay into high-level synthesis. In AVHDR architecture, voltages can be dynamically assigned for energy reduction. In other words, low supply voltages are assigned to non-critical operations, and leakage power is cut off by turning off the power supply to the sleeping functional units. Next, an AVHDR-based high-level synthesis algorithm is proposed. Our algorithm is based on iterative improvement of scheduling/binding and floorplanning. In the iteration process, the modules in each huddle can be placed close to each other and the corresponding AVHDR architecture can be generated and optimized with floorplanning information. Experimental results show that on average our algorithm achieves 43.9% energy-saving compared with conventional algorithms.

This paper presents a 12-bit interpolated pipeline analog to digital converter (ADC) using body voltage controlled amplifier for current biasing and common mode feedback (CMFB). The proposed body voltage control method allows the amplifier to achieve small power consumption and large output swing. The proposed amplifier has a power consumption lower than 15.6mW, almost half of the folded cascode amplifier satisfying 12-bit, 400MS/s ADC operation. Moreover, the proposed amplifier secures 600mV output swing, which is one drain source voltage (VDS) wider compared with the telescopic amplifier. The 12-bit interpolated pipeline ADC using the proposed amplifier is fabricated in a 1P9M 90nm CMOS technology with a 1.2V supply voltage. The ADC achieves an effective number of bit (ENOB) of about 10-bit at 300MS/s and an figure of merit (FoM) of 0.2pJ/conv. when the frequency of the input signal is sufficiently low.

We have studied photo-induced effects in a p-type transistor based on a [1]benzothieno[3,2-b]benzothiophene (BTBT) derivative. Repetition of blue light irradiation and electrical characterization under dark reveals that its threshold voltage gradually shifts in the positive direction as the cumulative exposure time increases. This shift is slowly reversed when the transistor is stored under dark. The onset voltage defined as the gate bias at which the sub-threshold current exceeds a certain level behaves in a similar manner. Mobility remains more or less the same during this exposure period and the storage period. Time evolution of the threshold voltage shift is fit by a model assuming two charged meta-stable states decaying independently. A set of parameters consists of a decay constant for each state and the ratio of the two states. A single parameter set reproduces the positive shift during the exposure period and the negative shift during the storage period. Time evolution of the onset voltage is reproduced by the same parameter set. We have also studied photo-induced effects in two types of n-type transistors where either a pure solution of a perylene derivative or a solution mixed with an insulating polymer is used for printing each semiconductor layer. A similar behavior is observed for these transistors: blue light irradiation under a negative gate bias shifts the threshold and the onset voltages in the negative direction and these shifts are reversed under dark. The two-component model reproduces the behavior of these voltage shifts and the parameter set is slightly different among the two transistors made from different semiconductor solutions. The onset voltage shift is well correlated to the threshold voltage shift for the three types of organic transistors studied here. The onset voltage is more sensitive to illumination than the threshold voltage and its sensitivity differs among transistors.

In this paper, a 24GHz transformer-coupled VCO is presented for a wide linear tuning range in the 0.13-µm CMOS process. The measured results of the proposed VCO show that the center frequency is 23.5GHz with 7.4% frequency tuning range. The output frequency curve has wide linear tuning region (5.5%) at the middle of the curve. Also, the VCO exhibits good phase noise of -110.23dBc/Hz at an offset frequency of 1 MHz. It has a compact chip size of 430 × 500µm2. The VCO core DC power consumption is 5.4mW at 1.35V VDD.

This paper proposes a new double-edge-triggered implicitly level-converting flip-flop, suitable for a low-power and low-voltage design. The design employs a sense amplifier architecture to reduce the delay and power consumption. Experimentally, when implemented with a 130-nm, single-Vt and 0.84V VDD process, it achieves 64% power-delay product (PDP) improvement, and moreover, 78% PDP improvement when implemented with a mixed-Vt technology, as compared to that of the classic double-edge-triggered flip-flop design.

The influence of the splitter plates on the high-current arc roots formation in low voltage circuit breaker is investigated. One arc quenching chamber model is designed, where the shape of the splitter plates can be changed. The capacitor bank circuit is used to provide the test power supply, and the effective value of the prospective short circuit current is fixed to 10kA. High speed CCD camera is adopted to record the arc images during the arcing duration. Arc current and voltage are also measured to analyze the arc characteristics. In addition, a simplified 1-D thermal-electric model is developed to investigate the influence of the splitter plates on the distribution of the current density of the arc plasma with the assumption of local thermal equilibrium (LTE). It shows that the distance between the arc initial ignition location and the splitter plates is crucial to the arc root formation.

Design equations for satisfying off-nominal operating conditions of the class E amplifier with a nonlinear shunt capacitance for a grading coefficient of 0.5 and the duty cycle D=0.5 are derived. By exploiting the off-nominal class E operation, various amplifier parameters such as input voltage, operating frequency, output power, and load resistance can be set as design specifications. As a result of the analysis in this paper, the following extension of the usability of the class E amplifier was achieved. With rising up the dc supply voltage, the shunt capacitance which achieves the off-nominal operation can be increased. This means that a transistor with higher output capacitance can be used for ZVS operation. This also means that maximum operating frequency which achieves ZVS can be increased. An example of a design procedure of the class E amplifier is given. The theoretical results were verified with an experiment.

This paper proposes a novel approach for implementing an ultra-low-power voltage reference using the structure of self-cascode MOSFET, operating in the subthreshold region with a self-biased body effect. The difference between the two gate-source voltages in the structure enables the voltage reference circuit to produce a low output voltage below the threshold voltage. The circuit is designed with only MOSFETs and fabricated in standard 0.18-µm CMOS technology. Measurements show that the reference voltage is about 107.5 mV, and the temperature coefficient is about 40 ppm/, at a range from -20 to 80. The voltage line sensitivity is 0.017%/V. The minimum supply voltage is 0.85 V, and the supply current is approximately 24 nA at 80. The occupied chip area is around 0.028 mm2.

A 5.6-GHz 1-V balanced LC-tank Colpitts voltage controlled oscillator is designed and implemented with a TSMC 0.18-µm CMOS process. This proposed Colpitts VCO circuit adopts two single-ended complementary LC-tank VCOs coupled by two pairs of varactors. The proposed VCO operates at low power consumption because it has the same dc current path as the np-MOSFETs. The Measured results of the proposed VCO achieve tuning range of 670 MHz from 5.23 to 5.9 GHz while the controlled voltage is tuned from 0 to 1-V, phase noise of -118.8 dBc/Hz at 1 MHz offset frequency from the carrier of 5.6 GHz and output power of -10.97 dBm at the supply voltage of 1 V. The power consumption of the core circuit is 1.79 mW and the chip area including pads is 0.451 (0.55 0.82) mm2.

Distribution of current onset voltage (COV) as well as threshold voltage (VTH) and drain induced barrier lowering (DIBL) in MOSFETs fabricated by 65 nm technology is statistically analyzed. Although VTH distribution follows the normal distribution, COV and DIBL deviate from the normal distribution. It is newly found that COV follows the Gumbel distribution, which is known as one of the extreme value distributions. This result of statistical COV analysis supports our model that COV is mainly determined by the deepest potential valley between source and drain.

A modified modeling of residue effect on nano-electro-mechanical nonvolatile memory (NEMory) is presented for considering wet etching process. The effect of a residue under the cantilever is investigated for the optimization. The feasibility of the proposed model is investigated by finite element analysis simulations.

The trench-gate type high-voltage (HV) MOSFET is one of the variants of HV-MOSFET, typically with its utility segments lying on a larger power consumption domain, compared to planar HV-MOSFETs. In this work, the HiSIM_HV compact model, originally intended for planar LDMOSFETs, was adequately extended to accommodate trench-gate type HV-MOSFETs. The model formulation focuses on a closed-form description of the current path in the highly resistive drift region, specific to the trench-gate HV-MOSFETs. It is verified that the developed compact expression can capture the conductivity in the drift region, which varies with voltage bias and device technology such as trench width. The notable enhancement of current drivability can be accounted for by the electrostatic control exerted by the trench gate within the framework of this model.

In this paper, a high performance current latch sense amplifier (CLSA) with vertical MOSFET is proposed, and its performances are investigated. The proposed CLSA with the vertical MOSFET realizes a 11% faster sensing time with about 3% smaller current consumption relative to the conventional CLSA with the planar MOSFET. Moreover, the proposed CLSA with the vertical MOSFET achieves an 1.11 dB increased voltage gain G(f) relative to the conventional CLSA with the planar MOSFET. Furthermore, the proposed CLSA realizes up to about 1.7% larger yield than the conventional CLSA, and its circuit area is 42% smaller than the conventional CLSA.

For a development of energy harvesting system, the fact of radio waves and ambient RF (Radio Frequency) sources, including passive devices along with novel circuits, are very closely related to mobile charging devices and energy storage system. The use of schottky diode and voltage multiplier circuits to express on the ambient RF sources surrounding the system is one way that has seen a sudden rise in use for energy harvesting. Practically speaking, the RF and ambient sources can be provided by active and passive devices such as inductors, capacitors, diode, etc. In this paper, we present a schottky based voltage multiplier circuits for mobile charging device which integrate the power generation module with radio wave generation module. We also discuss that multi-stage schematic, e.g., three-stage schottky diode based voltage multiplier circuits, for a continuing effort on energy harvesting system.

In this paper we show that self synchronous circuits can provide robust operation in both soft error prone and low voltage operating environments. Self synchronous circuits are shown to be self checking, where a soft error will either cause a detectable error or halt operation of the circuit. A watchdog circuit is proposed to autonomously detect dual-rail '11' errors and prevent propagation, with measurements in 65 nm CMOS showing seamless operation from 1.6 V to 0.37 V. Compared to a system without the watchdog circuit size and energy-per-operation is increased 6.9% and 16% respectively, while error tolerance to noise is improved 83% and 40% at 1.2 V and 0.4 V respectively. A circuit that uses the dual-pipeline circuit style as redundancy against permanent faults is also presented and 40 nm CMOS measurement results shows correct operation with throughput of 1.2 GHz and 810 MHz at 1.1 V before and after disabling a faulty pipeline stage respectively.

This paper presents a decoupling capacitance boosting method for the resonant supply noise reduction by fast voltage hopping of DVS systems. The proposed method utilizes a foot transistor as a switch between a conventional decoupling capacitor (decap) and GND. The switching controls of the foot transistor depending on the supply noise states achieve an effective noise reduction as well as fast settling time compared with the conventional passive decaps. The measurement results of a test chip fabricated in a 0.18 µm CMOS technology show 12X boost of effective decap value, and 65.8% supply noise reduction with 96% settling time improvement.

This paper presents an adaptive cache architecture for wide-range reliable low-voltage operations. The proposed associativity-reconfigurable cache consists of pairs of cache ways so that it can exploit the recovery feature of the novel 7T/14T SRAM cell. Each pair has two operating modes that can be selected based upon the required voltage level of current operating conditions: normal mode for high performance and dependable mode for reliable low-voltage operations. We can obtain reliable low-voltage operations by application of the dependable mode to weaker pairs that cannot operate reliably at low voltages. Meanwhile leaving stronger pairs in the normal mode, we can minimize performance losses. Our chip measurement results show that the proposed cache can trade off its associativity with the minimum operating voltage. Moreover, it can decrease the minimum operating voltage by 140 mV achieving 67.48% and 26.70% reduction of the power dissipation and energy per instruction. Processor simulation results show that designing the on-chip caches using the proposed scheme results in 2.95% maximum IPC losses, but it can be chosen various performance levels. Area estimation results show that the proposed cache adds area overhead of 1.61% and 5.49% in 32-KB and 256-KB caches, respectively.

This paper is focused on discussing a low-voltage system for lightning, and in particular the testing equipment of surge arresters. Only by demonstrating the performance and applicability of arresters can we seek the most feasible and economic low-voltage solutions. After performing repeated experiments with the same testing samples, using different testing equipment, we compare the different test results in order to select the most suitable and applicable testing equipment. In addition, the basis of a surge current parameter design theory is confirmed and verified through the test results using a simple and compact Impulse Current Generator to test a wide range of samples. By performing the actual analyzes and experiments, we can understand deeply how R, L, and C affect surge current, current wave, and current wave time. The ideal testing equipment standards have been set as follows: (1) Test Voltage up to 20 kV; (2) Expand current range from 1.5 kA to 46.5 kA, with resolution 1.5 kA; and (3) Simple operational procedures.

The three-bit balanced ternary quantum voltage generator was designed and tested. This voltage generator is based on zero-crossing Shapiro steps (ZCSSs) in asymmetric two-junction SQUID. ZCSSs were observed on the current-voltage curves, and maximum and minimum current of ZCSSs were almost same, respectively for the three bits. 27-step quantum voltages from -13Φ0f to +13 Φ0f were observed by combinations of inputs of bit1, bit2 and bit3.