In this paper, class DE inverter with second order constant K band-pass filter is proposed. In the proposed inverter, the band-pass filter is used instead of the resonant filter in class DE inverter presented at the previous papers. By using band-pass filter, two important results can be gotten. One is the sensitivity of the output voltage to the operating frequency is suppressed by using band-pass filter. The other is that zero voltage switching operation appears when the operating frequency is lower than the nominal frequency. Moreover, it keeps the advantage of class DE inverter with resonant filter, that is, high power conversion efficiency under high frequency operation because of class E switching. The laboratory experiments achieve 90.4% power conversion efficiency under 1.98 W output power and 1.0 MHz operation.

We demonstrate low-voltage operation of a CMOS imager with an in-pixel large-gain comparator without degradation of the dynamic range by using a pulse-width-modulation scheme in pixel readout. Experimental results showed a dynamic range of 57 dB with a 1.0 V power supply voltage at the pixel array block, which demonstrates the possibility of low-voltage, single-power-supply operation of imagers fabricated with deep-submicron CMOS technologies.

The advanced-DFM (Design For Manufacturability) RAM provides the solution for the limitation of SRAM voltage scaling down and the countermeasure of the process fluctuations. The characteristics of this RAM are the voltage scalability (@0.6 V operation) with wide operating margin and the reliability of long data retention time. The memory cell consists of 2 Cell/bit with the complementary dynamic memory operation and has the 1 Cell/bit test mode for the accelerated screening against the marginal cells. The GND bitline pre-charge sensing scheme and SSW (Sense Synchronized Write) peripheral circuit technologies are also adopted for the low voltage and DFV (Dynamic Frequency and Voltage) controllable SoC which will be strongly required from the many kinds of applications. This RAM supports the DFM functions with both good cell/bit for advanced process technologies and the voltage scalable SoC memory platform.

A low voltage 3-5 GHz CMOS ultra-wideband low noise amplifier is presented in this paper. A second order bandpass input impedance matching technique is used to achieve the broadband input matching. A folded cascode structure is employed to reduce the supply voltage and power consumption. A source follower acts as the buffer stage for broadband output impedance matching. The supply voltage is only 0.7 V. The operation frequency is 3-5 GHz. The maximum power gain is 13.2 dB. The noise figure is 3-4.2 dB. The power consumption of the core circuit is only 6.3 mW.

A new level shifter is proposed in this paper that mitigates the contention problem between its pull-up and pull-down switches without suffering the delay penalty. Comparing this new one with two conventional shifters (CLS-1 and CLS-2) indicates that CLS-1 and CLS-2 have the delay times which are 308% and 26% slower than the proposed shifter when VDDL/VDDH=0.3 and the fan-out=2, respectively. In addition, the comparison of power-delay products shows CLS-2 consumes 28.5% more energy than the proposed shifter. For the layout area, the proposed shifter needs only 15% more than CLS-2. By comparing the propagation delay times, the power-delay products, and the area overhead, the proposed shifter is considered very suitable to future Very Deep Sub-Micron (VDSM) technologies with low-voltage applications.

This paper proposes the P-1 radiation model for the calculation of low voltage arc plasma. The influence of both emission and self-absorption are taken into account in this model. Based on the couple of electric field, magnetic field, flow field and thermal field, a three-dimensional arc chamber model is constructed and its radiation energy is calculated by the P-1 model with the spectrum divided into six bands. From the obtained distributions of temperature, incident radiation intensity, plasma velocity and current density by P-1 model, it is observed that temperature is obviously different from the result by net emission coefficient (NEC) method in the low temperature region. Arc column edges near the arc root also absorb radiation energy. Furthermore, compared with the result by NEC method, the arc column voltage calculated by P-1 model is lower and more close to the experimental result.

Contact resistance is caused by constriction resistance and film resistance through contact layers. It is well known that a surface film causes non-linear voltage and current characteristics. The origin of non-linearity is caused by tunneling electron through thin insulation barrier or jumping over the thick barrier (Shottky barrier) on the contact surface. In this paper, a new idea causing nonlinear property by only current constriction which flows through very small contact spot area, if there is no film layer, is proposed by the two dimensional contact model. The contact model, used in this paper, is a two dimensional type narrow path of contact area (short bridge) made by thin copper foil of 0.035 mm on a glass epoxy resin board. The contact part is made by scraping with an electric drill as a single bridge shape of 0.1 mm wide and 0.3 mm long on the centre of a board (100 mm100 mm). The 3rd harmonic distortion voltage was measured by using a Component Linearity Test Equipment (Type CLT1 made by Radiometer Electronics Company) which the system supplies a pure sine wave current of 10 kHz and detects a distortion voltage of 30 kHz by a narrow band pass filter circuit. The sensitivity of the Component Linearity Test Equipment (CLT1) is under a 10-9 volt. Four bridge samples were examined for the comparison of nonlinear distortion voltage. The distortion voltage of a sample (A) (0.1 mm wide, 0.3 mm long) is too larger than the one of the sample (B) (0.2 mm wide, 0.3 mm long) at the same applied voltage which resistance is not so different each other. It seems that current constriction to the spot (A) may heat up higher and cool down lower than (B). It would be also guessed that the power dissipation of 20 kHz cause temperature oscillation of 20 kHz, then it causes a component of contact resistance of 20 kHz, and therefore the product of 10 kHz current and 20 kHz resistance component cause 30 kHz component distortion voltage.

This paper describes a capacitive voltage probe (CVP) that can measure a common-mode voltage on a cable without touching its conductor. This CVP has two coaxial electrodes: the inner electrode works as a voltage pickup and the outer one shields the inner electrode. These electrodes separate into two parts for clamping to the cable. Using a high input impedance circuit, this probe measures the common-mode voltage by detecting the voltage difference between the two electrodes. The probe characteristics are evaluated by measuring its linearity and frequency response. The results show that this probe has a dynamic range of 100 dB and flat frequency response from 10 kHz to 30 MHz. Deviations in sensitivity due to the position of the clamped cable in the inner electrode and to differences in the cable radius are evaluated theoretically and experimentally. The results indicate that the influence of the cable position can be calibrated. Finally, measured data obtained using both an impedance stabilizing network (ISN) and a CVP are compared to confirm the validity of the CVP. The results show that data measured by the CVP closely agreed with that obtained by the ISN. Therefore, the CVP is useful for EMC measurements to evaluate common-mode disturbances.

This report presents Dual Field-modulating-Plates (Dual-FP) technology for a 28 V operated high power GaAs heterojunction FET (HJFET) amplifier. A developed HJFET has two FP electrodes; the 1st-FP is connected to the gate and the 2nd-FP to the ground. The 2nd-FP suppresses the drain current dispersion effectively cooperating with the 1st-FP, and it can also reduce the gate-drain parasitic capacitance. The developed push-pull amplifier, with four Dual-FPFET chips, demonstrated 55.1 dBm (320 W) output power with a 14.0 dB linear gain and a drain efficiency of 62% at 2.14 GHz. Under two-carrier W-CDMA signals, it showed a high drain efficiency of 30% and low third-order Inter-modulation distortion of -37 dBc at output power of 47.5 dBm.

Low-voltage nanometer-scale embedded RAM cells are described. First, low-voltage RAM cells are compared in terms of cell size, threshold voltage for MOS transistor, and signal charge. Second, the solution for 6T and 4T SRAM cells to widen the voltage margin are investigated, especially the advantages with a back-gate controlled thin buried-oxide fully-depleted (FD) SOI are presented. Then, DRAM approach with a novel twin-cell is discussed in terms of improving the retention time and low-voltage operation. These low-voltage cell technologies are the promising candidates for future embedded RAMs.

This paper discusses issues in the design of analog-to-digital converters (ADCs) in nanoscale CMOS and introduces some experimental designs incorporating techniques to solve these issues. Technology scaling increases the maximum conversion rate, but it decreases the gain and the SNR. To maintain a high SNR level despite the low-voltage operation, the power consumption needs to be increased. Because of lowered supply voltages, the design of circuits based on operational amplifiers (OpAmps) has become more difficult. Designs without OpAmps have therefore received more attention. One way of realizing low-voltage pipeline ADCs is by using comparator-controlled current sources, instead of conventional OpAmps. Furthermore, successive approximation ADCs and sub-ranging ADCs do not require OpAmps and are therefore suitable for low-voltage operation. ADC designers are now searching for suitable architectures for future nanoscale CMOS processes.

A multi-band burst-mode clock and data recovery (BMCDR) circuit is presented. The available data rates are 2488.32 Mbps, 1244.16 Mbps, 622.08 Mbps, and 155.52 Mbps, which are specified in a gigabit-capable passive optical network (GPON) [1]. A half-rate and low-jitter gated voltage-controlled oscillator (GVCO) and a phase-controlled frequency divider are used to achieve the multi-band reception. The proposed BMCDR circuit has been fabricated in a 0.18 µm CMOS process. Its active area is 0.41 mm2 and consumes 70 mW including I/O buffers from a 1.8 V supply.

A low-power sub-1-V self-biased low-voltage reference is proposed for micropower electronic applications based on body effect. The proposed reference has a very low temperature dependence by using a MOSFET with body effect compared with other reported low-power references. An HSPICE simulation shows that the reference voltage and the total power dissipation are 181 mV and 1.1 µW, respectively. The temperature coefficient of the reference voltage is 33 ppm/ at temperatures from -40 to 100. The supply voltage can be as low as 0.95 V in a standard CMOS 0.35 µm technology with threshold voltages of about 0.5 V and -0.65 V for n-channel and p-channel MOSFETs, respectively. Furthermore, the supply voltage dependence is -0.36 mV/V (Vdd=0.95-3.3 V).

A DRAM-cell array with 12-F2 twin cell was developed and evaluated in terms of speed, retention time, and low-voltage operation. The write and read-out times of the twin-cell array are shorter than those of a single-cell array by 70% and 40% respectively, because of parallel writing and reading of half charge to and from two memory cells. According to measured retention characteristics of the single cells, the twin-cell array improves retention time by 20% compared with the single-cell array at 1 V and keeps the retention time of the single-cell array at 0.4 V. Furthermore, the cell accepts the plate-driven scheme without the need of a dummy cell, lowering the necessary word-line voltage by 0.4 V.

This paper describes an 18-GHz coupled VCO array for low jitter and low phase deviation clock distribution. To reduce the skew, jitter and power consumption associated with clock distribution, the clock is generated by a one-dimensional VCO array in which the oscillating nodes of adjacent VCOs are directly connected with wires. The effects of the wire length and number of unit VCOs in the array are discussed. Both 4-unit and a 2-unit VCO arrays for delivering a clock signal to a 16:1 multiplexor were designed and fabricated in a 90-nm CMOS process. The frequency range of the 4-unit VCO array was 16 GHz to 18.5 GHz while each unit VCO consumed 2 mA.

A supply voltage (VDD) independent temperature sensor circuit, which can be realized by the optimum combination of three current modes of n-MOSFETs including the subthreshold current using the feedback scheme from the temperature dependent voltage (VTD) output to the gates of three n-MOSFETs, was proposed and fabricated by a standard 1.2 µm n-well CMOS process. The circuit consists of only 17 MOSFETs without high resistors resulting in a small die area of 0.18 mm2. The temperature coefficient TC of the sensor circuit can be controlled by the channel length ratio L4/L3 of two n-MOSFETs. The average temperature sensor voltage VTS and its typical TC are 1.77 V at VDD=5.0 V (20) and 5.1 mV/ for VDD=5.01.0 V in the temperature range of -20-100 in case of L4/L3=9, respectively.

Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose low power adders that adaptively select supply voltages based on the input vector patterns. First, we apply the proposed scheme to the Ripple Carry Adder (RCA). A prototype design by a 0.18 µm CMOS technology shows that the Adaptive VDD 32-bit RCA achieves 25% power improvement over the conventional RCA with similar speed. The proposed adder cancels out the delay penalty, utilizing two innovative techniques: carry-skip techniques on the checking operands, and the use of Complementary Pass Transistor Logic (CPL) with dual supply voltage for level conversion. As an expansion to faster adder architectures, we extend the proposal to the Carry-Select Adders (CSA) composed of the RCA sub-blocks. We achieved 24% power improvement on the 128-bit CSA prototype over a conventional design. The proposed scheme also achieves stand-by leakage power reduction--for 32-bit and 128-bit Adaptive RCA and CSA, respectively, 62% and 54% leakage reduction was possible.

A novel high-speed and low-voltage CMOS level shifter circuit is proposed. The proposed circuit is suitable for block-level dynamic voltage and frequency scaling (DVFS) environment or multiple-clock and multiple-power-domain logic blocks. In order to achieve high performance in a chip consisting of logic blocks having different VDD voltages, the proposed circuit uses the circuit techniques to reduce the capacitive loading of input signals and to minimize the contention between pull-up and pull-down transistors through positive feedback loop. The techniques improve the slew rate of output signals, so that the level transient delay and duty distortions can be reduced. The proposed level up/down shifters are designed to operate over a wide range of voltage and frequency and verified with Berkeley's 65 nm CMOS model parameters, which can cover a voltage range from 0.6 to 1.6 V and at least frequency range up to 1000 MHz within 3% duty errors. Through simulation with Berkeley's 65 nm CMOS model parameters, the level shifter circuits can solve the duty distortion preventing them from high speed operation within the duty ratio error of 3% at 1 GHz. For verification through performance comparison with reported level shifts, the simulations are carried out with 0.35 µm CMOS technology, 0.13 µm IBM CMOS technology and Berkeley's 65 nm CMOS model parameters. The compared results show that delay time and duty ratio distortion are improved about 68% and 75%, respectively.

A new current reused quadrature voltage controlled oscillator (QVCO) is proposed and implemented using UMC 0.18 µm CMOS 1P6M process. The proposed circuit topology is made up two low voltage LC-tank VCOs, where the QVCO is obtained using the transformer coupling and current reuse technique. At 1.8 V supply voltage, the phase noise of the VCO is -117.13 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 2.18 GHz, the core power consumption is 4.14 mW, the total power consumption is 6.48 mW and tuning range is about 160 MHz.

This paper proposes a synthesis method of all low-voltage CMOS instantaneous-companding log domain integrators. The method is based on the exhaustive search of all low-voltage CMOS instantaneous-companding log domain integrators. All the integrators are derived from a general block diagram. A function of each block can be realized by any of a family of circuits and elemental circuits chosen from such families are combined to build an integrator. It is clarified that each family contains a few circuit topologies. All topologies of integrators including new ones are obtained from combinational procedure. Comparing characteristics of all generated integrators, ones satisfying required performances are found out.