This paper presents a miniaturized transformer-based ultra-low-power (ULP) LC-VCO with embedded supply pushing reduction techniques for IoT applications in 65-nm CMOS process. To reduce the on-chip area, a compact transformer patterned ground shield (PGS) is implemented. The transistors with switchable capacitor banks and associated components are placed underneath the transformer, which further shrinking the on-chip area. To lower the power consumption of VCO, a gm-stacked LC-VCO using the transformer embedded with PGS is proposed. The transformer is designed to provide large inductance to obtain a robust start-up within limited power consumption. Avoiding implementing an off/on-chip Low-dropout regulator (LDO) which requires additional voltage headroom, a low-power supply pushing reduction feedback loop is integrated to mitigate the current variation and thus the oscillation amplitude and frequency can be stabilized. The proposed ULP TF-based LC-VCO achieves phase noise of -114.8dBc/Hz at 1MHz frequency offset and 16kHz flicker corner with a 103µW power consumption at 2.6GHz oscillation frequency, which corresponds to a -193dBc/Hz VCO figure-of-merit (FoM) and only occupies 0.12mm2 on-chip area. The supply pushing is reduced to 2MHz/V resulting in a -50dBc spur, while 5MHz sinusoidal ripples with 50mVPP are added on the DC supply.

Cross-project defect prediction (CPDP) is a feasible solution to build an accurate prediction model without enough historical data. Although existing methods for CPDP that use only labeled data to build the prediction model achieve great results, there are much room left to further improve on prediction performance. In this paper we propose a Semi-Supervised Discriminative Feature Learning (SSDFL) approach for CPDP. SSDFL first transfers knowledge of source and target data into the common space by using a fully-connected neural network to mine potential similarities of source and target data. Next, we reduce the differences of both marginal distributions and conditional distributions between mapped source and target data. We also introduce the discriminative feature learning to make full use of label information, which is that the instances from the same class are close to each other and the instances from different classes are distant from each other. Extensive experiments are conducted on 10 projects from AEEEM and NASA datasets, and the experimental results indicate that our approach obtains better prediction performance than baselines.

This paper discusses and elaborates an analytical model of a multi-stage switched-capacitor (SC) voltage boost converter (VBC) for low-voltage and low-power energy harvesting systems, because the output impedance of the VBC, which is derived from the analytical model, plays an important role in the VBC's performance. In our proposed method, we focus on currents flowing into input and output terminals of each stage and model the VBCs using switching frequency f, charge transfer capacitance CF, load capacitance CL, and process dependent parasitic capacitance's parameter k. A comparison between simulated and calculated results showed that our model can estimate the output impedance of the VBC accurately. Our model is useful for comparing the relative merits of different types of multi-stage SC VBCs. Moreover, we demonstrate the performance of a prototype SC VBC and energy harvesting system using the SC VBC to show the effectiveness and feasibility of our proposed design guideline.

This paper proposes and demonstrates a 65nm CMOS process cascode single-inductor-dual-output (SIDO) boost converter whose outputs are Li-ion battery and 1V low voltage supply for RF wireless power transfer (WPT) receiver. The 1V power supply is used for internal control circuits to reduce power consumption. In order to withstand 4.2V Li-ion battery output, cascode 2.5V I/O PFETs are used at the power stage. On the other hand, to generate 1V while maintaining 4.2V tolerance at 1V output, cascode 2.5V I/O NFETs output stage is proposed. Measurement results show conversion efficiency of 87% at PIN=7mW, ILOAD=1.6mA and VBAT=4.0V, and 89% at PIN=7.9mW, ILOAD=2.1mA and VBAT=3.4V.

Intersymbol interference (ISI) is a significant source of degradation in many digital communication systems including our proposed non-far region communication system using large array antennas in the millimeter-wave band in which the main cause of ISI can be attributed to the path delay differences among the elements of an array antenna. This paper proposes a quantitative method to evaluate the ISI estimated from the measured near-field distribution of the array antenna. The influence of the uniformity in the aperture field distribution in ISI is discussed and compared with an ideally uniform excitation. The reliability of the proposed method is verified through a comparison with another method based on direct measurements of the transmission between the actual antennas. Finally, the signal to noise plus interference is evaluated based on the estimated ISI results and ISI is shown to be the dominant cause of the degradation in the reception zone of the system.

To tackle the distributed power optimization problems in wireless sensor networks localization systems, we model the problem as a hierarchical game, i.e. a multi-leader multi-follower Stackelberg game. Existing researches focus on the power allocation of anchor nodes for ranging signals or the power management of agent nodes for cooperative localization, individually. However, the power optimizations for different nodes are indiscerptible due to the common objective of localization accuracy. So it is a new challenging task when the power allocation strategies are considered for anchor and agent nodes simultaneously. To cope with this problem, a hierarchical game is proposed where anchor nodes are modeled as leaders and agent nodes are modeled as followers. Then, we prove that games of leaders and followers are both potential games, which guarantees the Nash equilibrium (NE) of each game. Moreover, the existence of Stackelberg equilibrium (SE) is proved and achieved by the best response dynamics. Simulation results demonstrate that the proposed algorithm can have better localization accuracy compared with the decomposed algorithm and uniform strategy.

Road traffic collisions are an extremely serious and often fatal issue. One promising approach to mitigate such collisions is the use of connected car services that share road traffic information obtained from vehicles and cameras over mobile networks. In connected car services, it is important for data chunks to arrive at a destination node within a certain deadline constraint. In this paper, we define a flow from a vehicle (or camera) to the same vehicle (or camera) via an MEC server, as a mission critical (MC) flow, and call a deadline of the MC flow the MC deadline. Our research objective is to achieve a higher arrival ratio within the MC deadline for the MC flow that passes through both the radio uplink and downlink. We previously developed a deadline-aware scheduler with consideration for quality fluctuation (DAS-QF) that considers chunk size and a certain deadline constraint in addition to radio quality and utilizes these to prioritize users such that the deadline constraints are met. However, this DAS-QF does not consider that the congestion levels of evolved NodeB (eNB) differ depending on the eNB location, or that the uplink congestion level differs from the downlink congestion level in the same eNB. Therefore, in the DAS-QF, some data chunks of a MC flow are discarded in the eNB when they exceed either the uplink or downlink deadline in congestion, even if they do not exceed the MC deadline. In this paper, to reduce the eNB packet drop probability due to exceeding either the uplink and downlink deadline, we propose a deadline coordination function (DCF) that adaptively sets each of the uplink and downlink deadlines for the MC flow according to the congestion level of each link. Simulation results show that the DAS-QF with DCF offers higher arrival ratios within the MC deadline compared to DAS-QF on its own

This paper presents a weighted spatial filter (WSF) design method based on direction of arrival (DOA) estimates for a novel array configuration called a sum and difference composite co-array. A sum and difference composite co-array is basically a combination of sum and difference co-arrays. Our configuration can realize higher degrees of freedom (DOF) with the sum co-array part at a calculation cost lower than those of the other sparse arrays. To further enhance the robustness of our proposed sum and difference composite co-array we design an optimal beam pattern by WSF based on the information of estimated DOAs. Performance of the proposed system and the DOA estimation accuracy of close-impinging waves are evaluated through computer simulations.

This paper presents two ultra-low voltage and high performance VCO ICs with two novel transformer-based harmonic tuned tanks. The first proposed harmonic tuned tank effectively shapes the pseudo-square drain-node voltage waveform for close-in phase noise reduction. To compensate the voltage drop caused by the transformer, an improved second tank is proposed. It not only has tuned harmonic impedance but also provides a voltage gain to enlarge the output voltage swing over supply voltage limitation. The VCO with second tank exhibits over 3 dB better phase noise performance in 1/f2 region among all tuning range. The two VCO ICs are designed, fabricated and measured on wafer in 45-nm SOI CMOS technology. With only 0.3 V supply voltage, the proposed two VCO ICs exhibit best phase noise of -123.3 and -127.2 dBc/Hz at 10 MHz offset and related FoMs of -191.7 and -192.2 dBc/Hz, respectively. The frequency tuning ranges of them are from 14.05 to 15.14 GHz and from 14.23 to 15.68 GHz, respectively.

Chopping technique up-modulates amplifier's offset and low-frequency noise up to its switching frequency, and therefore can achieve low offset and low temperature drift. On the other hand, it generates unwanted AC and DC errors due to its switching artifacts such as up-modulated ripple and glitches. This paper summarizes various circuit techniques of reducing such switching artifacts, and then discusses the advantages and disadvantages of each technique. The comparison shows that newer designs with advanced circuit techniques can achieve lower DC and AC errors with higher chopping frequency.

Hum noise such as power line interference is one of the critical problems in the biomedical signal acquisition. Various techniques have been proposed to suppress power line interference. However, some of the techniques require more components and power consumption. The notch depth in the conventional N-path notch filter circuits needs a higher number of paths and switches off-resistance. It makes the conventional N-path notch filter less of efficiency to suppress hum noise. This work proposed the new N-path notch filter to hum noise suppression in biomedical signal acquisition. The new N-path notch filter achieved notch depth above 40dB with sampling frequency 50Hz and 60Hz. Although the proposed circuits use less number of path and switches off-resistance. The proposed circuit has been verified using artificial ECG signal contaminated by hum noise at frequency 50Hz and 60Hz. The output of N-path notch filter achieved a noise-free signal even if the sampling frequency changes.

This paper presents a design of CMOS transimpedance amplifier (TIA) and peaking inductor for high speed, low power and small area. To realize high density integration of optical I/O, area reduction is an important figure as well as bandwidth, power and so on. To determine design parameters of multi-stage inverter-type TIA (INV-TIA) with peaking inductors, we derive a simplified model of the bandwidth and the energy per bit. Multi-layered on-chip inductors are designed for area-effective inductive peaking. A 5-stage INV-TIA with 3 peaking inductors is fabricated in a 65-nm CMOS. By using multi-layered inductors, 0.02 mm2 area is achieved. Measurement results show 45 Gb/s operation with 49 dBΩ transimpedance gain and 4.4 mW power consumption. The TIA achieves 98 fJ/bit energy efficiency.

Many studies of deep neural networks have reported inference accelerators for improved energy efficiency. We propose methods for further improving energy efficiency while maintaining recognition accuracy, which were developed by the co-design of a filter-by-filter quantization scheme with variable bit precision and a hardware architecture that fully supports it. Filter-wise quantization reduces the average bit precision of weights, so execution times and energy consumption for inference are reduced in proportion to the total number of computations multiplied by the average bit precision of weights. The hardware utilization is also improved by a bit-parallel architecture suitable for granularly quantized bit precision of weights. We implement the proposed architecture on an FPGA and demonstrate that the execution cycles are reduced to 1/5.3 for ResNet-50 on ImageNet in comparison with a conventional method, while maintaining recognition accuracy.

For automotive millimeter radar, a method using a multi-input multi-output (MIMO) array antenna is essential for high angle resolution with module miniaturization. MIMO enables us to extend an antenna array with virtual antennas, and a large antenna array aperture enables high resolution angle estimation. Time division multiplex (TDM) MIMO, which is a method to generate virtual array antennas, makes it easy to design radar system integrated circuits. However, this method leads to two issues in signal processing; the phase error reduces the accuracy of angle estimation of a moving target, and the maximum detectable velocity decreases in inverse proportion to the number of Tx antennas. We analytically derived this phase error and proposed a method to correct the error. Because the phase error of TDM-MIMO is proportional to the target velocity, accurate estimation of the target velocity is an important issue for phase error correction. However, the decrease of the maximum detectable velocity in TDM-MIMO reduces the accuracy of both velocity estimation and angle estimation. To solve these issues, we propose new signal processing for range-velocity estimation for TDM-MIMO radar. By using the feedback result of the estimated direction of arrival (DoA), we can avoid decreasing the maximum detectable velocity. We explain our method with our simulation results.

The task of image annotation is becoming enormously important for efficient image retrieval from the web and other large databases. However, huge semantic information and complex dependency of labels on an image make the task challenging. Hence determining the semantic similarity between multiple labels on an image is useful to understand any incomplete label assignment for image retrieval. This work proposes a novel method to solve the problem of multi-label image annotation by unifying two different types of Laplacian regularization terms in deep convolutional neural network (CNN) for robust annotation performance. The unified Laplacian regularization model is implemented to address the missing labels efficiently by generating the contextual similarity between labels both internally and externally through their semantic similarities, which is the main contribution of this study. Specifically, we generate similarity matrices between labels internally by using Hayashi's quantification method-type III and externally by using the word2vec method. The generated similarity matrices from the two different methods are then combined as a Laplacian regularization term, which is used as the new objective function of the deep CNN. The Regularization term implemented in this study is able to address the multi-label annotation problem, enabling a more effectively trained neural network. Experimental results on public benchmark datasets reveal that the proposed unified regularization model with deep CNN produces significantly better results than the baseline CNN without regularization and other state-of-the-art methods for predicting missing labels.

Optical navigation (OPNAV) is the use of the on-board imaging data to provide a direct measurement of the image coordinates of the target as navigation information. Among the optical observables in deep-space, the edge of the celestial body is an important feature that can be utilized for locating the planet centroid. However, traditional edge detection algorithms like Canny algorithm cannot be applied directly for OPNAV due to the noise edges caused by surface markings. Moreover, due to the constrained computation and energy capacity on-board, light-weight image-processing algorithms with less computational complexity are desirable for real-time processing. Thus, to fast and accurately extract the edge of the celestial body from high-resolution satellite imageries, this paper presents an algorithm-hardware co-design of real-time edge detection for OPNAV. First, a light-weight edge detection algorithm is proposed to efficiently detect the edge of the celestial body while suppressing the noise edges caused by surface markings. Then, we further present an FPGA implementation of the proposed algorithm with an optimized real-time performance and resource efficiency. Experimental results show that, compared with the traditional edge detection algorithms, our proposed one enables more accurate celestial body edge detection, while simplifying the hardware implementation.

Current stereo matching methods benefit a lot from the precise stereo estimation with Convolutional Neural Networks (CNNs). Nevertheless, patch-based siamese networks rely on the implicit assumption of constant depth within a window, which does not hold for slanted surfaces. Existing methods for handling slanted patches focus on post-processing. In contrast, we propose a novel module for matching cost networks to overcome this bias. Slanted objects appear horizontally stretched between stereo pairs, suggesting that the feature extraction in the horizontal direction should be different from that in the vertical direction. To tackle this distortion, we utilize asymmetric convolutions in our proposed module. Experimental results show that the proposed module in matching cost networks can achieve higher accuracy with fewer parameters compared to conventional methods.

High frame rate (HFR) video is attracting strong interest since it is considered as a next step toward providing Ultra-High Definition video service. For instance, the Association of Radio Industries and Businesses (ARIB) standard, the latest broadcasting standard in Japan, defines a 120 fps broadcasting format. The standard stipulates temporally scalable coding and hierarchical transmission by MPEG Media Transport (MMT), in which the base layer and the enhancement layer are transmitted over different paths for flexible distribution. We have developed the first ever MMT transmitter/receiver module for 4K/120fps temporally scalable video. The module is equipped with a newly proposed encapsulation method of temporally scalable bitstreams with correct boundaries. It is also designed to be tolerant to severe network constraints, including packet loss, arrival timing offset, and delay jitter. We conducted a hierarchical transmission experiment for 4K/120fps temporally scalable video. The experiment demonstrated that the MMT module was successfully fabricated and capable of dealing with severe network constraints. Consequently, the module has excellent potential as a means to support HFR video distribution in various network situations.

The recent development of semiconductor technology has led to downsized, large-scaled and low-power VLSI systems. However, the incidence of soft errors has increased. Soft errors are temporary events caused by striking of α-rays and high energy neutron radiation. Since the scale of VLSI has become smaller in recent development, it is necessary to consider the occurrence of not only single node upset (SNU) but also double node upset (DNU). The existing High-performance, Low-cost, and DNU Tolerant Latch design (HLDTL) does not completely tolerate DNU. This paper presents a new design of a DNU tolerant latch to resolve this issue by adding some transistors to the HLDTL latch.

In this paper, we present non-Markovian availability models for capturing the dynamics of system behavior of an operational software system that undergoes aperiodic time-based software rejuvenation and checkpointing. Two availability models with rejuvenation are considered taking account of the procedure after the completion of rollback recovery operation. We further proceed to investigate whether there exists the optimal rejuvenation schedule that maximizes the steady-state system availability, which is derived by means of the phase expansion technique, since the resulting models are not the trivial stochastic models such as semi-Markov process and Markov regenerative process, so that it is hard to solve them by using the common approaches like Laplace-Stieltjes transform and embedded Markov chain techniques. The numerical experiments are conducted to determine the optimal rejuvenation trigger timing maximizing the steady-state system availability for each availability model, and to compare both two models.