We propose a pre-T event-triggered controller (ETC) for the stabilization of a chain of integrators. Our per-T event-triggered controller is a modified event-triggered controller by adding a pre-defined positive constant T to the event-triggering condition. With this pre-T, the immediate advantages are (i) the often complicated additional analysis regarding the Zeno behavior is no longer needed, (ii) the positive lower bound of interexecution times can be specified, (iii) the number of control input updates can be further reduced. We carry out the rigorous system analysis and simulations to illustrate the advantages of our proposed method over the traditional event-triggered control method.

The development of energy-efficient neural network hardware using magnetic tunnel junction (MTJ) devices has been widely investigated. One of the issues in the use of MTJ devices is large write energy. Since MTJ devices show stochastic behaviors, a large write current with enough time length is required to guarantee the certainty of the information held in MTJ devices. This paper demonstrates that quantized neural networks (QNNs) exhibit high tolerance to bit errors in weights and an output feature map. Since probabilistic switching errors in MTJ devices do not have always a serious effect on the performance of QNNs, large write energy is not required for reliable switching operations of MTJ devices. Based on the evaluation results, we achieve about 80% write-energy reduction on buffer memory compared to the conventional method. In addition, it is demonstrated that binary representation exhibits higher bit-error tolerance than the other data representations in the range of large error rates.

This paper proposes a novel differential active self-interference canceller (DASIC) algorithm for asynchronous in-band full-duplex (IBFD) Gaussian filtered frequency shift keying (GFSK), which is designed for wireless Internet of Things (IoT). In IBFD communications, where two terminals simultaneously transmit and receive signals in the same frequency band, there is an extremely strong self-interference (SI). The SI can be mitigated by an active SI canceller (ASIC), which subtracts an interference replica based on channel state information (CSI) from the received signal. The challenging problem is the realization of asynchronous IBFD for wireless IoT in indoor environments. In the asynchronous mode, pilot contamination is induced by the non-orthogonality between asynchronous pilot sequences. In addition, the transceiver suffers from analog front-end (AFE) impairments, such as phase noise. Due to these impairments, the SI cannot be canceled entirely at the receiver, resulting in residual interference. To address the above issue, the DASIC incorporates the principle of the differential codec, which enables to suppress SI without the CSI estimation of SI owing to the differential structure. Also, on the premise of using an error correction technique, iterative detection and decoding (IDD) is applied to improve the detection capability while exchanging the extrinsic log-likelihood ratio (LLR) between the maximum a-posteriori probability (MAP) detector and the channel decoder. Finally, the validity of using the DASIC algorithm is evaluated by computer simulations in terms of the packet error rate (PER). The results clearly demonstrate the possibility of realizing asynchronous IBFD.

Data resource sharing can guarantee the reliable and safe operation of distribution power grid. However, it faces the challenges of low security and high delay in the sharing process. Consortium blockchain can ensure the security and efficiency of data resource sharing, but it still faces problems such as arbitrary master node selection and high consensus delay. In this paper, we propose an improved practical Byzantine fault tolerance (PBFT) consensus algorithm based on intelligent consensus node selection to realize high-security and real-time data resource sharing for distribution power grid. Firstly, a blockchain-based data resource sharing model is constructed to realize secure data resource storage by combining the consortium blockchain and interplanetary file system (IPFS). Then, the improved PBFT consensus algorithm is proposed to optimize the consensus node selection based on the upper confidence bound of node performance. It prevents Byzantine nodes from participating in the consensus process, reduces the consensus delay, and improves the security of data resource sharing. The simulation results verify the effectiveness of the proposed algorithm.

An optical mode multiplexer was newly designed and fabricated using LiNbO3 waveguides. The multiplexer consists of an asymmetric directional coupler capable of achieving the phase-matching condition by the voltage adjustment. The mode conversion efficiency between TM0 and TM1 modes was quantitatively measured to be 0.86 at maximum.

In cyber-physical systems (CPSs) that interact between physical and information components, there are many sensors that are connected through a communication network. In such cases, the reduction of communication costs is important. Event-triggered control that the control input is updated only when the measured value is widely changed is well known as one of the control methods of CPSs. In this paper, we propose a design method of output feedback controllers with decentralized event-triggering mechanisms, where the notion of uniformly ultimate boundedness is utilized as a control specification. Using this notion, we can guarantee that the state stays within a certain set containing the origin after a certain time, which depends on the initial state. As a result, the number of times that the event occurs can be decreased. First, the design problem is formulated. Next, this problem is reduced to a BMI (bilinear matrix inequality) optimization problem, which can be solved by solving multiple LMI (linear matrix inequality) optimization problems. Finally, the effectiveness of the proposed method is presented by a numerical example.

In recent years, to meet strict time-to-market constraints, it has become difficult for only one semiconductor design company to design a VLSI. Thus, design companies purchase IP cores from third-party IP vendors and design only the necessary parts. On the other hand, since IP cores have the disadvantage that copyright infringement can be easily performed, logic locking has to be applied to them. Functional logic locking methods using TTLock are resilient to SAT attacks however vulnerable to FALL attacks. Additionally, it is difficult to design logic locking based on TTLock at the gate level. This paper proposes a logic locking method, CRLock, based on SAT attack and FALL attack resistance at the register transfer level. The CRLock is a logic locking method for controllers at RTL in which the designer selects a protected input pattern and modifies the controller based on the protection input pattern. In experimental results, we applied CRLock to MCNC'91 benchmark circuits and showed that all circuits are resistant to SAT and FALL attacks.

This paper presents the design of a capacitive coupler for underwater wireless power transfer focused on the landing direction of a drone. The main design feature is the relative position of power feeding/receiving points on the coupler electrodes, which depends on the landing direction of the drone. First, the maximum power transfer efficiencies of coupled lines with different feeding positions are derived in a uniform dielectric environment, such as that realized underwater. As a result, these are formulated by the coupling coefficient of the capacitive coupler, the unloaded qualify factor of dielectrics, and hyperbolic functions with complex propagation constants. The hyperbolic functions vary depending on the relative positions and whether these are identical or opposite couplers, and the efficiencies of each coupler depend on the type of water, such as seawater and tap water. The design method was demonstrated and achieved the highest efficiencies of 95.2%, 91.5%, and 85.3% in tap water at transfer distances of 20, 50, and 100 mm, respectively.

Binary Neural Networks (BNN) have binarized neuron and connection values so that their accelerators can be realized by extremely efficient hardware. However, there is a significant accuracy gap between BNNs and networks with wider bit-width. Conventional BNNs binarize feature maps by static globally-unified thresholds, which makes the produced bipolar image lose local details. This paper proposes a multi-input activation function to enable adaptive thresholding for binarizing feature maps: (a) At the algorithm level, instead of operating each input pixel independently, adaptive thresholding dynamically changes the threshold according to surrounding pixels of the target pixel. When optimizing weights, adaptive thresholding is equivalent to an accompanied depth-wise convolution between normal convolution and binarization. Accompanied weights in the depth-wise filters are ternarized and optimized end-to-end. (b) At the hardware level, adaptive thresholding is realized through a multi-input activation function, which is compatible with common accelerator architectures. Compact activation hardware with only one extra accumulator is devised. By equipping the proposed method on FPGA, 4.1% accuracy improvement is achieved on the original BNN with only 1.1% extra LUT resource. Compared with State-of-the-art methods, the proposed idea further increases network accuracy by 0.8% on the Cifar-10 dataset and 0.4% on the ImageNet dataset.

Most quantum circuits require SWAP gate insertion to run on quantum hardware with limited qubit connectivity. A promising SWAP gate insertion method for blocks of commuting two-qubit gates is a predetermined swap strategy which applies layers of SWAP gates simultaneously executable on the coupling map. A good initial mapping for the swap strategy reduces the number of required swap gates. However, even when a circuit consists of commuting gates, e.g., as in the Quantum Approximate Optimization Algorithm (QAOA) or trotterized simulations of Ising Hamiltonians, finding a good initial mapping is a hard problem. We present a SAT-based approach to find good initial mappings for circuits with commuting gates transpiled to the hardware with swap strategies. Our method achieves a 65% reduction in gate count for random three-regular graphs with 500 nodes. In addition, we present a heuristic approach that combines the SAT formulation with a clustering algorithm to reduce large problems to a manageable size. This approach reduces the number of swap layers by 25% compared to both a trivial and random initial mapping for a random three-regular graph with 1000 nodes. Good initial mappings will therefore enable the study of quantum algorithms, such as QAOA and Ising Hamiltonian simulation applied to sparse problems, on noisy quantum hardware with several hundreds of qubits.

In this paper, a wireless communication network that uses unmanned aerial vehicles (UAVs) in the sky to transmit information between ground users is considered. We highlight a delay-tolerant network, where information is relayed in a store-and-forward fashion by establishing two types of intermittent communication links: between a UAV and a user (UAV-to-user) and between UAVs (UAV-to-UAV). Thus, a flight algorithm that controls the movement of the UAVs is crucial in achieving rapid information transmission. Our study proposes new flight algorithms that simultaneously consider the two types of communication links. In UAV-to-UAV links, the direct information transmission between two UAVs and the indirect transmission through other UAVs are considered separately. The movement of the UAVs is controlled by solving an optimization problem at certain time intervals, with a variable consideration ratio of the two types of links. In addition, we investigate not only the case where all UAVs move cooperatively but also the case where each UAV moves autonomously. Simulation results show that the proposed algorithms are effective. Moreover, they indicate the existence of an optimal consideration ratio of the two types of communication and demonstrate that our approach enables the control of frequencies of establishing the communication links. We conclude that increasing the frequency of indirect communication between UAVs improves network performance.

Indoor free space optical (FSO) communication technology that provides high-speed connectivity to edge users is expected to be introduced in the near future mobile communication system, where the silicon photonics solid-state beam scanning device is a promising tool because of its low cost, long-term reliability, and other beneficial properties. However, the current two-dimensional beam scanning devices using grating coupler arrays have difficulty in increasing the transmission capacity because of bandwidth regulation. To solve the problem, we have introduced a broadband surface optical coupler, “elephant coupler,” which has great potential for combining wavelength and spatial division multiplexing technologies into the beam scanning device, as an alternative to grating couplers. The prototype port-selective silicon beam scanning device fabricated using a 300 mm CMOS pilot line achieved broadband optical beam emission with a 1 dB-loss bandwidth of 40 nm and demonstrated beam scanning using an imaging lens. The device has also exhibited free-space signal transmission of non-return-to-zero on-off-keying signals at 10 Gbps over a wide wavelength range of 60 nm. In this paper, we present an overview of the developed beam scanning device. Furthermore, the theoretical design guidelines for indoor mobile FSO communication are discussed.

In this article, a new Beamforming Network (BFN) realized in Broadside Coupled Stripline (BCS) is proposed to feed 1×4 and 2×2 arrays antenna at 28 GHZ-Band. The new BFN is composed only of couplers and phase shifters. It doesn't require any crossover compared to the conventional Butler Matrix (BM) which requires two crossovers. The tight coupling and low loss characteristics of the BCS allow a design of a compact and wideband BFN. The new BFN produces the phase differences of (±90°) and (±45°, ±135°) respectively in x- and y-directions. Its integration with a 1×4 linear array antenna reduces the array area by 70% with an improvement of the gain performance compared with the conventional array. The integration with a 2×2 array allows the realization of a full 2-D beam scanning. The proposed concept has been verified experimentally by measuring the fabricated prototypes of the BFN, the 1-D and 2-D patch arrays antennas. The measured 11.5 dBi and 11.3 dBi maximum gains are realized in θ0 = 14° and (θ0, φ0) = (45°,345°) directions respectively for the 1-D and 2-D patch arrays. The physical area of the fabricated BFN is only (0.37λ0×0.3λ0×0.08λ0), while the 1-D array and 2-D array antennas areas without feeding transmission lines are respectively (0.5λ0×2.15λ0×0.08λ0) and (0.9λ0×0.8λ0×0.08λ0).

High power dissipation during scan test often causes undue yield loss, especially for low-power circuits. One major reason is that the resulting IR-drop in shift mode may corrupt test data. A common approach to solving this problem is partial-shift, in which multiple scan chains are formed and only one group of scan chains is shifted at a time. However, existing partial-shift based methods suffer from two major problems: (1) their IR-drop estimation is not accurate enough or computationally too expensive to be done for each shift cycle; (2) partial-shift is hence applied to all shift cycles, resulting in long test time. This paper addresses these two problems with a novel IR-drop-aware scan shift method, featuring: (1) Cycle-based IR-Drop Estimation (CIDE) supported by a GPU-accelerated dynamic power simulator to quickly find potential shift cycles with excessive peak IR-drop; (2) a scan shift scheduling method that generates a scan chain grouping targeted for each considered shift cycle to reduce the impact on test time. Experiments on ITC'99 benchmark circuits show that: (1) the CIDE is computationally feasible; (2) the proposed scan shift schedule can achieve a global peak IR-drop reduction of up to 47%. Its scheduling efficiency is 58.4% higher than that of an existing typical method on average, which means our method has less test time.

A fault-tolerant aggregate signature (FT-AS) scheme is a variant of an aggregate signature scheme with the additional functionality to trace signers that create invalid signatures in case an aggregate signature is invalid. Several FT-AS schemes have been proposed so far, and some of them trace such rogue signers in multi-rounds, i.e., the setting where the signers repeatedly send their individual signatures. However, it has been overlooked that there exists a potential attack on the efficiency of bandwidth consumption in a multi-round FT-AS scheme. Since one of the merits of aggregate signature schemes is the efficiency of bandwidth consumption, such an attack might be critical for multi-round FT-AS schemes. In this paper, we propose a new multi-round FT-AS scheme that is tolerant of such an attack. We implement our scheme and experimentally show that it is more efficient than the existing multi-round FT-AS scheme if rogue signers randomly create invalid signatures with low probability, which for example captures spontaneous failures of devices in IoT systems.

The existing target-dependent scalable image compression network can control the target of the compressed images between the human visual system and the deep learning based classification task. However, in its RNN based structure controls the bit-rate through the number of iterations, where each iteration generates a fixed size of the bit stream. Therefore, a large number of iterations are required at the high BPP, and fine-grained image quality control is not supported at the low BPP. In this paper, we propose a novel RNN-based image compression model that can schedule the channel size per iteration, to reduce the number of iterations at the high BPP and fine-grained bit-rate control at the low BPP. To further enhance the efficiency, multiple network models for various channel sizes are combined into a single model using the slimmable network architecture. The experimental results show that the proposed method achieves comparable performance to the existing method with finer BPP adjustment, increases parameters by only 0.15% and reduces the average amount of computation by 40.4%.

6G research has been extensively conducted by individual organizations as well as pre-competitive joint research initiatives. One of the joint initiatives is the Hexa-X European 6G flagship project. This paper shares the up-to-date deliverables through which Hexa-X is envisioning the 6G era. The Hexa-X deliverables presented in this paper encompass the overall 6G vision, use cases and technical enablers. The latest deliverables on tenets of 6G architectural design and central pillars of technical enablers are presented. In conclusion, the authors encourage joint research and PoC collaboration with Japanese industry, academia and research initiatives for the potential technical enablers presented in this paper, aimed at global harmonization towards 6G standards.

A 2-D beam scanning array antenna fed by a compact 16-way 2-D beamforming network (BFN) designed in Broadside Coupled Stripline (BCS) is addressed. The proposed 16-way 2-D BFN is formed by interconnecting two groups of 4x4 Butler Matrix (BM). Each group is composed of four compact 4x4 BMs. The critical point of the design is to propose a simple and compact 4x4 BM without crossover in BCS to achieve a better transmission coefficient of the 16-way 2-D BFN with reduced size of merely 0.8λ0×0.8λ0×0.04λ0. Moreover, the complexity of the interface connection between the 2-D BFN and the 4x4 patch array antenna is reduced by using probe feeding. The 16-way 2-D BFN is able to produce the phase shift of ±45°, and ±135° in x- and y- directions. The 2-D BFN is easily integrated under the 4x4 patch array to form a 2-D phased array capable of switching 16 beams in both elevation and azimuth directions. The area of the proposed 2-D beam scanning array antenna module has been significantly reduced to 2λ0×2λ0×0.04λ0. A prototype operating in the frequency range of 4-6GHz is fabricated and measured to validate the concept. The measurement results agree well with the simulations.

A novel displacement sensor was proposed based on a frequency delta-sigma modulator (FDSM) employing a microwave oscillator. To demonstrate basic operation, we fabricated a stylus surface profiler using a cylindrical cavity resonator, where one end of the cavity is replaced by a thin metal diaphragm with a stylus probe tip. Good surface profile was successfully obtained with this device. A 10 nm depth trench was clearly observed together with a 10 µm trench in a single scan without gain control. This result clearly demonstrates an extremely wide dynamic range of the FDSM displacement sensors.

The art gallery problem is to find a set of guards who together can observe every point of the interior of a polygon P. We study a chromatic variant of the problem, where each guard is assigned one of k distinct colors. A chromatic guarding is said to be conflict-free if at least one of the colors seen by every point in P is unique (i.e., each point in P is seen by some guard whose color appears exactly once among the guards visible to that point). In this paper, we consider vertex-to-point guarding, where the guards are placed on vertices of P, and they observe every point of the interior of P. The vertex-to-point conflict-free chromatic art gallery problem is to find a colored-guard set such that (i) guards are placed on P's vertices, and (ii) any point in P can see a guard of a unique color among all the visible guards. In this paper, it is shown that determining whether there exists a conflict-free chromatic vertex-guard set for a polygon with holes is NP-hard when the number of colors is k=2.