An application of laser annealing process, which is used to form the P-type Base junction for high-performance low-voltage power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), is proposed. An equivalent shallow-junction structure for P-Base junction with uniform impurity distribution is achieved by adopting green laser annealing of pulsed mode. Higher impurity activation for the shallow junction has been achieved by the laser annealing of melted phase than by conventional RTA (Rapid Thermal Annealing) of solid phase. The application of the laser annealing technology in the fabrication process of Low-Voltage U-MOSFET is also examined.

An application of laser annealing process, which is used to form the shallow P-type Base junction for 20-V planar power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) is proposed. We demonstrated that the fabricated devices integrated with laser annealing process have superior electrical characteristics than those fabricated according to the standard process. Moreover, the threshold voltage variation of the devices applied by the new annealing process is effectively suppressed. This is due to that a uniform impurity distribution at the channel region is achieved by adopting laser annealing. Laser annealing technology can be applied as a reliable, effective, and advantageous process for the low-voltage power MOSFETs.

In LDMOS devices for high-voltage applications, there appears a notable fingerprint of current-voltage characteristics known as soft breakdown. Its mechanism is analyzed and modeled on LDMOS devices where a high resistive drift region exists. This analysis has revealed that the softness of breakdown, known as the expansion effect, withholding a run-away of current, is contributed by the flux of holes underneath the gate-overlap region originated by impact-ionization. The mechanism of the expansion effect is modeled and implemented into the compact model HiSIM_HV for circuit simulation. A good agreement between simulated characteristics and 2D-device simulation results is verified.

It is shown that it is feasible to apply 0.5-V 6-T SRAM cells in a 25-nm high-speed 1-Gb e-SRAM. In particular, for coping with rapidly reduced voltage margin as VDD is reduced, a boosted word-voltage scheme is first proposed. Second, Vt variations are reduced with repair techniques and nanoscale FD-MOSFETs to further widen the voltage margin. Third, a worst case design is developed, for the first time, to evaluate the cell. This design features a dynamic margin analysis and takes subthreshold current, temperature, and Vt variations and their combination in the cell into account. Fourth, the proposed scheme is evaluated by applying the worst-case design and a 25-nm planar FD-SOI MOSFET. It is consequently found that the scheme provides a wide margin and high speed even at 0.5 V. A 0.5-V high-speed 25-nm 1-Gb SRAM is thus feasible. Finally, to further improve the scheme, it is shown that it is necessary to use FinFETs and suppress and compensate process, voltage, and temperature variations in a chip and wafer.

We proposed a novel representation of the thermal noise for scaled MOSFETs by applying an extended van der Ziel's model. A comparison between the proposed representation and Pospieszalski's model is also performed. We confirmed that the representation of drain noise temperature, Td corresponds to the electron temperature in a gradual channel region.

The downscaling of CMOS technology has resulted in strong improvement in RF performance of bulk and SOI MOSFETs. In order to realize a low-noise RF circuit, a deeper understanding of the noise performance for MOSFETs is required. Thermal noise is the main noise source of the CMOS device for high frequency performance, and is dominated by the drain channel noise, induced gate noise, and their correlation noise. In this work, we measured the RF noise parameter (Fmin, Rn, Γ opt) of 45 nm node MOSFETs from 5 to 15 GHz and extracted noise sources and noise coefficients P, R, and C by using an extended van der Ziel's model. We found, for the first time, that correlation coefficient C decreases from positive to negative values when the gate length is reduced continuously with the gate length of sub-100 nm. We confirmed that Pucel's noise figure model, using noise coefficients P, R, and C, can be considered a good approximation even for sub-50 nm MOSFETs. We also discussed a scaling effect of the noise coefficients, especially the correlation noise coefficient C on the minimum noise figure.

A flexible noise de-embedding method for on-wafer microwave measurements of silicon MOSFETs is presented in this study. We use the open, short, and thru dummy structures to subtract the parasitic effects from the probe pads and interconnects of a fixtured MOS transistor. The thru standard are used to extract the interconnect parameters for subtracting the interconnect parasitics in gate, drain, and source terminals of the MOSFET. The parasitics of the dangling leg in the source terminal are also modeled and taken into account in the noise de-embedding procedure. The MOS transistors and de-embedding dummy structures were fabricated in a standard CMOS process and characterized up to 20 GHz. Compared with the conventional de-embedding methods, the proposed technique is accurate and area-efficient.

We have fabricated enhancement-mode n-channel GaN MOSFETs with overlap gate structure on a p-GaN using thick HfO2 as a gate insulator. The maximum transconductance of 23 mS/mm which is 4 times larger, to our knowledge, than the best-reported value of the normally-off GaN MOSFETs with SiO2 gate oxide has been obtained.

The analysis of multiband quantum transport simulation in double-gate metal oxide semiconductor field effects transistors (DG-MOSFETs) is performed based on a non-equilibrium Green's function (NEGF) formalism coupled self-consistently with the Poisson equation. The empirical sp3s* tight binding approximation (TBA) with nearest neighbor coupling is employed to obtain a realistic multiband structure. The effects of non-parabolic bandstructure as well as anisotropic features of Si are studied and analyzed. As a result, it is found that the multiband simulation results on potential and current profiles show significant differences, especially in higher applied bias, from those of conventional effective mass model.

The new design with minimum loop inductance suitable for the measurements at high frequencies with substrate bias is described. These test structures allow characterizing 4-terminal MOSFETs with a standard two-port Network Analyzer. The high-frequency behavior of bulk effect in MOSFETs is studied at different bias conditions for a 0.18 µm RF CMOS technology. The BSIM3 extension RF MOSFET modeling with bulk effect is verified and analyzed from two-port Y-parameter results. The result of RF NMOSFET shows that a good accuracy of the 4-terminal RF MOSFET modeling is achieved.

In this paper we apply a parallel adaptive solution algorithm to simulate nanoscale double-gate metal-oxide-semiconductor field effect transistors (MOSFETs) on a personal computer (PC)-based Linux cluster with the message passing interface (MPI) libraries. Based on a posteriori error estimation, the triangular mesh generation, the adaptive finite volume method, the monotone iterative method, and the parallel domain decomposition algorithm, a set of two-dimensional quantum correction hydrodynamic (HD) equations is solved numerically on our constructed cluster system. This parallel adaptive simulation methodology with 1-irregular mesh was successfully developed and applied to deep-submicron semiconductor device simulation in our recent work. A 10 nm n-type double-gate MOSFET is simulated with the developed parallel adaptive simulator. In terms of physical quantities and refined adaptive mesh, simulation results demonstrate very good accuracy and computational efficiency. Benchmark results, such as load-balancing, speedup, and parallel efficiency are achieved and exhibit excellent parallel performance. On a 16 nodes PC-based Linux cluster, the maximum difference among CPUs is less than 6%. A 12.8 times speedup and 80% parallel efficiency are simultaneously attained with respect to different simulation cases.

The validity and capability of an iterative coupling scheme between single-particle frozen-field Monte Carlo simulations and nonlinear Poisson solutions for achieving self-consistency is investigated. For this purpose, a realistic 0.1 µm lightly-doped-drain (LDD) n-MOSFET with a maximum doping level of about 2.5 1020 cm-3 is simulated. It is found that taking the drift-diffusion (DD) or the hydrodynamic (HD) model as initial simulation leads to the same Monte Carlo result for the drain current. This shows that different electron densities taken either from a DD or a HD simulation in the bulk region, which is never visited by Monte Carlo electrons, have a negligible influence on the solution of the Poisson equation. For the device investigated about ten iterations are necessary to reach the stationary state after which gathering of cumulative averages can begin. Together with the absence of stability problems at high doping levels this makes the self-consistent single-particle approach (SPARTA) a robust and efficient method for the simulation of nanoscale MOSFETs where quasi-ballistic transport is crucial for the on-current.

We developed a method for analysis of boron penetration and gate depletion using N+ and P+ dual-gate PMOSFETs. An N+ gate PMOSFETs, which is immune to boron penetration and gate depletion, exhibited the threshold voltage shifts and fluctuation in P+ gate PMOSFETs fabricated using identical N- substrates. We showed the importance of Vth fluctuation analysis and found that the Vth fluctuation in N+ gate PMOSFETs was negligible, but, the Vth fluctuation in P+ gate PMOSFETs was significant, indicating that the Vth fluctuation in P+ gate PMOSFETs was dominated by boron penetration. It was also shown, for the first time, that boron penetration occurred with gate depletion, and gate depletion must be very strong to suppress boron penetration. The dual-gate PMOSFET method makes it possible to select high-performance G-bit DRAM fabrication processes that are robust against Vth fluctuation.

The gate oxide of sub-0.1 µm MOSFETs channel length is expected to be reduced beyond 3 nm in spite of an increasing direct tunneling gate current. As tunnel injection modeling into SiO2 is expected to depend on the electron transport model adopted for the device description, a critical comparison is made in this paper between gate currents obtained from simulators based on Drift-Diffusion, Energy-Balance, and Monte Carlo models. The studied device is a 0.07 µm channel length n-MOSFET with 1.5 nm thick gate oxide. It is shown that positive drain voltage is responsible for two opposite effects on DT leakage: a carrier heating and a potential barrier hardening along the channel. It is proved by a careful study of Monte Carlo microscopic quantities that, contrary to what holds for thicker gate oxide transistors, the balance is favorable to the potential barrier effect. Injection into SiO2 is then dominated by near-thermal carriers injected at the channel beginning. For this reason, the gate current decreases when increasing the drain bias, with the maximum leakage obtained for (Vgs=Vdd, Vds=0), and a correct agreement is obtained between the Drift-Diffusion, Energy-Balance, and Monte Carlo approaches of gate current calculation, in spite of very different physical descriptions of transport at the microscopic level.

A comprehensive analysis methodology allowing investigation of the RF performance of Si and strained Si:SiGe MOSFETs is presented. It is based on transient ensemble Monte Carlo simulation which correctly describes device transport, and employs a finite element solver to account for complex device geometries. Transfer characteristics and figures of merit for a number of existing and proposed RF MOSFETs are discussed.

Heavy-ion-induced soft errors (single event upset) in submicron silicon-on-insulator (SOI) MOSFETs under space environmental conditions are studied over the temperature range of 100-400 K using three-dimensional device simulator with full-temperature models. The temperature dependence of the drain collected charge is examined in detail when a heavy-ion strikes the gate center perpendicularly. At very low temperatures, SOI MOSFETs have very high immunity to the heavy-ion-induced soft errors. In particular, alpha-particle-induced soft errors hardly occur at temperatures below 200 K. As the temperature increases, the collected charge shows a marked rate of increase. The problem of single event upset in SOI MOSFETs becomes more serious with increasing working temperature. This is because the induced bipolar mechanism is a main factor to cause charge collection in SOI MOSFETs and the bipolar current increases exponentially with increasing temperature. At room and high temperatures, the drain collected charge is strongly dependent on channel length and SOI film thickness.

Surface-channel PMOSFETs are suitable for use in the quarter micron CMOS devices. For surface-channel PMOSFETs with p+ poly-Si gates, boron penetration and hot-carrier effects were investigated. When the annealing temperature is higher and the gate oxide is thinner, a larger threshold voltage shift was observed for p+ poly-Si PMOSFETs, because of boron penetration. Furthermore, PMOSFETs with BF2-implanted gates cause larger boron penetration than those with Boron-implanted gates. Howerer, the PMOSFET lifetime, determined by hot-carrier reliability, does not depend on the degree of boron penetration. Instead, it depends on doping species, that is, BF2 and Boron. PMOSFETs with BF2-implanted gates have about 100 times longer lifetime than those with Boron-implanted gates. The main reason for the longer lifetime of BF2-doped PMOSFETs is the incorporation of fluorine in the gate oxide of the PMOSFET with the BF2-implanted gate, resulting in the smaller electron trapping in the gate oxide. The maximun allowed supply voltage,based on the hot-carrier reliability, is higher than4V for sub-half micron PMOSFETs with BF2- or Boron-implanted poly Si gates.

Leakage enhancement after an ESD event has been analyzed for output buffer LDD MOSFETs. The HBM ESD failure threshold for the LDD MOSFETs is only 200-300 V and the failure is the leakage enhancement of the off-state MOSFETs called as "soft breakdown" leakage. This leakage enhancement is supposed to be caused by trapped electrons in the gate oxide and/or creation of interface states at the gate overlapped drain region due to snap-back stress during the ESD event. The mechanism of the lekage can be explained by band-to-band and/or interface state-to-band tunneling of electrons. The improvement of the HBM ESD threshold has been also evaluated by using two types of drain engineering which are additional arsenic implantation for the output LDD MOSFETs and "offset" gate MOSFET as a protection circuit for the output pins. By using these drain engineering, the threshold can be improved to more than 2000 V.

In this paper, a "hydrodynamic" version of the three-dimensional code HFIELDS-3D is used to achieve a detailed knowledge on the distribution of the substrate current inside a recessed-oxide MOSFET. The physical model features a temperature-dependent formulation of the impact-ionization rate, allowing non-local effects to be accounted for. The discretization strategy relies on the Box Integration scheme and uses suitable generalizations of the Scharfetter-Gummel technique for the energy-balance equation. The simulation results show that the narrow-channel effect has a different impact on drain and substrate currents. Further three-dimensional effects, such as the extra heating of the carriers at the channel edge, are demonstrated.