This paper describes 3-GHz and 7-GHz tunable-inductance LC-tank voltage-controlled oscillators (VCOs) implemented in 0.18-µm CMOS technology. Unlike the traditional tuning method by a varactor, a tunable inductor is employed in the VCO by using a transformer to compensate for the energy loss. The VCO facilitates the tuning frequency and low noise of the output signals, together with a variable inductor which satisfies both criteria. The 3-GHz VCO using a symmetry transformer provides the tuning range of 2.85 to 3.12 GHz at 1-V supply. The power consumption is 4.8 mW while the measured phase noise is -126 dBc/Hz at 1-MHz offset from a 2.85-GHz carrier. A small-area stacked transformer is employed in the 7-GHz VCO, which achieves a tuning range of 6.59 to 7.02 GHz and measured phase noise of -114 dBc/Hz at 1-MHz offset from a 6.59-GHz carrier while consuming 9 mW from a 1.2-V supply.

In this paper, we report a manufacturable InP DHBT technology, suitable for medium scale mixed-signal and monolithic microwave integrated circuits. The InGaAs/InP DHBTs were grown by MBE and fabricated using conventional process techniques. Devices with an emitter junction area of 4.8 µm2 exhibited peak cutoff frequency (fT) and maximum oscillation frequency (fMAX) values of 265 and 305 GHz, respectively, and a breakdown voltage (BVCEo) of over 5 V. Using this technology, a set of mixed-signal IC building blocks for ≥ 80 Gbit/s fibre optical links, including distributed amplifiers (DA), voltage controlled oscillators (VCO), and multiplexers (MUX), have been successfully fabricated and operated at 80 Gbit/s and beyond.

A VCO for multi-standard transceiver should operate in wide-tuning range, while providing low-phase noise quadrature outputs with low power consumption. In this paper, a multi-standard CMOS LC QVCO is designed utilizing reconfigurable LC tank and low power low phase noise quadrature generation method. Designed in 0.18 µm CMOS technology, the VCO achieved very wide tuning characteristics in two separate bands with low power consumption.

A simple low power low phase noise LC QVCO (Quadrature Voltage Controlled Oscillator) topology is proposed. The topology minimizes phase noise by eliminating the contributions from the tail current source and coupling transistors. With no more than 3.36 mW power consumption from a 1.2 V power supply, the VCO achieves -124 dBc/Hz phase noise performance at 1 MHz offset from the 2.85 GHz carrier frequency.

In deep sub-micrometer CMOS process, owing to the thin gate oxide and small subthreshold voltage, the leakage current becomes more and more serious. The leakage current has made the impact on phase-locked loops (PLLs). In this paper, the compensation circuits are presented to reduce the leakage current on the charge pump circuit and the MOS capacitor as the loop filter. The proposed circuit has been fabricated in 0.13-µm CMOS process. The power consumption is 3 mW and the die area is 0.270.3 mm2.

A low-noise, low-power 10-GHz CMOS VCO was developed using cost-effective 0.18-µm CMOS technology. A complementary cross-coupled topology was employed to decrease the power dissipation and phase noise. The fabricated VCO demonstrates a low phase noise of -106 dBc/Hz at an offset frequency of 1 MHz and a low power dissipation of 4.4 mW.

It is often observed that the operation of the digitally controlled dc-dc power converter becomes unstable when the relatively large integral coefficient is used to extend the regulation range of the output voltage to handle variations in the input voltage and load. This paper presents a novel digital controller with static model reference for switching dc-dc power converters to improve the performance characteristics and discusses its design-oriented analysis in the steady-state characteristics. It is clarified theoretically and experimentally that using the static model reference, the wide regulation range of the output voltage to handle variations in the input voltage and load current can be achieved with the appropriate small integral coefficient in the digital P-I-D controller. Therefore, since the integral coefficient is selected to cover the maximum instantaneous variation value of the static reference model, the integral coefficient is small and the operation is always stable.

A fully integrated voltage controlled oscillator (VCO) MMIC for millimeter-wave applications has been designed and implemented in InGaP/GaAs heterojunction bipolar transistor (HBT) technology. To achieve a fully integrated VCO, a base-emitter diode is employed as the tuning varactor, and microstrip lines are employed for the transmission lines. The fabricated VCO MMIC chip size is 0.86 mm 1.34 mm and delivers an output power of 5.1 dBm at 28.7 GHz and a free-running phase noise of -118 dBc/Hz at 1 MHz offset. The dc current consumption is only 20 mA.

A frequency drift of open-loop PLL is an issue for the direct-modulation applications such as Bluetooth transceiver. The drift mainly comes from a temperature variation of VCO during the transmission operation. In this paper, we propose the optimum location of the VCO, considering the temperature gradient through the whole-chip thermal analysis. Moreover, a novel temperature-compensated VCO, employing a new biasing scheme, is proposed. The combination of these two techniques enables the power reduction of the transmitter by 33% without sacrificing the performance.

This paper presents a novel wide tuning range CMOS Voltage Controlled Oscillator (VCO). VCO uses an on-chip variable inductor as an additional variable element to extend the tuning range of VCO. The fabricated variable inductor achieves the variable range of 35%. The VCO was fabricated using 0.35 µm standard CMOS process, and can be tuned continuously from 2.13 GHz to 3.28 GHz (tuning range of 38%) without degradation of phase noise. Wide tunable LC-VCO using a variable inductor is one of the key circuits for reconfigurable RF circuit.

A digitally controlled dc-dc power converter is useful to dc power supply systems for telecommunications and data communications systems that require high reliability and high performance. This paper presents a design criterion and output characteristics of 1 MHz high-speed digitally controlled dc-dc converter using a voltage controlled oscillator (VCO) as an analog to digital signal converter in the digital control circuit. As a result, it is revealed theoretically and experimentally that the proposed 1 MHz high-speed digitally controlled dc-dc converter has excellent static and dynamic characteristics. The adjustability of output voltage is less than 10 mV and there is no steady-state error within the integral controlled regulation range. Also, the overshoot is suppressed enough within 0.1 V and the transient time is very short.

An adaptive 4-state phase-frequency detector (PFD) for clock and data recovery (CDR) PLL of non return to zero (NRZ) data is presented. The PLL achieves false-lock free operation with rapid frequency-capture and wide bit-rate-capture range. The variable bit rate operation is achieved by adaptive delay control of data delay. Circuitry and overall architecture are described in detail. A z-Domain analysis is also presented.

We have proposed a new low-IF transceiver architecture to simultaneously achieve both a small chip area and good minimum input sensitivity. The distinctive point of the receiver architecture is that we replace the complicated high-order analog filter for channel selection with the combination of a simple low-order analog filter and a sharp digital band-pass filter. We also proposed a high-speed convergence AGC (automatic gain controller) and a demodulation block to realize the proposed digital architecture. For the transceiver, we further reduce the chip area by applying a new form of direct modulation for the VCO. Since conventional VCO direct modulation tends to suffer from variation of the modulation index with frequency, we have developed a new compensation technique that minimizes this variation, and designed the low-phase noise VCO with a new biasing method to achieve large PSRR (power-supply rejection ratio) for oscillation frequency. The test chip was fabricated in 0.35-µm BiCMOS. The chip size was 3 3 mm2; this very small area was realized by the advantages of the proposed transceiver architecture. The transceiver also achieved good minimum input sensitivity of -85 dBm and showed interference performance that satisfied the requirements of the Bluetooth standard.

A fully integrated RF front-end for W-CDMA applications including a low noise amplifier, a down conversion mixer, a digitally programmable gain amplifier, an on-chip VCO, and a fractional-N frequency synthesizer is designed using a 0.35-µm CMOS process. A multi-stage ring shaped on-chip LC-VCO exhibiting bandpass characteristics overcomes the limitation of low-Q components in the tank circuits and improves the phase noise performance. The measured phase noise of the on-chip VCO is -134 dBc/Hz at 1 MHz offset. The receiver RF front-end achieves a NF of 3.5 dB, an IIP3 of -16 dBm, and a maximum gain of 80 dB. The receiver consumes 52 mA with a 3-V supply and occupies only 2 mm2 die area with minimal external components.

The fully integrated LC voltage controlled oscillator by 0.35 µm CMOS technology is demonstrated. It has 2 GHz oscillation frequency, 23.58 mW power consumption under 3 V biased and 9.1% frequency tuning. The layout optimization method of inductor to increase quality factor and also to reduce phase noise is used. A general method is proposed which is capable of making an effective prediction of F, device excess noise number, and acquiring the phase noise of oscillators accurately. From this proposed method, the low phase noise by calculation is attained. The phase noise of measured value which shows good match with calculating data is about -115.5 dBc/Hz at off set frequency 600 kHz.

The low phase noise, low supply voltage 1.3 GHz CMOS VCO has been realized by 0.25 µm standard CMOS technology without any trimming and any tuning. The phase noise characteristics of -109 dBc/Hz and -123 dBc/Hz at 100 kHz offset and 500 kHz offset were achieved from carrier, respectively, with 1.3 GHz oscillation frequency at 1.4 V supply voltage. The performance of 1.4 V supply voltage phase noise was superior to that of 2.0 V supply voltage phase noise due to low output impedance current source. The tuning ranges of 13.3%, 16.6%, and 20.1% for 1.4 V, 1.8 V, and 2.0 V supply voltage were achieved, respectively. The amplifier consisted of one pair of PMOS differential stage with large gate length NMOS current source to realize low supply voltage operation and to avoid flicker noise contribution for phase noise. The on-chip spiral inductor consisted of three terminals arranged in a special shape to obtain high Q and small chip area. The power dissipation of this VCO was 22.4 mW without buffer amplifier.

We introduce a PLL (Phase Locked Loop) for low-power and a low supply voltage applications. Because the PLL is a key device of the system LSIs used in mobile terminals, it is very important that PLLs operate under a low supply voltage to reduce power consumption. We investigate the limitations of the conventional VCO that we proposed in Ref.[5] and propose a modified VCO that uses common load transistors. Furthermore, we propose a charge pump that uses a dynamic output stage op-amp and a stability technique for the CMOS process, and it does not contain any special resistors. The results of an evaluation of a device fabricated using a standard logic 0.18-µm CMOS process demonstrated that the proposed PLL operated above 1.0 GHz with a 1.2-V supply voltage and it produced only a small amount of jitter that was lower than 78 psp-p.

Problems concerning a phase-locked loop (PLL) fabricated by a deep-sub-micron process were investigated, and a high-speed self-calibration technique for tuning a voltage-controlled oscillator (VCO) frequency range automatically was developed. The self-calibration technique can measure VCO frequency in short time by comparing intervals between a PLL reference and a VCO output. Furthermore, a loop-filter bypassing method was also used to change the calibration frequency in short time. At 0.7 V and 200 MHz, the prototype PLL has a calibration time of 1.4 µs and a total settling time of 10 µs, which are adequate for microprocessor applications. Moreover, the PLL has a cycle-to-cycle jitter of 142 ps and a power consumption of 470 µW.

Fully integrated VCO using the "turbo-charger" technique to improve phase noise characteristics is presented. The phase noise degradation of relatively lower oscillation frequency in tuning range was caused by oscillation amplitude lowering due to large total capacitance. On the other hand, the phase noise degradation of relatively higher frequency in tuning range was caused by excess current noise. A new "turbo-charger" circuit increased operation current to obtain sufficient transconductance of amplifier when oscillation frequency was lower to improve phase noise characteristics. The phase noise of VCO employing this technique was extremely low and stable, below -140-dBc/Hz at 3-MHz offset from oscillation frequency, in wide oscillation frequency range, approximately 200-MHz for 1200-MHz oscillation. This VCO was operated with 5.8-7.4-mA current consumption at 3-V supply voltage. The manufacturing process was 0.6-µm SiGe BiCMOS.

This paper describes low-power and low-voltage analog circuit techniques applicable to deep sub-micron LSIs in baseband and RF signal processing. The trends indicate that reductions in the supply voltage are inevitable, that power dissipation will not become sufficiently low, and that performance will improve continuously. Some circuit techniques currently being used to achieve these goals are reviewed. Next, three trial approaches are introduced. The first of these is a 1 V operational video-speed CMOS sample-and-hold IC. The second is a 1 V operational high-frequency CMOS VCO circuit. Finally, a step-down DC-DC converter IC with a 1 V output and a greater than 80% power efficiency is introduced. These approaches prove that the low-power and low-voltage operation of analog circuits can be realized without sacrificing performance.