A Real-time Capacitor Compensation (RCC) scheme is proposed for low power and continuous communication in the wearable inductive coupling transceiver. Since inductance values of wearable inductor vary dynamically with deterioration of its communication characteristics, the inductance value is monitored and its resonance frequency is adjusted by additive parallel/serial capacitors in real time. RLC Bridge for detection of the inductance variations and the Dual-edge Sampling Comparator for recognition of the variance direction are proposed. It is implemented in a 0.18 µm CMOS technology, and it occupies a 12.7 mm2 chip area. The proposed transceiver consumes only 426.6 µW at 4 Mbps data rate. The compensation time takes 4.78 µs, including 3 µs of detection and 1.78 µs for compensation process in worst case.

In an early design stage of LSI designing, finding out the proper parameters for power planning is important from the viewpoint of cost minimization. In this paper, we present simple analytical formulas which are used to obtain the initial parameters close to the proper power distribution networks in the early design stage. The formulas for estimating static and pseudo-dynamic voltage drops (IR-drops) are derived by the response surface method (RSM). By making the formulas once, they can be used for the general power planning for the power-grid style in any process technology.

This paper shows experimental results of packet error rates (PERs) in wireless-LAN mounted printed circuit boards and gives a discussion on a mechanism of electromagnetic noise coupling that affects the PER. We utilized the amplitude probability distribution to investigate the noise coupling channel. We measured the magnetic near-field distribution to obtain information about noise sources. Based on measurement results, we also performed parallel plate resonance analysis to find out electromagnetic interference antennas. We confirmed that noise radiates from a power supply system of a digital circuit and its coupling to a receiving antenna causes an increase of the PER.

This paper provides an investigation of power distribution network (PDN) performance by a full-wave prediction tool and by experimental measurements. A set of six real boards characterized by increasing complexity is considered in order to establish a solid base for behaviour understanding of printed circuit boards. How the growing complexity impacts on the board performance is investigated by measurements and by simulations. Strengths and weakness of PDN modeling by the full-wave software tool Microwave Studio are highlighted and discussed.

We investigated the effect of a high-speed power line communication (PLC) signal induced into a very high-speed digital subscriber line (VDSL) system by conductive coupling based on a network model. Four electronic devices with AC mains and telecommunication ports were modeled using a 4-port network, and the parameters of the network were obtained from measuring impedance and transmission loss. We evaluated the decoupling factor from the mains port to the telecommunication port of a VDSL modem using these parameters for the four electric and electronic devices. The results indicate that the mean value of the decoupling factor for the differential and common mode signals were more than 88 and 62 dB, respectively, in the frequency range of a PLC system. Taking the following parameters into consideration; decoupling factor Ld, the average transmission signal powers of VDSL and PLC, desired and undesired (DU) ratio, and transmission loss of a typical 300-m-long indoor telecommunication line, the VDSL system cannot be disturbed by the PLC signal induced into the VDSL modem from the AC mains port in normal installation.

An arbitrary noise generator (ANG) is based on time-series charging of divided parasitic capacitance (TSDPC) and emulates power supply noise generation in a CMOS digital circuit. A prototype ANG incorporates an array of 32 x 32 6-bit TSDPC cells along with a 128-word vector memory and occupies 2 x 2 mm2 in a 65 nm 1.2 V CMOS technology. Digital noise emulation of functional logic cores such as register arrays is demonstrated with chip-level waveform monitoring at power supply, ground, as well as substrate nodes.

A boosted bit line program scheme is proposed for low operating voltage in the multi-level-cell (MLC) NAND flash memory. Our BL to BL boosting scheme, which uses the BL coupling capacitance, is applied to achieve a higher channel potential than is possible with Vcc, so that the Vpass window margin is improved by up to 59% in 40 nm MLC NAND flash memory with 2.7 V Vcc. In the case of 1.8 V Vcc, the margin of the proposed scheme is 12% higher than one of the conventional schemes at 2.7 V Vcc.

Capacitance charging modeling efficiently captures power supply currents in dynamic operations of a CMOS digital circuit and accurately expresses their interaction with on- and off-chip impedance networks. Derivation of such models is generally defined for combinational and sequential logic functions. Simulated substrate and power noises due to sequential logic operation show clear dependency on the size of circuits as well as the internal activity of logic gates. Furthermore, it is experimentally found that the inclusion of impedance networks of a silicon substrate, a package, and an evaluation board, is substantially effective to improve the accuracy of noise analysis. Quantitative correlation among simulation with on-chip noise measurements is demonstrated in a 90-nm 1.2-V CMOS technology.

A wireless power link utilizing inductive coupling is developed between stacked chips. In this paper, we discuss inductor layout optimization and rectifier circuit design. The inductive-coupling power link is analyzed using simple equivalent circuit models. On the basis of the analytic models, the inductor size is minimized for the given required power on the receiver chip. Two kinds of full-wave rectifiers are discussed and compared. Various low-power circuit design techniques for rectifiers are employed to decrease the substrate leakage current, reduce the possibility of latch-up, and improve the power transmission efficiency and the high-frequency performance of the rectifier block. Test chips are fabricated in a 0.18 µm CMOS process. With a pair of 700700 µm2 on-chip inductors, the test chips achieve 10% peak efficiency and 36 mW power transmission. Compared with the previous work the received power is 13 times larger for the same inductor size .

In this paper, an indoor repeater antenna with high isolation for WCDMA application is proposed. The designed repeater has very small separation of 20 mm between the donor and server antennas. The antenna has two resonance frequencies to cover the WCDMA band from 1.92 GHz to 2.17 GHz. The fabricated antenna has VSWR below 1.5, gain over 8 dBi, and isolation between server and donor antennas less than -80 dB in the WCDMA band.

A filter integrated antenna configuration that suppresses the coupling signal from the transmitter (Tx) to receiver (Rx) base station antenna is investigated. We propose an aperture coupled patch antenna with multiple trapezoidal elements installed on the substrate of the Rx antenna between the radiation and feed layers in order to increase the bandwidth in the Rx band while maintaining low mutual coupling in the Tx band. The mutual coupling characteristics and the fractional bandwidth of the Rx antenna are presented as functions of the shape and width of the trapezoidal elements.

A 2.45-GHz-band small passive radio-frequency identification (RFID) tag consists of a small loop antenna and chip, and its size is several millimeters. Because of the tag's poor impedance-matching characteristic and radiation efficiency, an ordinary reader has difficulty reading it. We propose a new technique for reading the tag that involves installing a square half-wavelength meander-line conductor on the reader as an adapter and placing the adapter in the vicinity of the tag, and verify the effectiveness of the technique by simulation and experiment. Moreover, characteristics of simultaneous read of the small RFID tags by the proposed reading technique are revealed by simulation and experimental results.

This paper presents the analysis and design of a reflection-cancelling transverse slot-pair array antenna with baffles by using the Spectrum of Two-Dimensional Solutions (S2DS) method. For the transverse slot array, the slot spacings with more than one free-space wavelength cause the grating-lobes. The baffles suppress the grating-lobes effectively. A one-dimensional slot array is extracted from the 2D array with in-phase excitation by assuming periodicity in the transversal direction. The uniform excitation over the finite array is synthesized iteratively to demonstrate the fast and accurate results by S2DS. A unit design model with the baffles is introduced to determine the initial parameters of the slot-pairs, which greatly accelerate the iterations process. Experiments at 25.3 GHz demonstrate the suppression of the grating lobes to the level less than -20.0 dB and also the good uniformity of the aperture field distribution.

In this paper, the feasibility of composite right/left-handed transmission lines for realizing proximity coupled interconnects is reported. The proposed interconnects' resonant length can be miniaturized due to the zeroth order resonance supported by a composite right/left-handed transmission line resonator. In addition, the proposed interconnects can achieve broadside coupling because the zeroth order resonance occurs in the fast-wave region. Simulated and measured electric field distributions are shown to explain the broadside coupling phenomenon. To validate the arbitrary size and broadside coupling of the proposed interconnects, simulated and measured transmission characteristics are presented. The results show that low insertion loss can be achieved by using single and double broadside coupling between interconnects.

Dual-band chip antennas usually have a narrow bandwidth in the first resonance frequency band due to an inter-coupling capacitance. In order to analyze the effect of the inter-coupling capacitance, an equivalent circuit of an antenna with a branch radiator is considered in this paper. Based on the equivalent circuit model, it is found that the inter-coupling capacitance reduces impedance bandwidth. This paper proposes a gap feeding method to alleviate the effect of the inter-coupling capacitance and explains it using an equivalent circuit.

A fully integrated CMOS wideband Low Noise Amplifier (LNA) operating over 2.3-7 GHz is designed and fabricated using a 0.18 µm CMOS process. The proposed structure is a common source-common source (CS-CS) cascode amplifier with a coupling capacitor. It realizes both low voltage drop at load resistor (Rload) and high gain over 2.3-7 GHz with simultaneous noise and input matching and low power consumption. This paper presents the proposed design technique of a wideband LNA, and verifies its performance by simulation and measurement. This wideband LNA achieves an average gain (S21) of 16.5 (dB), an input return loss (S11) less than -8 dB, a noise figure (NF) of 3.4-6.7 dB, and a third order input interception point (IIP3) of -7.5-3 dBm at 2.3-7 GHz with power consumption of 10.8 mW under 1.8 V VDD.

A decoupling device that can be used for millimeter-waves is required to reduce the effect of the parasitic impedance at the grounded terminal of the power supply. The frequently used decoupling capacitor is not appropriate because it has self-resonance characteristics due to the parasitic inductance. To realize resonance-free wideband decoupling, a high-attenuation power line (HAPL) is proposed. The HAPL has constant input impedance equal to its characteristic impedance, and has constant isolation unaffected by the phase constant and the terminal impedance. Furthermore, the HAPL contributes to the area reduction of the millimeter-wave circuits because it simultaneously acts as a power line and a decoupling device. The HAPL was fabricated with a 90 nm CMOS process. The proposed structure increases parallel conductance and capacitance using an MOS capacitor and its equivalent series resistance, therefore realizing high attenuation and resonance suppression while reducing characteristic impedance. With a 200-µm-long HAPL, Re (S11) was less than -0.9 and isolation was more than 25 dB, from 50 GHz to 90 GHz including unlicensed bands used for wireless personal area network and radar application. As a result, power-supply network with wideband decoupling is realized by simply connecting power-supply pads and feeding point via the HAPL. The HAPL is expected to contribute to the simple and compact design of millimeter-wave circuits.

Testing and diagnosis techniques play a key role in the advance of semiconductor memory technology. The challenge of failure detection has created intensive investigation on efficient testing and diagnosis algorithm for better fault coverage and diagnostic resolution. At present, March test algorithm is used to detect and diagnose all faults related to Random Access Memories. However, the test and diagnosis process are mainly done manually. Due to this, a systematic approach for developing and evaluating memory test algorithm is required. This work is focused on incorporating the March based test algorithm using a software simulator tool for implementing a fast and systematic memory testing algorithm. The simulator allows a user through a GUI to select a March based test algorithm depending on the desired fault coverage and diagnostic resolution. Experimental results show that using the simulator for testing is more efficient than that of the traditional testing algorithm. This new simulator makes it possible for a detailed list of stuck-at faults, transition faults and coupling faults covered by each algorithm and its percentage to be displayed after a set of test algorithms has been chosen. The percentage of diagnostic resolution is also displayed. This proves that the simulator reduces the trade-off between test time, fault coverage and diagnostic resolution. Moreover, the chosen algorithm can be applied to incorporate with memory built-in self-test and diagnosis, to have a better fault coverage and diagnostic resolution. Universities and industry involved in memory Built-in-Self test, Built-in-Self repair and Built-in-Self diagnose will benefit by saving a few years on researching an efficient algorithm to be implemented in their designs.

Complex bandpass ΔΣAD modulators can provide superior performance to a pair of real bandpass ΔΣAD modulators of the same order. They process just input I and Q signals, not image signals, and AD conversion can be realized with low power dissipation, so that they are desirable for such low-IF receiver applications. This paper proposes a new architecture for complex bandpass Δ ΣAD modulators with cross-noise-coupled topology, which effectively raises the order of the complex modulator and achieves higher SQNDR (Signal to Quantization Noise and Distortion Ratio) with low power dissipation. By providing the cross-coupled quantization noise injection to internal I and Q paths, noise coupling between two quantizers can be realized in complex form, which enhances the order of noise shaping in complex domain, and provides a higher-order NTF using a lower-order loop filter in the complex ΔΣAD modulator. Proposed higher-order modulator can be realized just by adding some passive capacitors and switches, the additional integrator circuit composed of an operational amplifier is not necessary, and the performance of the complex modulator can be effectively raised without more power dissipation. We have performed simulation with MATLAB to verify the effectiveness of the proposed architecture. The simulation results show that the proposed architecture can achieve the realization of higher-order enhancement, and improve SQNDR of the complex bandpass ΔΣAD modulator.

The high-speed and low-power system LSIs in recent years have crucial need for managing power supply noise so that it might not substantially affect the circuit functionality and performance. The decoupling capacitance is known as an effective measure for suppressing the power supply noise. In this paper, we propose a design methodology for decoupling capacitance budgeting, in which the decoupling capacitance is distributed appropriately over the LSI chip area in order to suppress the power supply noise of each local region. For efficient budgeting, we introduced a new concept of power-capacitance ratio, which is the ratio of power dissipation to capacitance. The proposed method first performs a simplified power supply noise analysis by using a lumped circuit model to determine the total required on-chip capacitance, and calculate the power-capacitance ratio. Then, in the layout design phase, the decoupling capacitance budgeting is performed by using the above power-capacitance ratio as a guideline. The effectiveness of the proposed method was verified by using SPICE simulations on example chip models of 90 nm technology node. The verification results show that, even for a chip with very wide on-chip variation in power density, the proposed method can suppress the power supply noise of each local region effectively.