A daisy chain of current-driven transmitters in inductive-coupling complementary metal oxide semiconductor (CMOS) links is presented. Transmitter power can be reduced since current is reused by multiple transmitters. Eight transceivers are arranged with a pitch of 20 µm in 0.18 µm CMOS. Transmitter power is reduced by 35% without sacrificing either the data rate (1 Gb/s/ch) or BER (<10-12) by using a 4-transmitter daisy chain. A coding technique for efficient use of daisy chain transmitters is also proposed. With the proposed coding technique, additional power reduction can be achieved.

A new current reused quadrature voltage controlled oscillator (QVCO) is proposed and implemented using UMC 0.18 µm CMOS 1P6M process. The proposed circuit topology is made up two low voltage LC-tank VCOs, where the QVCO is obtained using the transformer coupling and current reuse technique. At 1.8 V supply voltage, the phase noise of the VCO is -117.13 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 2.18 GHz, the core power consumption is 4.14 mW, the total power consumption is 6.48 mW and tuning range is about 160 MHz.

Substrate-coupling equivalent circuits can be derived for arbitrary isolation structures by F-matrix computation. The derived netlist represents a unified impedance network among multiple sites on a chip surface as well as internal nodes of isolation structures and can be applied with SPICE simulation to evaluate isolation strengths. Geometry dependency of isolation attributes to layout parameters such as area, width, and location distance. On the other hand, structural dependency arises from vertical impurity concentration specific to p+/n+ diffusion and deep n-well. Simulation-based prototyping of isolation structures can include all these dependences and strongly helps establish an isolation strategy against high-frequency substrate coupling in a given technology. The analysis of isolation strength provided by p+/n+ guard ring, deep n-well guard ring as well as deep n-well pocket well explains S21 measurements performed on high-frequency test structures targeting 5 GHz bandwidth, that was formed in a 0.25-µm CMOS high frequency.

We propose a wave analysis method for probe-fed Radial Line Planar Antennas (RLPAs) which yields an approximate solution for the aperture field distribution and scattering by loaded probes. Damping of electric power in the radial line due to radiation by antenna elements is included. The method can accommodate the effect of all conductors, including the terminating wall, by introducing the concept of equivalent posts. We have found good correspondence between the measured and calculated values of the aperture field distribution. The proposed method is effective for general geometries of probe-fed RLPAs.

This letter presents mutual coupling reduction in an E-plane arranged microstrip patch array fed by a triplate waveguide. Five mushroom-like electromagnetic band-gap (EBG) elements arranged in one column are embedded both between two radiating patches and between the feeding lines for suppression of the surface wave and the parallel plate mode, respectively. Validity of the proposed EBG elements is confirmed by the measurement.

Sleep transistors such as MTCMOS and SCCMOS drastically reduce leakage current, but their ON resistances cause significant performance degradation. Larger sleep transistors reduce their ON resistances, but increase leakage current in a sleep mode. Decoupling capacitors beside sleep transistors reduce leakage current. Experimental results show that PMOS SCCMOS with a 4 pF decoupling capacitor reduces leakage current by 1/673 on a 64 bit adder in a 90 nm process.

A wireless interface for stacked chips in System-in-a-Package is presented. The interface utilizes inductive coupling between metal inductors. S21 parameters of the inductive coupling are measured between chips stacked in face-up for the first time. Calculations from a theoretical model have good agreement with the measurements. A transceiver circuit for Non-Return-to-Zero signaling is developed to reduce power dissipation. The transceiver is implemented in a test chip fabricated in 0.35 µm CMOS and the chips are stacked in face-up. The chips communicate through the transceiver at 1.2 Gb/s/ch with 46 mW power dissipation at 3.3 V over 300 µm distance. A scaling scenario is derived based on the theoretical model and measurement results. It indicates that, if the communication distance is reduced to 13 µm in 70 nm CMOS, 34 Tbps/mm2 will be obtained.

A highly collision-resistive RFID system multiplexes communications between thousands of tags and a single reader in combination with time-domain multiplexing code division multiple access (TD-CDMA), CRC error detection, and re-transmission for error recovery. The collision probability due to a random selection of CDMA codes and TDMA channels bounds the number of IDs successfully transmitted to a reader during a limited time frame. However, theoretical analysis showed that the re-transmission greatly reduced the collision probability and that an ID error rate of 2.510-9 could be achieved when 1,000 ID tags responded within a time frame of 400 msec in ideal communication channels. The proposed collision-resistive communication scheme for a thousand multiplexed channels was modeled on a discrete-time digital expression and an FPGA-based emulator was built to evaluate a practical ID error rate under the presence of background noise in communication channels. To achieve simple anti-noise communication in a multiple-response RFID system, as well as unurged re-transmission of ID data, adjusting of correlator thresholds provides a significant improvement to the error rate. Thus, the proposed scheme does not require a reader to request ID transmission to erroneously responding tags. A reader also can lower noise influence by using correlator thresholds, since the scheme multiplexes IDs by CDMA-based communication. The effectiveness of the re-transmission was confirmed experimentally even in noisy channels, and the ID error rate derived from the emulation was 1.910-5. The emulation was useful for deriving an optimum set of RFID system parameters to be used in the design of mixed analog and digital integrated circuits for RFID communication.

With increase of clock frequency, on-chip wire inductance starts to play an important role in power/ground distribution analysis, although it has not been considered so far. We perform a case study work that evaluates relation between decoupling capacitance position and noise suppression effect, and we reveal that placing decoupling capacitance close to current load is necessary for noise reduction. We experimentally show that impact of on-chip inductance becomes small when on-chip decoupling capacitance is well placed according to local power consumption. We also examine influences of grid pitch, wire area, and spacing between paired power and ground wires on power supply noise. When effect of on-chip inductance on power/ground noise is significant, minification of grid pitch is more efficient than increase in wire area, and small spacing reduces power noise as we expected.

Coupling between resonators are analyzed theoretically on basis of the coupled mode theory. New and basic equations for the coupling coefficient are derived and compared with those of waveguides. They should be useful for understanding the physical background of coupling and designing a new coupling scheme.

In the move toward higher clock rates and advanced process technologies, designers of the latest electronic products are finding increasing silicon failure with respect to noise. On the other hand, the minimum dimension of patterns on LSIs is much smaller than the wavelength of exposure, making it difficult for LSI manufacturers to obtain high yield. In this paper, we present a solution to reduce power-supply noise in LSI microchips. The proposed design methodology also considers design for manufacturability (DFM) at the same time as power integrity. The method was successfully applied to the design of a system-on-chip (SOC), achieving a 13.1-13.2% noise reduction in power-supply voltage and uniformity of pattern density for chemical mechanical polishing (CMP).

Unwanted electromagnetic emission occurs due to the common-mode current on the cables entering a PC's metal enclosure and can be treated as wire antennas passing through the apertures of the enclosure. To reduce the emission, a stack of metal rings is suggested to be placed around the cable and external to the aperture, adopting the concept of a Coaxial Band-Stop Filter, for the first time. The influence of this novel structure on the common-mode current is examined in the FDTD-method frame work.

This paper proposes the design to reduce the number of fed elements by replacing with parasitic elements in an array antenna. The study depends on the analysis of electromagnetic wave fields in consideration of the coupling between the half-wavelength dipoles. The case of 2 fed elements and 2 parasitic elements is considered as a unit cell to form the total array. After optimizing the element arrangement, the antenna gain can match that of the equivalent 4-fed element case. Feeding networks in a high power radiating system are analyzed in terms of the length and matching of feed lines, and the arrangement of amplifiers.

A compensation method of the array element pattern is proposed to measure EM field distribution on an observation plane located several wavelengths away from electronic devices in a short time. Numerical and experimental data of the 3 and 5 element collinear dipole array sensors are presented to demonstrate the validity of the proposed method.

This paper reports experimental results on far-field radiated emission for different on-chip chip power supply networks. Two types of test chips were developed as noise generators. One was with on-chip decoupling capacitance, and the other was without intentional on-chip decoupling capacitance. They were assembled in a CSP (Chip scale package). The effects of on-chip decoupling capacitance on far-field radiated emission were investigated for the operation of core logic circuits and output buffer circuits. Reduced radiated emission was observed for every harmonics for the operation of core logic circuits by the on-chip decoupling capacitance. While, reduced radiated emission was observed for the even-order harmonics for the operation of output buffer circuits due to the existence of on-chip decoupling capacitance.

In a multi-layered RF circuit, it is important to avoid unexpected coupling caused by a parallel plate mode excited between different ground layers. Ground via-holes that short-circuit different ground layers are used for suppressing this mode. Quantitative evaluation of relations between suppression effect and ground via-hole disposition is required for optimal design. In this paper, a simple design formula that describes the suppression ratio is derived by mode-matching technique. The results of comparison with an FEM simulation validate our proposed formula. It is shown that the technique is indispensable for designing optimal disposition of via-holes to minimize the area of the ground via-holes for desired performance.

This study presents a method of realizing second order band-pass filters with planar inductive π-network. The proposed filter is more flexible in practical implementation than those using magnetic or electric coupling methods. Electromagnetic simulation results show that the bandwidth of the filter is quite insensitive to the variation in substrate thicknesses and physical layout. A 5.2 GHz filter prototype is designed and fabricated. The measured insertion loss is less than 2.3 dB in the designed pass band and the attenuations at the stop bands are all greater than 30 dB.

A feedforward-based active shielding technique for digital noise suppression is more preferred for its capability of reducing the noise on the entire area inside the guard ring. In order to compensate for the variation of substrate parameters, an automatic control scheme to tune the gain of the active shield circuit is proposed. Simulation results show the effectiveness of the proposed system in reducing the digital noise regardless of circuit layout. Simulation results also show that noise suppression improvement from passive guard ring to active shield with tuning is 20 dB or one tenth while that from active shield without tuning to active shield with tuning is 12 dB.

MBF (Microwave Beam Forming) antennas are beam forming antennas that perform pattern control in RF, for a low-cost design suitable for mobile terminals. An MBF antenna has only a single output port, since this antenna consists of an array antenna, microwave phase shifters, and a power combiner. Because of this simple configuration, MBF antennas cannot adopt conventional beam forming algorithms that require both phase and amplitude control, and signal observation of each antenna element. In this paper, mutual coupling matrix estimation and null forming methods are presented for MBF antennas. It is shown that the mutual coupling matrix can be estimated by changing the antenna weight instead of signal observation of each antenna element. It is also shown that phase-only null forming, including mutual coupling effect, can be done by the optimum phase perturbations. Numerical and experimental results show the performance of these algorithms.

Press-induced long-period fiber gratings exhibiting strong core-to-cladding mode coupling were formed in photonic crystal fiber. Only one resonance peak was observed over a 600 nm spectral range and the resonant wavelength was tuned over the whole range by tilting a groove plate before pressing the fiber. The resonant wavelength decreased with increasing periodicity of the grating, which was opposite to the trend of the step-index conventional optical fiber. Meanwhile, the resonant wavelength increased with increasing the ambient refractive index, which was also opposite to that of the conventional optical fiber.