Memory-based Programmable Logic Device (MPLD) is a new type of reconfigurable device constructed using a general SRAM array in a unique interconnect configuration. This research aims to propose approaches to guarantee the long-term reliability of MPLDs, including a test method to identify interconnect defects in the SRAM array during the production phase and a delay monitoring technique to detect aging-caused failures. The proposed test method configures pre-generated test configuration data into SRAMs to create fault propagation paths, applies an external walking-zero/one vector to excite faults, and identifies faults at the external output ports. The proposed delay monitoring method configures a novel ring oscillator logic design into MPLD to measure delay variations when the device is in practical use. The logic simulation results with fault injection confirm the effectiveness of the proposed methods.

A design-for-testability method and an electrical interconnect test method are proposed to detect open defects occurring at interconnects among dies and input/output pins in 3D stacked ICs. As part of the design method, an nMOS and a diode are added to each input interconnect. The test method is based on measuring the quiescent current that is made to flow through an interconnect to be tested. The testability is examined both by SPICE simulation and by experimentation. The test method enabled the detection of open defects occurring at the newly designed interconnects of dies at experiments test speed of 1MHz. The simulation results reveal that an open defect generating additional delay of 279psec is detectable by the test method at a test speed of 200MHz beside of open defects that generate no logical errors.

With aggressive device scaling, timing failures have become more prevalent due to manufacturing defects and process variations. When timing failure occurs, it is important to take corrective actions immediately. Therefore, an efficient and fast diagnosis method is essential. In this paper, we propose a new diagnostic method using timing information. Our method approximately estimates all the segment delays of measured paths in a design, using inequality-constrained least squares methods. Then, the proposed method ranks the possible locations of delay defects based on the difference between estimated segment delays and the expected values of segment delays. The method works well for multiple delay defects as well as single delay defects. Experiment results show that our method yields good diagnostic resolution. With the proposed method, the average first hit rank (FHR), was within 7 for single delay defect and within 8 for multiple delay defects.

With IC design entering the nanometer scale integration, the reliability of VLSI has declined due to small-delay defects, which are hard to detect by traditional delay fault testing. To detect small-delay defects, on-chip delay measurement, which measures the delay time of paths in the circuit under test (CUT), was proposed. However, our pre-simulation results show that when using on-chip delay measurement method to detect small-delay defects, test generation under the single-path sensitization is required. This constraint makes the fault coverage very low. To improve fault coverage, this paper introduces techniques which use segmented scan and test point insertion (TPI). Evaluation results indicate that we can get an acceptable fault coverage, by combining these techniques for launch off shift (LOS) testing under the single-path sensitization condition. Specifically, fault coverage is improved 27.02∼47.74% with 6.33∼12.35% of hardware overhead.

In recent VLSIs, small-delay defects, which are hard to detect by traditional delay fault testing, can bring about serious issues such as short lifetime. To detect small-delay defects, on-chip delay measurement which measures the delay time of paths in the circuit under test (CUT) was proposed. However, this approach incurs high test cost because it uses scan design, which brings about long test application time due to scan shift operation. Our solution is a test application time reduction method for testing using the on-chip path delay measurement. The testing with on-chip path delay measurement does not require capture operations, unlike the conventional delay testing. Specifically, FFs keep the transition pattern of the test pattern pair sensitizing a path under measurement (PUM) (denoted as p) even after the measurement of p. The proposed method uses this characteristic. The proposed method reduces scan shift time and test data volume using test pattern merging. Evaluation results on ISCAS89 benchmark circuits indicate that the proposed method reduces the test application time by 6.89∼62.67% and test data volume by 46.39∼74.86%.

Small delay defects can cause serious issues such as very short lifetime in the recent VLSI devices. Delay measurement is useful to detect small delay defects in manufacturing testing. This paper presents a design for delay measurement to detect small delay defects on global routing resources, such as double, hex and long lines, in a Xilinx Virtex 4 based FPGA. This paper also shows a measurement method using the proposed design. The proposed measurement method is based on an existing one for SoC using delay value measurement circuit (DVMC). The proposed measurement modifies the construction of configurable logic blocks (CLBs) and utilizes an on-chip DVMC newly added. The number of configurations required by the proposed measurement is 60, which is comparable to that required by stuck-at fault testing for global routing resources in FPGAs. The area overhead is low for general FPGAs, in which the area of routing resources is much larger than that of the other elements such as CLBs. The area of every modified CLB is 7% larger than an original CLB, and the area of the on-chip DVMC is 22% as large as that of an original CLB. For recent FPGAs, we can estimate that the area overhead is approximately 2% or less of the FPGAs.

Nano-scale VLSI design is facing the problems of increased test data volume. Small delay defects are becoming possible sources of test escapes, and high delay test quality and therefore a greater volume of test data are required. The increased test data volume requires more tester memory and test application time, and both result in test cost inflation. Test pattern ordering gives a practical solution to reduce test cost, where test patterns are ordered so that more defects can be detected as early as possible. In this paper, we propose a test pattern ordering method based on SDQL (Statistical Delay Quality Level), which is a measure of delay test quality considering small delay defects. Our proposed method orders test patterns so that SDQL shrinks fast, which means more delay defects can be detected as early as possible. The proposed method efficiently orders test patterns with minimal usage of time-consuming timing-aware fault simulation. Experimental results demonstrate that our method can obtain test pattern ordering within a reasonable time, and also suggest how to prepare test sets suitable as inputs of test pattern ordering.

In order to accelerate yield improvement in semiconductor manufacturing, it is important to prevent the root causes of product-specific failures, such as systematic defects and parametric defects, which are different for each product. We herein propose a method for the investigation of product-specific failures by estimating differences between the actual failing bit signatures (FBSs) and the predicted FBSs caused by random defects. In order to estimate these differences accurately, we have developed a novel algorithm by which to extract the critical area for each FBS. The total failure rate errors of FBSs are within 0.5% for embedded SRAMs. The proposed method identified the root causes of product-specific failures in 150 and 65 nm technology node products.

Shorts and opens are two major kind of defects that are most likely to occur in Very Large Scale Integrated Circuits. In modern Integrated Circuit devices these defects must be considered not only at gate-level but also at transistor level. In this paper, we propose a method for generating test vectors that targets both transistor shorts (tr-shorts) and transistor opens (tr-opens). Since two consecutive test vectors need to be applied in order to detect tr-opens, we assume launch on capture (LOC) test application mechanism. This makes it possible to detect delay type defects. Further, the proposed method employs existing stuck-at test generation tools thus requiring no change in the design and development flow and development of no new tools is needed. Experimental results for benchmark circuits demonstrate the effectiveness of the proposed method by providing 100% fault efficiency while the test set size is still moderate.

Initial growth of GaP on Si substrates using metalorganic vapor phase epitaxy was studied. Si substrates were exposed to PH3 preflow for 15 s or 120 s at 830 after they were preheated at 925. Atomic force microscopy (AFM) revealed that the Si surface after preflow for 120 s was much rougher than that after preflow for 15 s. After 1.5 nm GaP deposition on the Si substrates at 830, GaP islands nucleated more uniformly on the Si substrate after preflow for 15 s than on the substrate after preflow for 120 s. After 3 nm GaP deposition, layer structures were observed on a fraction of Si surface after preflow for 15 s. Island-like structures remained on the Si surface after preflow for 120 s. After 6 nm GaP deposition, the continuity of GaP layers improved on both substrates. However, AFM shows pits that penetrated a Si substrate with preflow for 120 s. Transmission electron microscopy of a GaP layer on the Si substrate after preflow for 120 s revealed that V-shaped pits penetrated the Si substrate. The preflow for a long time roughened the Si surface, which facilitated the pit formation during GaP growth in addition to degrading the surface morphology of GaP at the initial growth stage. Even after 50 nm GaP deposition, pits with a density on the order of 107 cm-2 remained in the sample. A 50-nm-thick flat GaP surface without pits was achieved for the sample with PH3 preflow for 15 s. The PH3 short preflow is necessary to produce a flat GaP surface on a Si substrate.

To improve product yield in high-product-mix semiconductor manufacturing, it is important to estimate the systematic yield inherent to each product and to extract problematic products that have low systematic yields. We propose a simplified and available yield model using a critical area analysis. This model enables the extraction of problematic products by the relationship between actual yields and the short sensitivities of the products. Furthermore, we present an enterprise-wide yield management system using this model and some useful applications. As a result, the system increases the efficiency of the yield management and enhancement dramatically.

It is very important to guarantee the quality of the industrial products by means of visual inspection. In order to reduce the soldering defect with terminal deformation and terminal burr in the manufacturing process, this paper proposes a 3D visual inspection system based on a stereo vision with single camera. It is technically noted that the base line of this single camera stereo was precisely calibrated by the image processing procedure. Also to extract the measuring point coordinates for computing disparity; the error is reduced with original algorithm. Comparing its performance with that of human inspection using industrial microscope, the proposed 3D inspection could be an alternative in precision and in processing cost. Since the practical specification in 3D precision is less than 1 pixel and the experimental performance was around the same, it was demonstrated by the proposed system that the soldering defect with terminal deformation and terminal burr in inspection, especially in 3D inspection, was decreased. In order to realize the inline inspection, this paper will suggest how the human inspection of the products could be modeled and be implemented by the computer system especially in manufacturing process.

We have fabricated and investigated InGaAs Esaki tunnel diodes, grown on GaAs or InP substrates, of varied defect densities. The tunnel diodes exhibit the same I-V characteristics in spite of the variation of defect density. Under the simple thermal annealing and forward current stress tests, the change in the valley current was not observed, indicating that defects were not increased. On the other hand, the reduction in the peak current due to the carbon diffusion was observed under both tests. The diffusion was enhanced by the stress current owing to the energy dissipation associated with the nonradiative electron-hole recombination. From the reduction rates of the peak current, we obtained the thermal and current-enhanced carbon diffusion constants in InGaAs, which are independent of defect density. Although thermal diffusion of carbon in InGaAs is comparable with that in GaAs, the current-induced enhancement of diffusion in InGaAs is extremely weaker than that in GaAs. The difference between activation energy of thermal and current-enhanced diffusion is 0.8 eV, which is independent of stress current density and close to InGaAs bandgap energy. This indicates that the current-enhanced diffusion is dominated by the energy dissipation associated with nonradiative band-to-band recombination. This enhancement mechanism well explains that the current-induced enhancement is independent of defect density and extremely weak. We also have found that the current-enhanced diffusion constant is approximately proportional to the square of current density, suggesting that the recombination in the depletion layer dominates the current-enhanced diffusion.

In this paper, supply current testing for detecting open defects in CMOS circuits is discussed. It is known that open defects cause unpredictable faulty effects and are difficult to be detected. In our test method, an AC electric field is applied during testing. The voltage at a floating node caused by an open defect is varied by the applied electric field and then the defect can be detected. The test pattern generation procedure for open defects is proposed and is applied to benchmark circuits. The experimental results shows that the number of test vectors for opens are much smaller than that for stuck-at faults. The experimental evaluation for an LSI chip is also shown to present the feasibility of our test method.

We have developed and demonstrated a novel technique for electrical inspection and electrical failure analysis, which can detect open, high-resistance, and short circuits without the need for electrical contact with the outside of the LSI chip or the board on which the LSI chip is mounted. The basic idea of the technique is the detection of the magnetic field produced by OBIC (optical beam induced current) or photo current. A DC-SQUID (superconducting quantum interference device) magnetometer is used to detect the magnetic field. This scanning laser-SQUID microscopy ("laser-SQUID" for short) has a spatial resolution of about 1.3 µm. It can be used to distinguish defective chips before bonding pad patterning or after bonding without pin-selection. It can localize any defective site in the chip to within a few square microns.

We investigate the engineering of the impurity bands in photonic crystals (PCs) for realizing high-efficiency wave guiding, all-optical switching and optical delay for ultrashort optical pulses. It is found that quasi-flat impurity bands suitable for the transmission of ultrashort pulses can be achieved by properly controlling the configuration of coupled cavity waveguides (CCWs). At sharp corners, high bending efficiency is obtained over the entire impurity band. All-optical switching can be realized by creating a dynamical band gap at the center of an impurity band. The concentration of electromagnetic wave at defect regions leads to high switching efficiency while the tunable feature of PC defects makes all-optical control possible. It is also revealed that CCWs with quasi-flat impurity bands provide efficient group delay for ultrashort pulses with negligible attenuation and distortion. From the viewpoint of practical fabrication, the effect of disorder on the transmission property of impurity bands is discussed and the criterion for localization transition is determined.

This paper proposes a precise method of realizing simultaneous measurement of microscopic defects and the macroscopic three-dimensional shapes of planar objects having specular reflection surfaces. The direction vector field of surface tilt is evaluated directly by the introduction of a moving slit-light technique based on computer graphic animation. A reflected image created by the moving slit-light is captured by a video camera, and the image sequence of the slit-light deformation is analyzed. The obtained direction vector field of the surface tilt recovers the surface shape by means of integration. Two sample objects, a concave mirror and a plane plastic injection molding, are tested to measure the performance of the proposed method. Surface anomalies such as surface dent and warpage are detected quantitatively at a high resolution (about 0.2 [µm]) and a high accuracy (about 95%) in a wide area (about 15 [cm]) of the test object.

This paper reports a Monte Carlo calculation of the bimolecular reaction of arsenic precipitation. As the accuracy of the numerical solution for the coupled rate equations strongly depends on the size of grid spacing, it is necessary to choose adequate number of rate equations in order to understand the behavior of the extended defects. Therefore, we developed a general kinetic Monte Carlo model for the extended defects, which explicitly takes the time evolution of the size density of the extended defects into account. The Monte Carlo calculation exhibits a quantitative agreement with the experimental data for deactivation, and successfully reproduces the rapid deactivation at the beginning phase followed by slow deactivation in the subsequent steps.

This paper reports the implementation in three dimensions (3D) of diffusion models for low dose implanted dopants in silicon and the various numerical issues associated with it. In order to allow the end-users to choose between high accuracy or small calculation time, a conventional and 5-species diffusion models have been implemented in the 3D module DIFOX-3D belonging to the PROMPT plateform. By comparison with one and two-dimensional (1D and 2D) simulations performed with IMPACT-4, where calibrated models exist, the validity of this 3D models have been checked. Finally, the results obtained for a 3-dimensional simulation of a rapid thermal annealing step involved in the manufacturing of a MOS transistor are presented what show the capability of this module to handle the optimization of real devices.

Recent years have seen great advances in our understanding and modeling of the coupled diffusion of dopants and defects in silicon during integrated circuit fabrication processes. However, the ever-progressing shrinkage of device dimensions and tolerances leads to new problems and a need for even better models. In this review, we address some of the advances in the understanding of defect-mediated diffusion, focusing on the equations and parameters appropriate for modeling of dopant diffusion in submicron structures.