In this paper, we present a new analog multiplier with wide input range which is achieved by utilizing the variable threshold voltage characteristics of FG-MOSFET's. The performance of the proposed multiplier is evaluated through HSPICE simulation with 2.0 µm CMOS process parameters. From HSPICE simulation, we can find that the proposed multiplier can be operated at the supply voltage of 3.0 V with 3.0 Vp-p input range. Namely, the input voltage range of the multiplier is equal to the supply voltage. The maximum power consumption of the multiplier is 8.8 mW. The THD is 1.36% under the condition that the amplitude of the input signal is 3.0 Vp-p and the frequency is 1 MHz. Under the same condition, the linearity error is less than 0.5%. The -3 dB bandwidth of the proposed multiplier is 23 MHz.

This paper presents a new asynchronous multiplier. The original array structure is divided into two asymmetric arrays, called an upper array and a lower array. For the lower array, Left to Right scheme is applied to take advantage of a fast computation and low power consumption as well. Simulation results show that the proposed multiplier has 40% of performance improvement with a relatively lower power consumption. The multiplier has been implemented in a CMOS 0.35 µm technology and proved functionally correct.

This paper describes a novel four-quadrant analog multiplier. It is comprised of two mixed signal circuits, a voltage adder circuit, a voltage divider circuit and a basic multiplier. Its major advantages over the other analog multipliers are: this design has single ended inputs, the geometry of all CMOS transistors are equal, and its output can be the product of two signal currents, the product of two signal voltages, or the product of a signal current and a signal voltage. Second-order effects are analyzed, and the experimental and simulative results that confirm the theoretical analysis are carried out.

This paper presents a group theoretic approach to the design of Decision diagrams (DDs) with increased functionality of nodes. Basic characteristics of DDs determine their applications, and thus, the optimization of DDs with respect to different characteristics is an important task. Increased functionality of nodes provides for optimization of DDs. In this paper, the methods for optimization of binary DDs by pairing of variables are interpreted as the optimization of DDs by changing the domain group for the represented functions. Then, it is pointed out that, for Abelian groups, the increased functionality of nodes by using larger subgroups may improve some of the characteristics of DDs at the price of other characteristics. With this motivation, we proposed the use of non-Abelian groups for the domain of represented functions by taking advantages from basic features of their group representations. At the same time, the present methods for optimization of DDs, do not offer any criterion or efficient algorithm to choose among a variety of possible different DDs for an assumed domain group. Therefore, we propose Fourier DDs on non-Abelian groups to exploit the reduced cardinality of the Fourier spectrum on these groups.

In this paper, we describe two approaches to optimize the Phase-Mode pipelined parallel multiplier. One of the approaches is reforming a data distribution for an AND array, which is named the hybrid structure. Another method is applying a Booth encoder as a substitute of the AND array in order to generate partial products. We design a 2-bit 2-bit Phase-Mode Booth encoder and test the circuit by the numerical simulations. The circuit consists of 21 ICF gates and operates correctly at a throughput of 37.0 GHz. The numbers of Josephson junctions and the pipelined stages in each scale of multipliers are reduced remarkably by using the encoder. According to our estimations, the Phase-Mode Booth encoder is the effective component to improve the performance of large-scale parallel multipliers.

A new modulation technique for "LInear modulation with Nonlinear Translation" (LINT) is proposed. The new LINT technique is an extension of the popular LINC (LInear amplification with Nonlinear Components) technique for power efficient transmitter operation with spectrally efficient linear modulations. While providing this advantage, the LINT technique also incorporates the principles of direct modulation and provides frequency translation without the use of multiple stages of bulky upconversion circuitry. These features make the LINT method especially suitable for high frequency applications emerging at upper microwave and millimeter-wave frequencies. A two-stage 12 frequency multiplier chain is employed for frequency translation, to evaluate the feasibility of the LINT architecture for generating 16-QAM modulation at 28 GHz. The effect of imperfections on modulator performance is also considered.

To design a high-speed m-bit parallel inversion circuit over GF(2m), we study two variations for the repetition-operation of the numerical formula, AB2, in employing square-first and multiply-first type operations. From the proposed two variations, we propose four inversion architectures, adopting the multiplier and square in [10], as follows: simple duplication semi-systolic architecture for multiply-first inversion circuit (MFIC), m-bit parallel semi-systolic architecture for MFIC, simple duplication semi-systolic architecture for square-first inversion circuit (SFIC), and simplified m-bit parallel semi-systolic architecture for SFIC. Among them, performance of the simplified m-bit parallel semi-systolic architecture for SFIC is recommended for a high-speed applications to get a maximum throughput in the sense of small hardware-complexity, and low latency. When we implement the simplified 8-bit parallel semi-systolic architecture for SFIC over GF(28) by using 0.25 µm CMOS library, necessary are 2495 logic-gates and 1848 latches, and the latency is 56 and the estimated clock-rate is 580 MHz at 100% throughput.

In this paper, a high performance 3232-bit multiplier for a DSP core is proposed. The multiplier is composed of a block of Booth Encoder, a block of data compression, and a block of a 64-bit adder. In the block of Booth encoder, a conditional sign decision Booth encoder that reduces the gate delay and power consumption is proposed. In the block of data compression, 4-2 and 9-2 data compressors based on a novel compound logic are used for the efficient compressing of extra sign bit. In the block of 64-bit adder, an adaptive MUX-based conditional select adder with a separated carry generation block is proposed. The proposed 3232-bit multiplier is designed by a full-custom method and there are about 28,000 transistors in an active area of 900 µm 500 µm with 0.25 µm CMOS technology. From the experimental results, the multiplication time of the multiplier is about 3.2 ns at 2.5 V power supply, and it consumes about 50 mW at 100 MHz.

Hypercomplex coefficient digital filters provide several attractive advantages such as compact realization with reduced system order, inherent parallelism. However, they also possess a drawback in that a multiplier requires a large amount of computations. This paper proposes a computationally efficient implementation of digital filters whose coefficient is a type of hypercomplex number; a bicomplex number. By decomposing a bicomplex multiplier into two parallel complex multipliers, we show that hypercomplex digital filters can be implemented as two parallel complex digital filters. The proposed implementation offers more than a 60% reduction in the count of real multipliers.

A new four-quadrant (4Q) Multiplier complementally using linear and saturation regions of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is proposed for the wide dynamic range and superior flexibility of the input range. This multiplier operates in the region except for the threshold voltage VT to zero. The validity of the proposed circuit is confirmed through HSPICE simulation.

The radix-64 encoding scheme was used to reduce the number of partial products in the 5454 CMOS parallel multiplier. The transistor counts, the chip area and the power-delay product were reduced by 28%, 22%, and 17%, respectively, compared to any of the published 5454 CMOS parallel multipliers. A redundant binary (RB) number system was used to represent any of the 65 multiplying coefficients as a RB number which consists of two of 9 fundamental multiplying coefficients and their complements. The resultant RB partial products were added by using optimized RB adders. The total transistor count of the proposed multiplier was 43,579. The chip area in 0.25 µm CMOS process with 5 metal layers was 0.99 mm2. The power consumption and the multiplication time were 111 mW and 6.9 ns, respectively.

A new logic-in-memory circuit is proposed for a fine-grain pipelined VLSI system. Dynamic-storage elements are distributed over a logic-circuit plane. A functional pass gate is a key component, where a linear summation and threshold function are merged compactly using charge-storage and charge-coupling effect with a DRAM-cell-based circuit structure. The use of dynamic logic based on pass-transistor network using functional pass gates makes it possible to realize any logic circuits compactly with small power dissipation. As a typical example, a 54-bit pipelined multiplier is implemented by using the proposed circuit technology. Its power dissipation and chip area are reduced to about 63 percent and 72 percent, respectively, in comparison with those of a corresponding binary CMOS implementation under 0.35-µm CMOS technology.

A new approach on designing a finite field multiplier architecture is proposed. The proposed architecture trades reduction in the number of clock cycles with resources. This architecture features high performance, simple structure, scalability and independence on the choice of the finite field, and can be used in high security cryptographic applications such as elliptic curve crypto-systems in large prime Galois Fields (GF(2m)).

We introduce PC Linux cluster computing techniques to an Evolutionary Graph Generation (EGG) system, and successfully implement the parallel version of the EGG system, called PEGG. Our survey satisfactorily shows that the parallel evolutionary approach meets our expectation that the final solutions obtained from PEGG will be as good as or better than those obtained from EGG, and that PEGG can ultimately improve the speed of evolution.

This paper considers FIR filter design using linear predictive coding technique, for which the coefficients belong to a small set of integers, so that the coefficients have small wordlengths. Previously, integer programming was used to find the coefficients of such filters. However, the design method using integer programming suffers from high computational cost as the filter length increases. The computation can quickly become prohibition. In this paper, we propose two designs of predictive encoded FIR filters based on a modified Karmarkar's linear programming algorithm, which is known to be more suitable for solving large problems. First, we formulate the problem as a weighted minimax error problem and arrange it in a form that the modified Karmarkar algorithm can be applied. The design algorithm has the same (low) complexity as that of the weighted least-square method, but it can solve problems with some constraints, whereas the weighted least-square method cannot. However, the algorithm has a difficulty due to an ill condition caused by matrix inversion when the predictive filter order is high. To avoid this difficulty, we formulate the design as a weighted least absolute error problem. By using this second proposed algorithm, a filter with shorter coefficient wordlength can be found using a higher-order predictor filter at the expense of more computational cost. To further reduce the coefficient wordlength, the filter impulse response is separated into two sections having different ranges of coefficient values. Each section uses a different scaling factor to scale the coefficient values. With small coefficient wordlength, the filter can be realized without hardware multipliers using a low-radix signed-digit number representation. Each coefficient is distributed in space as 2-3 ternary {0,1} or quinary {0,1, 2} coefficients. Ternary coefficients require only add/subtract operation, while quinary coefficients require one-bit shift and add/subtract operations. The shift can be hardwired without any additional hardware.

A unified polyphase representation of analysis and synthesis filter banks is introduced in this paper, and then the efficient implementation on digital signal processors (DSP) is investigated. Especially, the number of memory accesses, power consumption, processing accuracy and the required instruction cycles are discussed. Firstly, a unified representation is given, and then two types of procedures, SIMO system-based and MISO system-based procedures, are shown, where SIMO and MISO are abbreviations for single-input/multiple-output and multiple-input/single-output, respectively. These procedures are compared to each other. It is shown that the number of data load in SIMO system-based procedure is a half of that in MISO system-based procedure for two-channel filter banks. The implementation of M-channel filter banks is also discussed.

We have proposed area-reduction techniques for superscalar datapath architectures with 34 SIMD instructions and have developed an integer-media unit based on these techniques. The unit's design is both functionally asymmetrical and integer-SIMD unified, and the resulting savings in area are 27%-48% as compared to other, functionally equivalent mid-level microprocessor designs, with performance that is, at most, only 7.2% lower. Further, in 2-D IDCT processing, the unit outperforms embedded microprocessor designs without SIMD functions by 49%-118%. Specifically, effective area reduction of adders, shifters, and multiply-and-adders has been achieved by using the unified design. These area-effective techniques are useful for embedded microprocessors and scalable systems that employ highly parallel superscalar and on-chip parallel architectures. The integer-media unit has been implemented in an evaluation chip fabricated with 0.15-µm 5-metal CMOS technology.

In this paper, we propose a high-speed multiplier-free realization using ROM's to store the results of coefficient scalings in combination with higher signal rate and pipelined operations, without the need of hardware multipliers. By varying some parameters, the proposed structure provides various combinations of hardware and clock speed (or throughput). Examples are given comparing the proposed realization with the distributed arithmetic (DA) realization and direct-form realization with power-of-two coefficients. Results show that with proper choices of the parameters the proposed structure achieves a faster processing speed with less hardware, as compared to the DA realization, while it is much faster than the direct-form with slightly more hardware.

This paper describes a new algorithm for configuring the array of adders used to add the partial products in a multiplier circuit. The new algorithm reduces not only the number of half adders in an adder tree, but also the number of operands passed to the block generating the final product in a multiplier. The arrays obtained with this algorithm are smaller than Wallace's ones and have fewer outputs than Dadda's arrays. We show some evaluation figures and preliminary simulation results of 4, 8 and 16-bit tree configurations.

This study presents two new bit-parallel cellular multipliers based on an irreducible all one polynomial (AOP) over the finite field GF(2m). Using the property of the AOP, this work also presents an efficient algorithm of inner-product multiplication for computing AB2 multiplications is proposed, with a structure that can simplify the time and space complexity for hardware implementations. The first structure employs the new inner-product multiplication algorithm to construct the bit-parallel cellular architecture. The designed multiplier only requires the computational delays of (m+1)(TAND+TXOR). The second proposed structure is a modification of the first structure, and it requires (m+2) TXOR delays. Moreover, the proposed multipliers can perform A2iB2j computations by shuffling the coefficients to make i and j integers. For the computing multiplication in GF(2m), the novel multipliers turn out to be efficient as they simplify architecture and accelerate computation. The two novel architectures are highly regular, simpler, and have shorter computation delays than the conventional cellular multipliers.