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IEICE TRANSACTIONS on Electronics

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Advance publication (published online immediately after acceptance)

Volume E103-C No.2  (Publication Date:2020/02/01)

    Regular Section
  • Reconstruction of Scatterer Shape from Relative Intensity of Scattered Field by Using Linearized Boundary Element Method

    Jun-ichiro SUGISAKA  Takashi YASUI  Koichi HIRAYAMA  

     
    PAPER-Electromagnetic Theory

      Pubricized:
    2019/08/22
      Page(s):
    30-38

    A method to reconstruct the surface shape of a scatterer from the relative intensity of the scattered field is proposed. Reconstruction of the scatterer shape has been studied as an inverse problem. An approach that employs boundary-integral equations can determine the scatterer shape with low computation resources and high accuracy. In this method, the reconstruction process is performed so that the error between the measured far field of the sample and the computed far field of the estimated scatterer shape is minimized. The amplitude of the incident wave at the sample is required to compute the scattered field of the estimated shape. However, measurement of the incident wave at the sample (measurement without the sample) is inconvenient, particularly when the output power of the wave source is temporally unstable. In this study, we improve the reconstruction method with boundary-integral equations for practical use and expandability to various types of samples. First, we propose new boundary-integral equations that can reconstruct the sample shape from the relative intensity at a finite distance. The relative intensity is independent from the amplitude of the incident wave, and the reconstruction process can be performed without measuring the incident field. Second, the boundary integral equation for reconstruction is discretized with boundary elements. The boundary elements can flexibly discretize various shapes of samples, and this approach can be applied to various inverse scattering problems. In this paper, we present a few reconstruction processes in numerical simulations. Then, we discuss the reason for slow-convergence conditions and introduce a weighting coefficient to accelerate the convergence. The weighting coefficient depends on the distance between the sample and the observation points. Finally, we derive a formula to obtain an optimum weighting coefficient so that we can reconstruct the surface shape of a scatterer at various distances of the observation points.

  • A 28-GHz CMOS Vector-Summing Phase Shifter Featuring I/Q Imbalance Calibration Supporting 11.2Gb/s in 256QAM for 5G New Radio

    Jian PANG  Ryo KUBOZOE  Zheng LI  Masaru KAWABUCHI  Atsushi SHIRANE  Kenichi OKADA  

     
    PAPER-Electronic Circuits

      Pubricized:
    2019/08/19
      Page(s):
    39-47

    Regarding the enlarged array size for the 5G new radio (NR) millimeter-wave phased-array transceivers, an improved phase tuning resolution will be required to support the accurate beam control. This paper introduces a CMOS implementation of an active vector-summing phase shifter. The proposed phase shifter realizes a 6-bit phase shifting with an active area of 0.32mm2. To minimize the gain variation during the phase tuning, a gain error compensation technique is proposed. After the compensation, the measured gain variation within the 5G NR band n257 is less than 0.9dB. The corresponding RMS gain error is less than 0.2dB. The measured RMS phase error from 26.5GHz to 29.5GHz is less than 1.2°. Gain-invariant, high-resolution phase tuning is realized by this work. Considering the error vector magnitude (EVM) performance, the proposed phase shifter supports a maximum data rate of 11.2Gb/s in 256QAM with a power consumption of 25.2mW.

  • DFE Error Propagation and FEC Interleaving for 400GbE PAM4 Electrical Lane Open Access

    Yongzheng ZHAN  Qingsheng HU  Yinhang ZHANG  

     
    PAPER-Integrated Electronics

      Pubricized:
    2019/08/05
      Page(s):
    48-58

    This paper analyzes the effect of error propagation of decision feedback equalizer (DFE) for PAM4 based 400Gb/s Ethernet. First, an analytic model for the error propagation is proposed to estimate the probability of different burst error length due to error propagation for PAM4 link system with multi-tap TX FFE (Feed Forward Equalizer) + RX DFE architecture. After calculating the symbol error rate (SER) and bit error rate (BER) based on the probability model, the theoretical analysis about the impact of different equalizer configurations on BER is compared with the simulation results, and then BER performance with FEC (Forward Error Correction) is analyzed to evaluate the effect of DFE error propagation on PAM4 link. Finally, two FEC interleaving schemes, symbol and bit interleaving, are employed in order to reduce BER further and then the theoretical analysis and the simulation result of their performance improvement are also evaluated. Simulation results show that at most 0.52dB interleaving gain can be achieved compared with non-interleaving scheme just at a little cost in storing memory and latency. And between the two interleaving methods, symbol interleaving performs better compared with the other one from the view of tradeoff between the interleaving gain and the cost and can be applied for 400Gb/s Ethernet.

  • S-Shaped Nonlinearity in Electrical Resistance of Electroactive Supercoiled Polymer Artificial Muscle Open Access

    Kazuya TADA  Masaki KAKU  

     
    BRIEF PAPER-Organic Molecular Electronics

      Pubricized:
    2019/08/05
      Page(s):
    59-61

    S-shaped nonlinearity is found in the electrical resistance-length relationship in an electroactive supercoiled polymer artificial muscle. The modulation of the electrical resistance is mainly caused by the change in the contact condition of coils in the artificial muscle upon deformation. A mathematical model based on logistic function fairly reproduces the experimental data of electrical resistance-length relationship.

  • Dielectrophoretic Assembly of Gold Nanoparticle Arrays Evaluated in Terms of Room-Temperature Resistance

    Yoshinao MIZUGAKI  Makoto MORIBAYASHI  Tomoki YAGAI  Masataka MORIYA  Hiroshi SHIMADA  Ayumi HIRANO-IWATA  Fumihiko HIROSE  

     
    BRIEF PAPER-Semiconductor Materials and Devices

      Pubricized:
    2019/08/05
      Page(s):
    62-65

    Gold nanoparticles (GNPs) are often used as island electrodes of single-electron (SE) devices. One of technical challenges in fabrication of SE devices with GNPs is the placement of GNPs in a nanogap between two lead electrodes. Utilization of dielectrophoresis (DEP) phenomena is one of possible solutions for this challenge, whereas the fabrication process with DEP includes stochastic aspects. In this brief paper, we present our experimental results on electric resistance of GNP arrays assembled by DEP. More than 300 pairs of electrodes were investigated under various DEP conditions by trial and error approach. We evaluated the relationship between the DEP conditions and the electric resistance of assembled GNP arrays, which would indicate possible DEP conditions for fabrication of SE devices.