By adding an auxiliary transformer to a single-stage single-switch power-factor-corrected converter (S4PFCC), the storage capacitor voltage and its range of voltage change against line voltage change are reduced. In addition, this transformer provides a direct power transfer path for input line to output load to increase the conversion efficiency. High power factor is maintained due to the elimination of dead angle of the input current. This paper presents detailed analysis and optimal design of a discontinuous conduction mode (DCM) boost-flyback S4PFCC with the auxiliary transformer. Experimental results for a 15 V/60 W prototype and with comparison to a S4PFCC without the auxiliary transformer are given to show the proposed approach effective.

We've been developing new electron guns for a high brightness CRT. The electron guns were modified to increase the emission current without the increase of the driving voltage. We achieved the high brightness CRT with "low cut-off electron gun" and the gun was successfully introduced into our multimedia CRT. Now we are developing next generation gun or "double drive electron gun" for larger screen CRT. The gun can emit about double current in comparison with the "low cut-off electron gun."

We have obtained high performance and low voltage driving OCB panel by reducing the critical voltage and retardation matching between liquid crystal layer and compensation films. Flattening color filter layer and optimizing rubbing process have minimized the critical voltage in the panel. In addition, an appropriate retardation of the film and LC layer has scanned to achieve low driving voltage and high transmission. Especially, by adopting new driving scheme, we considerably reduced the initial bend transition time, which is known as one of drawbacks in OCB mode. As a result, we developed the proto-type 17" WXGA OCB panel with less than 5 V drive, over 90% of TN light efficiency and over 80 degree for all viewing direction except for rubbing direction including color shift as well as high-speed response time.

This paper describes the robust design of the 30 V high voltage NMOS (HVNMOS) structure implemented in a 0.6 µm 5 V standard CMOS processes without any additional masks or process steps. The structure makes use of the field oxide (FOX) and light doping N-well to increase the drain to gate and drain to bulk breakdown voltages, respectively. By varying the six spacing parameters: the channel length, gate overlap FOX, N-well overlap channel length, poly to the active area of the drain (OD2), metal extend beyond the OD2 and N-well extend beyond the OD2 in HVNMOS structure, the breakdown voltage can be improved. The experimental results show that the breakdown voltage of the normal NMOS is 11 V, and the breakdown voltage of the HVNMOS is increased to over 30 V. With the optimized layout parameters of the HVNMOS, it can be increased to 38 V.

We present excellent performance of a novel two-stage SiGe hetero-bipolar transistor (HBT) power amplifier (PA) in which different collector doping structures were employed for the first and second stages. A selectively ion implanted collector (SIC) structure was employed for the first stage HBT in order to obtain a high gain, while without-SIC structure was used for the second stage HBT in order to achieve a high breakdown voltage. At 1.95 GHz, the total PAE of 31% and a gain of 28 dB with an output power (Pout) of 26 dBm were obtained while the adjacent channel power ratio (ACPR) was less than -38 dBc for W-CDMA modulation signals.

We study the advantages and limitations of InP/GaAsSb/InP DHBTs for high-speed digital circuit applications. We show that the high-current performance limitation in these devices is electrostatic in nature. Comparison of the location of collector current blocking in various collector designs suggests a smoother, more gradual onset of blocking effects in type-II collectors. A comparison of collector current blocking effects between InP/GaAsSb--based and various designs of InP/GaInAs--based DHBTs provides support for our analysis.

We demonstrated the uniformity and stability as well as the high breakdown voltage of 0.1-µm-gate InP HEMTs with a double recess structure. To overcome the drawbacks regarding the uniformity and stability in the double recess structure, an InP passivation layer that functions as an etch-stopper and a surface passivator was successfully applied to the structure. It was confirmed that there was no degradation in the uniformity and stability of device performance for the double recess HEMTs that had the breakdown voltages in the on-state and off-state improved by a factor of 1.6.

DC and RF performances of AlGaN/GaN HEMTs are simulated using a two-dimensional device simulator with the material parameters of GaN and AlGaN. The cut-off frequency is estimated as 205 GHz at the gate length of 0.05 µm and the drain breakdown voltage at this gate length is over 10 V. The values are satisfactory for millimeter wavelength power applications. The use of thin AlGaN layers has key importance to alleviate gate parasitic capacitance effects at this gate length.

The fully integrated LC voltage controlled oscillator by 0.35 µm CMOS technology is demonstrated. It has 2 GHz oscillation frequency, 23.58 mW power consumption under 3 V biased and 9.1% frequency tuning. The layout optimization method of inductor to increase quality factor and also to reduce phase noise is used. A general method is proposed which is capable of making an effective prediction of F, device excess noise number, and acquiring the phase noise of oscillators accurately. From this proposed method, the low phase noise by calculation is attained. The phase noise of measured value which shows good match with calculating data is about -115.5 dBc/Hz at off set frequency 600 kHz.

In order to increase the capacity of a DS-CDMA system, several kinds of interference suppression techniques have been studied, such as multiple access interference (MAI) cancellers and adaptive array antennas. However, their performance tends to degrade in high traffic-load situations. To compensate for the degradation, a receiver cascading an adaptive array antenna and a multistage parallel interference canceller (PIC) is studied in this paper. This receiver first uses an adaptive array antenna to suppress interference signals spatially, and uses a multistage PIC to suppress in-beam interference effectively. The performance of the cascaded receiver is evaluated with two schemes for antenna weight generation by computer simulations assuming a Rayleigh-distributed L-path channel. When antenna weights are generated for each user by an LMS algorithm, the cascaded receiver has shown better performance at the cost of a large number of pilot symbols and symbol by symbol weight update. Its performance degradation is 2.8 dB at the BER of 10-4 even when the number of users increases from one to 24. On the other hand, when antenna weights are generated for each path by a DMI algorithm, its performance is degraded due to the inaccurate weight generation which occurs when the SINR of the desired signal is small. This degradation can be mitigated by using all signals of the desired user received by all antenna patterns of desired user for RAKE combining when the difference among arrival angles of the paths of the desired user is small.

The demand for wireless mobile communications has grown at a very high rate, recently. In order to solve the non-uniform traffic rates, the use of cell splits is unavoidable for balancing the traffic rate and maximizing total system capacity. For cell planning, a DS-CDMA cellular system can be comprise of different cell sizes because of different demands and population density of the service area. In this paper, we develop a general model to study the forward link capacity and outage probability of a DS-CDMA cellular system with mixed cell sizes. The analysis of outage probability is carried out using the log-normal approximation. When a macrocell is split into the three microcells, as an example, we calculate the multi-cross interferences between macrocells and microcells, and the forward link capacities for the microcells and the neighboring macrocells. The maximum allowable capacity plane for macrocell and microcell is also investigated. The numerical results and discussions with previous published results of reverse link are summarized.

In this paper, we propose a modified CP-AFC (Cross-Product Automatic Frequency Control) algorithm to enhance coherent signal detection for WCDMA reverse link receiver. We introduce a moving average filter at the FDD input to decrease the noise effect by increasing the number of cross-products, since pilot symbol in WCDMA is not transmitted continuously. We also add normalization algorithm to overcome the conventional CP-FDD's sensitivity to the variance of input signal amplitude and to increase the linear range of S-curve. For rapid frequency acquisition and tracking, we adopt a multi-stage tracking mode. We applied the proposed algorithm in the implementation of WCDMA base station modem successfully.

In this paper, a Micro-Step-Separating System is realized for investigating phenomena of initial state of separating contacts. This system can control the contact separation in a discrete way with about 0.5 µm step. By using this system, we observed a relationship between contact voltage and contact separation gap. Ag contacts were observed. The observation showed that the contact voltage rose up and then fell down to the stable voltage at each step separation. From this observation, we expect to elucidate the contact bridge phenomena with more sophisticated way because we can approach them under the thermal equilibrium condition.

Sliding contact behavior is important in the mechanism of collecting current. In this study, the effect of ambient gas including an inert gas on surface film formation and on the contact voltage drop was examined, changing the atmosphere from low pressure to atmospheric pressure. Furthermore, the sliding surface state was observed using SEM, EDX and XPS analyzers after the test operation. As a result, at the sliding contact in an inert gaseous environment (nitrogen and argon), it was confirmed that the contact voltage drop tends to increase. However, it was clarified that any chemically generated surface film is difficult to detect in the inert gas environment by qualitative analysis. On the basis of these results, we suggest the existence of physically adsorbed surface film. The relationship between inert gases and sliding contact phenomena is discussed.

The low phase noise, low supply voltage 1.3 GHz CMOS VCO has been realized by 0.25 µm standard CMOS technology without any trimming and any tuning. The phase noise characteristics of -109 dBc/Hz and -123 dBc/Hz at 100 kHz offset and 500 kHz offset were achieved from carrier, respectively, with 1.3 GHz oscillation frequency at 1.4 V supply voltage. The performance of 1.4 V supply voltage phase noise was superior to that of 2.0 V supply voltage phase noise due to low output impedance current source. The tuning ranges of 13.3%, 16.6%, and 20.1% for 1.4 V, 1.8 V, and 2.0 V supply voltage were achieved, respectively. The amplifier consisted of one pair of PMOS differential stage with large gate length NMOS current source to realize low supply voltage operation and to avoid flicker noise contribution for phase noise. The on-chip spiral inductor consisted of three terminals arranged in a special shape to obtain high Q and small chip area. The power dissipation of this VCO was 22.4 mW without buffer amplifier.

This paper describes the design of a 2.7 V operational, 200 MS/s, 14-bit CMOS D/A converter (DAC). The DAC consists of 63 current cells in matrix form for an upper 6-bit sub-DAC, and 8 current cells and R-2R ladder resistors for a lower 8-bit sub-DAC. A source degeneration resistor, for which a transistor in the triode operational region is used, is connected to the source of a MOS current source transistor in a current cell in order to reduce the influence of threshold voltage (Vth) variation and to satisfy the differential nonlinearity error specification as a 14-bit DAC. In conventional high-speed and high-resolution DACs that have the same design specifications described here, spurious-free dynamic range (SFDR) characteristics commonly deteriorate drastically as the frequency of the reconstructed waveform increases. The causes of this deterioration were carefully examined in the present study, finding that the deterioration is caused in part by the input-data-dependent time-constant change at the output terminal. Unexpected current flow in parasitic capacitors associated with current sources causes the change in the output current depending on the input data, resulting in time-constant change. In order to solve this problem, we propose a new output circuit to fix the voltage at the node where the outputs of the current sources are combined. SPICE circuit simulation demonstrates that 63 dB of SFDR characteristics for the 90 MHz reconstructed waveform at the output can be realizable when the supply voltage is 2.7 V, the clock rate is 200 MS/s, and the power dissipation is estimated to be 300 mW.

A voltage-controlled ring oscillator with an RC delay as an additional delay to vary the oscillation frequency is proposed. The use of MOS resistors provides a wide range tuning ability from 40 Hz to 366 MHz. The proposed circuit also enables implementation of a low frequency voltage-controlled ring oscillator with relatively smaller devices than the conventional one.

We present a new multi-stage charge pump that is suitable for low-voltage operation, and in particular for low voltage flash memory. Compare to the Dickson charge pump and previously reported modified Dickson charge pumps, the proposed charge pump offers the improved pumping voltage gains. The proposed charge pump is composed of a pair of pumps and utilizes the internal boosted voltages of one side of the paired pumps as the charge transferring voltages to the other side. The simulated and measured results indicate that the proposed pump is highly efficient in overcoming both the pumping gain decrease and the current driving capability degradation caused by the threshold voltage of the charge-transfer gate.

A pass-transistor logic is enhanced with a bootstrap configuration for sub-1 V operation at high speed and low power. The bootstrap configuration drives the output to full swing, which accelerates the signal transition and cuts off the short-circuit current of subsequent CMOS logic gates. The asynchronous or synchronous timing sequence of the input (drain) and the control (gate) signals ensures bootstrap operation. A 1-b arithmetic logic unit (ALU) and an EXNOR gate built with the bootstrap pass-transistor logic outperforms those built with other types of pass-transistor logic. An experimental 16-b pass-transistor adder operates down to 0.4 V with a delay time of 4.2 ns and a power dissipation of 2.8 µ W/MHz at 0.5 V.

A linear voltage-to-current convertor without current mirror circuit is proposed for low distortion applications employing short channel MOSFET's. Twin current sources and current sinks pair of MOSFET's having the same drain-source voltage are employed for a substitute of the current mirror circuits, in order to eliminate the channel length modulation factor of the short channel MOSFET's. HSPICE simulation is shown in order to evaluate the proposed circuits. As an application, a low distortion OTA is realized by employing the proposed linear voltage-to-current convertor with short channel MOSFET's.