This paper introduces a switched-voltage delay cell with differential inputs. It can be used as a building block for a range of analogue functions such as voltage-to-frenquency converter, A/D converter, etc. Applications incorporating the delay cell are presented. The performances are verified by simulations on PSpice.

We propose an effective model that can reproduce the reverse short channel effect (RSCE) of the threshold voltage (Vth) of MOSFETs using a conventional process simulator that solves one equation for each impurity. The proposed model is developed for local modeling which is effective within the limited process conditions. The proposed model involves the physics in which RSCE is due to the pile up of channel dopant at the Si/SiO2 interface. We also report the application to actual device design using our model. The calculation cost is much lower than for a pair diffusion model, and device design in an acceptable turn around time is possible.

The current voltage characteristics of the ballistic metal oxide semiconductor field effect transistor (MOSFET) is reviewed. Reducing the carrier scattering by employing e.g. the intrinsic channel structure and the low temperature operation, nanometer to sub-0.1 µm size MOSFETs operation approaches the ballistic transport. The drain current is derived by analyzing the carrier behavior in the vicinity of the potential maximum in the channel. The carrier degeneracy and the predominant carrier distribution in the lowest subband around the maximum point have critical effects on the current value. A convenient approximation of the current in terms of terminal voltages is given. The current control mechanism is discussed with use of the "Injection velocity," with which carriers are injected from the source to the channel. An index to represent the ballisticity is given, and some published experimental data are analyzed. Transport of the quasi-ballistic MOSFET is discussed.

In this paper, a CMOS down-conversion double-balanced mixer is presented with the modified low voltage design technique. The frequencies of the radio frequency (RF) signal, local oscillator (LO) and intermediate frequency (IF) are 2.4 GHz, 2.3 GHz and 100 MHz, respectively. Measurement results of the proposed mixer exhibit 6.7 dB of conversion gain, -18 dBm of input 1 dB compression point (P-1 dB), -8 dBm of input-referred third-order intercept point (IIP3), and 14.7 dB single-side band (SSB) noise figure (NF) while applying -8 dBm LO power and consumes 3.3 mA from 1.8 V supply voltage. It can provide 0.7 dB conversion gain when the supply voltage reduces to 1.3 V. This mixer was fabricated in a 0.35 µm 1P4M standard digital CMOS process and the die size is 1.5 1.1 mm2.

Technology scaling will become difficult due to power wall. On the other hand, future computer and communications technology will require further reduction in power dissipation. Since no new energy efficient device technology is on the horizon, low power CMOS design should be challenged. This paper discusses what and how much designers can do for CMOS power reduction.

In SDMA, a spatial domain interference canceller applying a multistage processing concept to the MMSE multibeam adaptive array has an attractive feature. Weak power signals strongly interfered can be detected in the succeeded stages after removing other strong power signals which are already detected. This idea can be enhanced to the reference timing estimation required in the MMSE algorithm. In this paper, the spatial domain interference canceller introducing multistage timing estimation is proposed and its performance is evaluated by computer simulations. The results show that the timing estimation performance highly improved.

A large-signal simulation program for multi-stage power amplifier modules by using a novel interpolation is presented. This simulation program has the function to make the Load-Pull and Source-Pull (LP/SP) data required for the simulation. By using the interpolation, a lot of LP/SP data can be made from a small number of measured LP/SP data. The interpolation is based on the calculation method using a two-dimensional function. By using the simulation program, we can calculate the large-signal characteristics depended on frequency and temperature of the multi-stage amplifier module. We apply the simulation program to the design of the amplifier. The calculated and measured results agree well. The accuracy of the presented interpolation is confirmed. It is considered that the presented program is useful to calculate large-signal characteristics of the amplifier module.

Optimum antenna sub-set selection in MIMO systems is an attractive cost reducing technique. In this paper we develop an optimal antenna sub-set selection technique to be used in conjunction with space-time block codes over a MIMO link to optimize link error performance over a fading channel. We study the case when antenna sub-set selection is applied either at the transmitter or the receiver. We provide analytical results for substantial improvement in average SNR and outage capacity when antenna sub-set selection is used. Simulation results that verify our analytical prediction are also presented.

A 1T2C-type ferroelectric memory cell, in which two ferroelectric capacitors with the same area are connected to the gate of an usual MOSFET with a SiO2/Si interface, was fabricated and characterized. The relations between various device parameters and characteristics of memory cell were investigated by using SPICE simulation. It was found from the simulation results that the memory window significantly changed by the device parameters, which means that the operation voltage of the memory cell can be well controlled by these parameters. The fabricated cell is composed of a stacked gate structure of Pt/SBT/Pt/Ti/SiO2/Si with the area ratio of the MOS capacitor (SO) to the ferroelectric capacitor (SF) of 6 or 10. Nonvolatile memory operation was confirmed, and the obtained memory window coincided with the simulated results qualitatively. Furthermore, the current on/off ratio in the read-out operation was larger than 3-order-of magnitude and the data retention time was longer than 6 104 seconds. It was also predicted that low voltage operation was possible if the device parameters were optimized.

In this letter, performance evaluation of a system that combines between Code-Division Multiple Access (CDMA) and ALOHA protocol in multimedia networks is presented. In our analysis, we compare the performance between the two basic techniques of ALOHA protocol, i.e., Slotted-ALOHA (S-ALOHA) and Unslotted-ALOHA (U-ALOHA), when combined with CDMA scheme to support voice and data users operating in same CDMA channel. The quality of service (QoS) required for voice and data media is completely taken care of. We obtain the throughput of data media, and the outage probability for voice considering both voice and data offered loads. Throughput performance of S-ALOHA technique is almost twice of that of U-ALOHA. However, we show in this letter that when we combine CDMA with the two basic techniques of ALOHA to accomplish multimedia transmission, both techniques have almost same performance. And, thus, CDMA U-ALOHA can be a good candidate for multimedia networks.

The stage 3/2 decoding scheme, originally suggested by U. Timor, is modified for a Rayleigh fading channel to improve the performance of a fast frequency-hopped multiple access/multilevel frequency shift keying system. When signal-to-noise ratio per bit is 30 dB, the simulation results show that the modified stage 3/2 decoding scheme increases the spectral efficiency by 11% compared to the modified stage 1 decoding scheme at bit error rate of 10-3. Further, the performance comparisons are made between the modified multistage decoding scheme and the diversity combining methods, where the modified stage 3/2 decoding scheme shows better performance.

It is difficult for an adaptive array to reduce interference signals efficiently from received signals when the interference signals and desired signal are closely located. This is a problem for a spatial division multiple access (SDMA) system using the multibeam adaptive array as a multiuser detector. In this paper, we propose a space domain multistage interference canceller (SD-MIC) for the SDMA system. Its performance is evaluated by computer simulations, assuming Japanese personal handy phone system (PHS) uplink environments. The results show remarkable improvement in high spatial correlation situations.

In order to increase the link capacity in the wideband direct sequence code division multiple access (W-CDMA) reverse link, employing a parallel-type coherent multi-stage interference canceller (COMSIC) is more practical than employing a serial (successive)-type due to its inherent advantage of a short processing delay, although its interference suppression effect is inferior to that of the serial-type. Therefore, this paper proposes a parallel-type COMSIC with iterative channel estimation (ICE) using both pilot and decision-feedback data symbols at each canceling stage in order to improve the interference suppression effect of the parallel-type COMSIC. Computer simulation results demonstrate that by applying the parallel-type COMSIC with ICE after FEC decoding, the capacity in an isolated cell can be increased by approximately 1.6 (2.5) times that of the conventional parallel-type COMSIC with channel estimation using only pilot symbols (the MF-based Rake receiver) at the required average transmit Eb/N0 of 15 dB, i.e. in the interference-limited channel. The results also show that, although the capacity in the isolated cell with the parallel-type COMSIC with ICE after FEC decoding is degraded by approximately 6% compared to that with the serial-type COMSIC with ICE after FEC decoding, the processing delay can be significantly decreased owing to the simultaneous parallel operation especially when the number of active users is large.

In this paper, outage performance of a turbo-coded CDMA system is analyzed and simulated in a multiple-beam satellite channel. From the simulation results, it is confirmed that turbo coding provides considerable coding gain over an uncoded system. And, it is demonstrated that Max-Log-MAP decoding algorithm is most promising in terms of performance and complexity.

A low-voltage 6-GHz-band monolithic LC-tank VCO has been fabricated using 0.2-µm CMOS/SIMOX process technology. The VCO features a tuning-range switching technique to achieve a wide tuning range. The output frequency range is between 5.71 and 6.21 GHz owing to the tuning-range switch. With the tuning-range switch on or off, the phase noise is about -100 dBc/Hz at 1-MHz offset and about -120 dBc/Hz at 10-MHz offset frequency at the supply voltage of 2 V.

EL (Electroluminescent) displays have been applied to automobiles, as their images are very clear and bright. High voltage, high integration and low power dissipation ICs are needed to drive these devices. To meet this, high voltage CMOS ICs using SOI (Silicon On Insulator) substrates are chosen as the driving devices. In this paper, an isolation structure between the output CMOS devices, of high density and high voltage is proposed. Conventional trench dielectric isolation shows degradation of a break down voltage with short distance from trench to source. In this work, the authors make clear the electric field distribution near the isolation, and offer a novel structure of "Field-plate Trench Isolation," which enables to relax the electric field on the silicon surface by shifting a part of electric field into surface oxide. Finally, operation of high voltage and high density, a 200-volt and 32-channel, EL display driver for automotive display panel is confirmed.

A new CMOS DC voltage doubler with nonoverlapping switching control is proposed, in order to eliminate the dynamic current loss during switching as well as the threshold voltage drop of the serial switches. The simulated results at 1.5 V show that the maximum power efficiency is improved with about 30%, whereas the efficiency in the low output current region is larger than 5 times compared to the conventional voltage doublers. This proposed CMOS DC voltage doubler can be used as a VPP generator of low voltage DRAM's.

This paper describes 1.0 V operation power performance of a double doped AlGaAs/InGaAs/AlGaAs heterojunction FET for personal digital cellular phones. The developed FET with a multilayer cap consisting of a highly Si-doped GaAs, an undoped GaAs and a highly Si-doped AlGaAs exhibited an on-resistance of 1.3 Ωmm and a maximum drain current of 620 mA/mm. A 28 mm gate-width device, operating with a drain bias voltage of 1.0 V, demonstrated an output power of 1.0 W, a power-added efficiency of 59% and an associated gain of 13.7 dB at an adjacent channel leakage power at 50 kHz off-center frequency of -48 dBc with a 950 MHz π/4-shifted quadrature phase shift keying signal.

Voltage follower is one of the most useful building blocks in analog circuits. This paper proposes a voltage follower composed of a complementary pair of p-channel MOS(PMOS) and n-channel MOS (NMOS) differential amplifiers which operates under low power supply. The proposed circuit has a rail-to-rail dynamic range by combining complementary differential amplifiers.

The reverse-link of the DS-CDMA cellular system requires transmit power control (TPC) and diversity reception. This paper develops the expression of the received signal-to-interference ratio (SIR), and evaluates the outage probability using the Monte Carlo simulation to obtain the link capacity. The link capacities with received signal strength (SS)-based TPC and SIR-based TPC are compared. This paper investigates the required maximum and minimum transmit powers and the capacity gain of the SIR-based TPC over SS-based TPC as well as the effect of the diversity reception on the link capacity and transmit power. The reverse-link capacity is compared with the forward-link capacity to check the balance of capacities between both links.