The power supply voltage of LSI has been lowered due to system requirements for low power dissipation. An on-chip power-on reset pulse generator (POR-PG) is used to determine the initial state of the memory devices of the system LSI. The requirement for the POR-PG is strict for lower power supply voltage because noise margin is smaller relatively. This paper describes a POR-PG for low power voltage supply (Vdd) which overcomes these problems. Hardware measurement proves improved pulse height relative to various power-on profiles (slope, rise time etc.) and fluctuations of temperature and process. Further, the design provides robust noise immunity against voltage fluctuations on the power supply line. The circuit is implemented within a small area (115 µm 345 µm) in the input/output buffer area of a micro-processor and hard-disk controller integrated LSI with 0.25-µm four-layer-metal CMOS technology.

A building block for widening an input range under low power-supply voltages is proposed and the block is used in a popular linearization technique for voltage-to-current converters. The block employs two MOSFETs each of which actively works when and only when the other is in cutoff region. Accurate level shift circuits for the control of the MOSFETs enable such exclusive operation. Simulation results show that the complementary MOSFETs perform as an equivalent MOSFET without any cutoff region. It is also confirmed that the novel linear voltage-to-current converter is effective for not only a wide input range but also low-power consumption.

An LSI has been fabricated and measured to demonstrate feasibility of VDD-hopping scheme in an embedded system level by executing MPEG4 CODEC. In the VDD-hopping, supply voltage of a processor is dynamically controlled by a hardware-software cooperative mechanism depending on workload of the processor. When the workload is about a half, the VDD-hopping is shown to reduce power to less than a quarter compared to the conventional fixed-VDD scheme. The power saving is achieved without degrading real-time features of MPEG4 CODEC.

This paper describes 2.4-GHz-band front-end building circuits--a down conversion mixer (DCM), a dual-modulus divide-by-4/5 prescaler, a transmit/receive antenna switch (SW), a power amplifier (PA), and a low noise amplifier (LNA). They are fabricated using a standard bulk 0.18 µm CMOS process with a lower current consumption than bipolar circuits, and can operate at the low supply voltage of 1.8 V. Meshed-shielded pads are adopted for lower receiver circuit noise. Pads shielded by metals become cracked when they are bounded, therefore silicided active areas are used as shields instead of metals to avoid these cracks. The meshed shields achieve lower parasitic pad capacitors without parasitic resistors, and also act as dummy active areas. The proposed DCM has a high IP3 characteristic. The DCM has a cascode FET configuration and LO power is injected into the lower FET. By keeping the drain-source voltage of the upper transistor large, the nonlinearity of the drain-source transconductance is reduced and a low distortion DCM is realized. It achieves a higher input referred IP3 with a higher conversion gain for almost the same current consumption of a conventional single-balanced mixer. The output referred IP3 is higher 5.0 dB than the single-balanced mixer. The proposed dual-modulus prescaler employs a fully-differential technique to achieve stable operation. In order to avoid errors, the fully-differential circuit gives the logic voltage swing margins. In addition, the differential technique also reduces the noise effect from the supply voltage line because of the common-mode signal rejection. The maximum operating frequency is 3.0 GHz, and the one flip-flop power consumption normalized by the maximum operating frequency is 180 µW/GHz.

For several years, more and more people are joining the Internet and various kind of packets (so called transaction-, block-, and stream-types) have been transmitted in the same network, so that poor network conditions cause loss of the stream-type data packets, such as voices, which request smaller transmission delay time than others. We consider a switching node (router) in a network as an N-series M/G/1-type queueing model and have mainly evaluated the fluctuation of packet delay time and end-to-end delay time, using the two moments matching method with initial value, then define the delay jitter D of a network which consists of jointed N switching nodes. It is clarified that this network is not suitable for voice packets transmission media without measures.

To overcome the problems of the modified Dickson pump like NCP-2, another pump (CCTS-1) where simple voltage doublers are cascaded in series and each of them has cross-coupled configuration is studied in this letter for possible use in low-voltage EEPROMs and DRAMs. Though this concept of cascading doublers has been previously proposed, it is firstly addressed in this letter that CCTS-1 has lower gate-oxide stress, improved voltage pumping gain, and better power efficiency than NCP-2 so that CCTS-1 can be more suitable for multi-stage pump in particular at low VCC. In addition, CCTS-2 is proposed to overcome the degraded body-effect of CCTS-1 without using boosted clocks when the stage number is large.

A fully on-chip open-drain CMOS output driver was designed for high bandwidth DRAMs, such that its output voltage swing was insensitive to the variations of temperature and supply voltage. An auto refresh signal was used to update the contents of the current control register, which determined the transistors to be turned-on among the six binary-weighted transistors of an output driver. Because the auto refresh signal is available in DRAM chips, the output driver of this work does not require any external signals to update the current control register. During the time interval while the update is in progress, a negative feedback loop is formed to maintain the low level output voltage (VOL) to be equal to the reference voltage (VOL.ref) which is generated by a low-voltage bandgap reference circuit. Test results showed the successful operation at the data rate up to 1 Gb/s. The worst-case variations of VOL.ref and VOL of the proposed output driver were measured to be 2.5% and 7.5% respectively within a temperature range of 20 to 90 and a supply voltage range of 2.25 V to 2.75 V, while the worst-case variation of VOL of the conventional output driver was measured to be 24% within the same ranges of temperature and supply voltage.

The concept of a "standardized brain" is familiar in modern functional neuro-imaging techniques including PET and fMRI, but it has never been adopted for optical imaging studies that deal with a regional cortical area rather than the whole brain. In this paper, we propose a "standardized barrel cortex" for rodents, and present a method for mapping optically detected neural activity onto the standard cortex. The standard cortex is defined as a set of simple cortical columns, which are modeled on the cytoarchitectonic patterns of cell aggregates in cortical layer IV of the barrel cortex. Referring to its underlying anatomical structure, the method warps the surface image of individual cortices to fit the standard cortex. The cortex is warped using a two-dimensional free-form deformation technique with direct manipulation. Since optical imaging provides a map of neural activity on the cortical surface, the warping consequently remaps it on the standard cortex. Data presented in this paper show that somatosensory evoked neural activity is successfully represented on the standardized cortex, suggesting that the combination of optical imaging with our method is a promising approach for investigating the functional architecture of the cortex.

It is well known that interpath interference (IPI) is a major factor that limits the performance of high data rate transmissions over a variable spreading factor wideband-CDMA (W-CDMA) link since the spreading factor is in general small. An optimum combining scheme suppressing IPI was recently proposed for RAKE reception in [1]. The main contribution of this letter is to present a theoretical model for the outage probability and bit error probability of a RAKE receiver utilizing the optimum combining scheme. Analytical and simulation results are closely matched and show that the optimum scheme provides significant performance improvement compared to the conventional maximum ratio combining (MRC) scheme.

This paper investigates the interference suppression effect from much higher rate dedicated physical channels (DPCHs) of a parallel-type coherent multistage interference canceller (COMSIC) with iterative channel estimation (ICE) by laboratory experiments in the transmit-power-controlled W-CDMA reverse link. The experimental results elucidate that when two interfering DPCHs exist with the spreading factor (SF) of 8 and with the ratio of the target signal energy per bit-to-interference power spectrum density ratio (Eb/I0) of fast transmit power control, ΔEb/I0, of -6 dB (which corresponds to 64 simultaneous DPCHs with SF = 64, i.e., the same symbol rate as the desired DPCH), the implemented COMSIC receiver with ICE exhibits a significant decrease in the required transmit signal energy per bit-to-background noise power spectrum density ratio (Eb/N0) at the average bit error rate (BER) of 10-3 (while the matched filter (MF)-based Rake receiver could not realize the average BER of 10-3 due to severe multiple access interference (MAI)). It is also found that the achieved BER performance at the average BER of 10-3 of the COMSIC receiver with the A/D converter quantization of 8 bits in the laboratory experiments is degraded by approximately 1.0 dB and 4.0 dB compared to the computer simulation results, when ΔEb/I0=-6 dB and -9 dB, respectively, due to the quantization error of the desired signal and path search error for the Rake combiner. Finally, we show that the required transmit Eb/N0 at the average BER of 10-3 of the third-stage COMSIC with ICE is decreased by approximately 0.3 and 0.5 dB compared to that of COMSIC with decision-feedback type channel estimation (DFCE) with and without antenna diversity reception, respectively.

A priming effect is studied for a three-electrode, surface-discharge AC-PDP, which has stripe barrier ribs of 0.22 mm pitch. It was found that by keeping the interval between the reset and address pulses within 24 µs, the data pulse voltage can be reduced while the data pulse width can be narrowed due to the priming effect. By adopting the primed addressing technique to the PDP, the data pulse voltage was reduced to 20 V when the data and scan pulse widths were 1 µs. Alternatively, the data pulse width could be narrowed to 0.33 µs when the data pulse voltage was 56 V. 69% of the TV field time could be assigned for the display periods with 12 sub-fields, assuring high luminance display.

In this paper we propose a MIN (Multistage Interconnection Network) whose performance in the faulty case degrades as gracefully as possible. We focus on a two-dilated baseline network as a sort of MIN. The link connection pattern in our MIN is determined so that all the available paths established between an input terminal and an output terminal via an identical input of a SE (Switching Element) in some stage will never pass through an identical SE in the next stage. Extra links are useful in improving the performance of the MIN and do not complicate the routing scheme. There is no difference between our MIN and others constructed from a baseline network with regard to numbers of links and cross points in all SEs. The theoretical computation and simulation-based study show that our MIN is superior to others in performance, especially in robustness against concentrated SE faults in an identical stage.

A system level approach for a memory power reduction is proposed in this paper. The basic idea is allocating frequently executed object codes into a small subprogram memory and optimizing supply voltage and threshold voltage of the subprogram memory. Since large scale memory contains a lot of direct paths from power supply to ground, power dissipation caused by subthreshold leakage current is more serious than dynamic power dissipation. Our approach optimizes the size of subprogram memory, supply voltage, and threshold voltage so as to minimize memory power dissipation including static power dissipation caused by leakage current. A heuristic algorithm which determines code allocation, supply voltage, and threshold voltage simultaneously so as to minimize power dissipation of memories is proposed as well. Our experiments with some benchmark programs demonstrate significant energy reductions up to 80% over a program memory which does not employ our approach.

We have developed InGaP-channel field effect transistors (FETs) with high breakdown voltages that can be fabricated by using conventional GaAs FET fabrication processes. The buffer and barrier layers were also optimized for the realization of high-voltage operation. The InGaP-channel FET has an extremely high on-state drain-to-source breakdown voltage of over 40 V, and a gate-to-drain breakdown voltage of 55 V. This enabled high-voltage large-signal operation at 40 V. The third-order intermodulation distortion of the InGaP channel FETs was 10-20 dB lower than that of an equivalent GaAs-channel FET, due to the high operating voltage.

A novel multilevel construction for permutation codes is presented. A permutation code of length n is a subset of all the vectors obtained from coordinate permutations on the vector (0,1,. . . ,n-1). We would like to construct a permutation code with cardinality as large as possible for a given code length n and a minimum distance. The proposed construction is available when n = 2m (m is a positive integer). We exploit m-constant weight binary codes as component codes and combine them in a multilevel way. Permutation codes with various parameters can be constructed by selecting appropriate combination of component codes. Furthermore, multi-stage decoding is available for decoding the permutation codes constructed by the proposed construction.

This paper presents improved versions of three-stage positive-output and two-stage negative-output Dickson charge-pump circuits which are intended to replace switching regulators in video-product CCD driver applications (where 12 V and -6.5 V are needed), and are designed and fabricated in a custom CMOS process. From a power supply Vdd of 4.0 to 5.5 V, the positive charge pump generates a positive output voltage of greater than 3.9Vdd, while the negative charge pump generates a negative voltage of greater than -1.9Vdd, both with efficiencies of greater than 94% at 2 mA output currents.

We report here on the electrical and structural characteristics of InGaP/GaInAsN DHBTs with up to a 50 mV reduction in turn-on voltage relative to standard InGaP/GaAs HBTs. High p-type doping levels ( 3 1019 cm-3) and dc current gain (βmax up to 100) are achieved in GaInAsN base layer structures ranging in base sheet resistance between 250 and 750 Ω/. The separate effects of a base-emitter conduction band spike and base layer energy-gap on turn-on voltage are ascertained by comparing the collector current characteristics of several different GaAs-based bipolar transistors. Photoluminescence measurements are made on the InGaP/GaInAsN DHBTs to confirm the base layer energy gap, and double crystal x-ray diffraction spectrums are used to assess strain levels in the GaInAsN base layer.

This paper proposes a new coherent CDMA channel structure for the uplink with staggered burst pilot and its detection algorithm. In the uplink, mobiles in a cell share a pilot channel by transmitting periodic bursts in nonoverlapping time slots, which enables coherent detection. We analyze the uplink capacity and derive the capacity formula. The dual mode channel estimator (DMCE) consists of pilot-based channel estimation (PBCE) and data-based channel estimation (DBCE). The proposed DMCE algorithm is very stable in the presence of Gaussian noise and Doppler shift because the pilot burst initiates the DMCE operation periodically. A negligible loss (0.068 dB) in Eb/N0 results from the introduction of the burst pilot. When compared with ideal (0 km/h) coherent detection, the required Eb/N0 in Doppler shift, corresponding to the speed of 160 km/h, is degraded less than 2.0 dB. The simulation result also shows increased channel capacity. The burst pilot can be implemented without added complexity even though some extra correlators are needed for the DMCE. This improvement is significant compared to previously published studies of coherent CDMA detectors with non-shared pilots.

Reliability-based decoding algorithm in multistage decoding of multilevel codes is discussed. Through theoretical analyses, effects of soft reliability information are examined for different types of partitionings.

We propose an effective model that can reproduce the reverse short channel effect (RSCE) of the threshold voltage (Vth) of MOSFETs using a conventional process simulator that solves one equation for each impurity. The proposed model is developed for local modeling which is effective within the limited process conditions. The proposed model involves the physics in which RSCE is due to the pile up of channel dopant at the Si/SiO2 interface. We also report the application to actual device design using our model. The calculation cost is much lower than for a pair diffusion model, and device design in an acceptable turn around time is possible.