A novel zero-voltage-switched half-bridge converter is proposed. This converter achieves the zero-voltage switching while maintaining a constant frequency PWM control. Then the power conversion of high efficiency and low noise is realized at a higher switching frequency. In the experiment, a high efficiency of 83% is achieved for a low output voltage of 3.3 V, an output current of 30 A, and an input-voltage range of 200 to 400 V at the switching frequency of 400 kHz.

Unequal error protection (UEP) is a very promising coding technique for satellite broadcasting, as it gradually reduces the transmission rate. From the viewpoint of bandwidth efficiency, UEP should be achieved in the context of multilevel coded modulation. However, the conventional mapping between encoded bits and modulation signals, usually realized for multilevel block modulation codes and multistage decoding, is not very compatible with UEP coding because of the large number of resulting nearest neighbor codewords. In this paper, new coded modulation schemes for UEP based on unconventional partitioning are proposed. A linear operation referred to as interlevel combination is introduced. This operation generalizes previous partitioning proposed for UEP applications and provides additional flexibility with respect to UEP capabilities. The error performance of the proposed codes are evaluated both by computer simulations and a theoretical analysis. The obtained results show that the proposed codes achieve good tradeoff between the proportion and the error performance of each error protection level.

In this paper, a virtual-short circuit which consists of only two MOS transistors operated in the weak-inversion region is proposed. It has the advantages of almost zero power consumption, low voltage operation, small chip area, and no needlessness of bias voltages or currents. The second order effects, such as the device mismatch, the Early effect, and the temperature dependency of the circuit are analyzed in detail. Next, current-controlled and voltage-controlled current sources using the proposed virtual-short circuit are presented as applications. The performance of the proposed circuits is estimated using SPICE simulation with MOSIS 1. 2 µm CMOS device parameters. The results are reported on this paper.

An elastic-Vt CMOS circuit is proposed which facilitates both high speed and low power consumption at low supply voltages. This circuit permits fine-grain power control on each multiple circuit block composing a chip, and it is not sensitive to design factors as device-parameter deviations or operating-environment variations. It also does not require any such additional fabrication technology as triple-well structure or multi-threshold voltage. The effectiveness of the circuits design was confirmed in applying it to specially fabricated 16-bit adders and 4-kb SRAMs based on 1. 5-V, 0. 35- µm CMOS technology.

A single-chip GaAs Transmit/Receive (T/R)-MMIC front-end has been developed which is applicable to 1. 9-GHz personal communication terminals such as digital cordless phones. This chip is fabricated using a planar self-aligned gate FET useful for low-cost and high-volume production. The chip integrates RF front-end analog circuits a power amplifier, a T/R-switch, and a low-noise amplifier. Additionally integrated are a newly developed voltage-doubler negative-voltage generator (VDNVG) and a control logic circuit to control transmit and receive functions, enabling both a single-voltage operation and an enhanced power handling capability of the switch, even under a single low-voltage supply condition of 2 V. The power amplifier incorporated onto the chip is capable of delivering a 21 dBm output power at a 39% efficiency, and a 30 dB associated gain with a 2 V single power supply in the transmit mode. The gain and efficiency are higher than those of the previously reported amplifier operating with a 2 V single power supply. The VDNVG produces a step-up voltage of 2. 9 V as well as a negative voltage of -1. 8 V from a 2 V power supply, operating with a charge time of less than 0. 25 µs. The control logic circuit on the chip has a newly designed interface circuit utilizing the step-up voltage and negative voltage, thereby enabling the chip to handle high power outputs over 24 dBm with a low operating voltage of 2 V. In the receive mode, a 1. 7 dB noise figure and a 0. 6 dB insertion loss are achieved with a current dissipation of 3. 6 mA. The developed MMIC, which is the first reported 2 V single-voltage operation T/R-MMIC front-end, is expected to contribute to the size and weight reductions in personal communication terminals.

A unified tag by which both TLBs and caches can be accessed is presented. This architecture reduces the chip area of conventional cache tags and also improves the speed of cache systems. In addition, it has expanded to support snoop accesses for multiprocessor environments. To validate the proposed architecture, we measured the area and speed based on VLSI circuits.

This paper describes design approach and power performance of a single 1. 5 V operation two-stage power amplifier MMIC for 2. 4 GHz wireless local area network applications. The MMIC with 0. 760. 96 mm2 area includes SrTiO3 (STO) capacitors with a high capacitance density of 8. 0 fF/µm2 and double-doped AlGaAs/InGaAs/AlGaAs heterojunction FETs with a shallow threshold voltage of -0. 24 V. Utilizing a series STO capacitor and a shunt inductor as an output matching circuit, the total chip size was reduced by 40% as compared with an MMIC utilizing SiNx capacitors. Under single 1.5 V operation, the developed MMIC delivered an output power of 110 mW (20.4 dBm) and a power-added efficiency (PAE) of 36.7% with an associated gain of 20.0 dB at 2.4 GHz. Even operated at a drain bias voltage of 0.8 V, the MMIC exhibited a high PAE of 31.0%.

This paper describes a calculation method of large-signal characteristics of multi-stage power amplifier modules using source-pull and load-pull data. An output power, a power-added efficiency, and a phase deviation of multi-stage power amplifier modules are calculated based on the source-pull and load-pull data, which are comprised of input and output reflection coefficients, an input power, an output power, a phase deviation and a drain voltage and current, taking into account the source and load impedance of each stage FET. Applying this method to a 900 MHz two-stage Si-MOSFET power amplifier module, the calculated and measured results are in good agreement.

This paper describes the evaluation of the Voltage Down Converter (VDC) with low ratio of consuming current to load current in DC/AC operation mode. The stability, response and power consumption are investigated. First, for the stability and response, the VDC can operate in the condition that the bounce of the down voltage (dVDL) is no more than 10% of the setting voltage and the maximum load operation frequency (fmax) is 100 MHz at the average load current 70 mA (the maximum load current 140 mA). Secondly, for the power consumption, by using this VDC technology, the value of IC/IL can be suppressed to 5.1E-4 (IC: total consuming current in VDC, IL: average load current) in the condition that dVDL is no more than 10% of the setting voltage and fmax is 10 MHz at the average load current 70 mA. Thus, it is made clear that the VDC can realize high stability, good response and low power consumption at the same time. This technology is suitable for high performance ULSIs which require large load current and low-power consumption.

A GaAs power amplifier IC has been developed for 1. 9-GHz digital mobile communication applications, such as the handsets of the Japanese personal handy phone system (PHS), which was assembled into a very small 0. 012-cc surface mount plastic package. This power amplifier using refractory WNx/W self-aligned gate MESFETs with p-pocket layers can operate with high efficiency and low distortion with a single 3-V supply. A very low dissipated current of 119 mA was obtained with an output power of 21. 1 dBm and a low 600-kHz adjacent channel leakage power (ACP) of -63 dBc for π/4-shifted quadrature phase shift keying (QPSK) modulated input.

A GaAs power MESFET amplifier with a low-distortion, 10-dB gain-variable attenuator has been developed for 1. 9-GHz Japanese personal handy phone system (PHS). Independently of its gain, a very low 600-kHz adjacent channel leakage power (ACP) with sufficient output power was attained. In single low 2. 4-V supply operation, an output power of 21. 1 dBm, a low dissipated current of 157 mA and a high power-added efficiency (PAE) of 37. 2% were obtained with an ACP of -55 dBc.

In the future asynchronous transfer mode (ATM) networks, an efficient virtual path (VP) control strategy must be applied to guarantee the network has high throughput with tolerable node processing load. The multistage VP control may be the best candidate since the tasks in this method are shared by the central node and local nodes, and it allows us to track the traffic changes while maintain a good state of the VP topology by reconfiguring it at regular or need based intervals. In this paper, we focus on the VP topology optimization problem in the multistage VP control. We first present the problem formulation in which the tradeoff between the network throughput and processing costs is considered, and then employ an algorithm based on a route-neuron Hopfield neural network (HNN) model to solve this problem. The numerical results demonstrate the HNN can converge to optimal solutions with high probability and stability while in other cases to near optimal solutions if the values of the system parameters in the route-neuron model are chosen according to some empirical formulas provided in this paper.

The Rician factor is an important parameter in evaluating the outage probability and reuse distance of cellular systems. From the measurement of 1. 8 GHz radio propagation in outdoor urban microcells, it is found that the measured pdf of the Rician factor for low tier systems follows a lognormal distribution and the factor is independent on the propagation distance.

This letter describes new active building blocks defined as the generalized voltage conveyor (GVC) and the generalized current conveyor (GCC). A very simple practical realization of the GVC using the second generation current conveyors (CCII) is given. The special cases of the first generation voltage conveyor (VCI) and the second generation voltage conveyor (VCII) are also considered. A practical realization of the GCC using the CCII is also given. Applications of the voltage and current conveyors in oscillators are considered.

In recent years, there has been a rapid growth in applications such as World Wide Web browsing, which are characterized by fairly short sessions that transfer substantial amounts of data. Conventional connection-oriented and datagram services are not ideally engineered to handle this kind of traffic. We present a new ATM service, called Dynaflow service, in which virtual circuits are created on a burst-by-burst basis and we evaluate key aspects of its performance. We compare Dynaflow to the Fast reservation protocol (FRP) and show that Dynaflow can achieve higher overall throughput due to the elimination of reservation delays, and through the use of shared "burst-stores. " We study the queueing performance of the dynaflow switch and quantify the relationship between the loss ratio and the buffer size.

Ferroelectric non-volatile memory (FeRAM) has been inspiring interests since bismuth layer perovskite material family was found to provide "Fatigue Free" endurance, superior retention and imprint characteristics. In this paper, we will provide new circuits technology for FeRAM developed to implement high speed operation, low voltage operation and low power consumption. Performance of LSI embedded with FeRAM for contactless IC card is also provided to demonstrate the feasibility of the circuit technology.

In this paper, we propose an interference canceller for asynchronous DS-CDMA. The principle is based on parallel cancellation using soft decision(PCSD), however, we propose to add an operation to suppress the strength of interfering signals replica on PCSD. We show here that this operation plays a very important theoretical role in PCSD, and that the performance of our proposed scheme approaches that of a perfect decorrelating detector under certain conditions. With this theoretical background in mind, we named this scheme the "Near-Decorrelating Multistage Detector"(NDMD). To demonstrate NDMD performance, we performed two kinds of computer simulations. In the first kind of simulation, simple conditions are assumed in order to evaluate basic cancelling performance. In the other kind of simulation, essential techniques for CDMA cellular systems such as FEC, transmission power control(TPC), and base band filtering were implemented while taking into account NDMD as applied to such systems. These simulations numerically demonstrate that NDMD is very efficient in cancelling out interference and that it improves asynchronous DS-CDMA performance.

The electromagnetic interference (EMI) induced by steady arc has been demonstrated to be dependent on arc voltage fluctuation when the arc transfers from the metallic phase to the gaseous phase. In order to give the physical understanding of this arc voltage fluctuation and EMI, several typical materials, such as Ag, Cu and Zr, were tested and their arc behavior was determined and compared. The experimental results indicated that the arc behavior, in particular the arc voltage fluctuation in the moment that metallic phase transfers to the gaseous phase was different for different materials. Based on the test results and former investigations, a plausible mechanism is proposed for understanding these phenomena.

A technique for realization of low-voltage OTAs is presented in this letter. A very low-voltage differential-output OTA is realized by employing a new common-mode amplifier in the common-mode feedback circuit. The results of PSpice simulations are shown. The proposed OTA can operate at a 0. 9 V supply voltage.

This paper describes an MOS current-mode sample-and-hold (S/H) circuit that potentially operates with a sub-1. 5 V supply voltage, 20 MHz clock frequency, and less than 0. 1% linearity. A newly developed voltage-to-current converter suppresses the voltage change at an input terminal and achieves low-voltage operation with superior linearity. Sample switches are differentially placed at the inputs of a differential amplifier so that the feedthrough errors from switches cancel out. The MOS current-mode S/H circuit is designed and simulated using CMOS 0. 6 µm device parameters. Simulation results indicate that an operation with 20 MHz clock frequency, linearity error of less than 0. 1%, and 1 MHz input from a 1. 5 V power supply is achievable.