The current-voltage characteristics of a single electron transistor (SET) in the resonant transport mode are investigated. In the future when SET devices are applied to integrated electronics, the quantum effect will seriously modify their characteristics in ultra-small geometry. The current will be dominated by the resonant transport through narrow energy levels in the dot. The simple case of a two-level system is analyzed and the transport mechanism is clarified. The transport property at low temperatures (higher than the Kondo temperature) in the low tunneling rate limit is discussed, and a current map where current values are classified in the gate bias-drain bias plane is provided. It was shown that the dynamic aspect of electron flow seriously influences the current value.

In this work, a CMOS on-chip current reference circuit for memory, operational amplifiers, comparators, and data converters is proposed. The reference current is nearly insensitive to temperature and supply-voltage variations. In the proposed circuit, the current component with a positive temperature coefficient cancels that with a negative temperature coefficient each other. While conventional current reference circuits are based on bipolar transistors in BiCMOS, bipolar, or CMOS processes, the proposed circuit can be integrated on a single chip with other digital and analog circuits using a standard CMOS process and extra masks are not required. Measured results are demonstrated for two different prototypes. The first is fabricated employing a 1.0 µm p-well double-poly double-metal CMOS process and operates at 5 V nominally. The second, based on a 0.6 µm n-well process, is optimized for 3 V to 5 V operation. The latter prototype achieves the temperature coefficient of 98 ppm/ over a temperature range from -25 to 75 and the output variation of 1.5% with the supply-voltage changes from 2.5 V to 5.5 V. A simple calibration technique for reducing output current variations improves circuit yield.

A GaAs linear power amplifier operating with a single 3-V supply has been developed for 5.8-GHz ISM band applications. Two kinds of refractory WNx/W self-aligned gate MESFETs, a P-pocket MESFET and an asymmetric MESFET with a buried p-layer (BP- MESFET ) have been compared in terms of DC characteristics, small signal characteristics and power performances at 5.8 GHz. To obtain both high gain and high efficiency in the case of single 3-V supply operation at 5.8 GHz, we used a highly efficient and linear P-pocket MESFET for the output-stage power FET and a high-gain asymmetric MESFET with a buried p-layer (BP- MESFET ) for the driver-stage FET. The bias condition for 1-mm output-stage P-pocket MESFET was set near class-AB, so as to obtain sufficient output power with high PAE. The two-stage power amplifier MMIC module which can include all matching and biasing circuits, has been designed and fabricated. The amplifier exhibits a high power gain of 17.9 dB and a high power-added efficiency of 25.7% with a sufficient output power of 18.7 dBm at the 1-dB compression point. This self-aligned gate GaAs MESFET technology is promising for near-future 5.8-GHz applications, because of such good power performance and good mass-producibility.

This paper describes an MOS current-mode, voltage-controlled oscillator (VCO) circuit that potentially operates with a 2 V supply voltage, 500 MHz oscillation frequency, and -90 dBc/Hz phase noise at the 1 MHz offset. It also has an improved oscillation frequency linearity of the control voltage and 11 mW power dissipation. The oscillation frequency reached 920 MHz when the supply voltage was increased to 3 V.

Low-voltage technique for IC is getting one of the most important matters. It is quite difficult to realize a filter which can operate at 1 V or less because the base-emitter voltage of transistors can hardly be reduced. A design of a low-voltage continuous-time filter is presented in this paper. The basic building block of the filter is a pseudo-differential transconductor which has no tail current source. Therefore, the operating voltage is lower than that of an emitter-coupled pair. However, the common-mode (CM) gain of the transconductor is quite high and the CMRR is low. In order to reduce the CM gain, a CM feedback circuit is employed. The transconductance characteristic is expressed as the function of hyperbolic cosine. The designed filter is a fifth-order gyrator-C filter. The transconductor and the filter which has a fifth-order Butterworth lowpass characteristic are demonstrated by PSpice simulation. Transconductance characteristic, CMRR and stability of the transconductor are confirmed through the simulation. In the analysis of the filter, frequency response and offset voltage are examined. It is shown that the filter which has corner frequency of the order of megahertz can operate at a 1 V supply voltage.

We propose a new inverse modeling method to extract 2D channel dopant profile in an MOSFET. The profile is extracted from threshold voltage (Vth) of MOSFETs with a series of gate lengths. The uniqueness of the extracted channel and drain profile is confirmed through test simulations. The extracted profile of actual 0.1 µm nMOSFETs explains reverse short channel effects (RSCE) of threshold voltage dependent on gate length including substrate bias dependence.

The architecture and control procedure for a direct conversion receiver are investigated for a linear modulation scheme. The proposed design techniques maintain receiver linearity despite various types of signal distortion. The techniques include the fast gain control procedure for receiving a control channel for air interface connection, DC offset canceling in both analog and digital stages, and 2nd-order intermodulation distortion canceling in an analog down-conversion stage. Experimental and computer simulation results on PHS (Personal Handy-phone System) parameters, showed that required linear modulation performance was achieved and thus the applicability of the proposed techniques was demonstrated.

An on-chip high voltage generator applicable to low voltage flash memory is introduced. Bootstrapped gate transfer switches of two parallel paths suppress the voltage loss due to threshold voltage drop of transfer transistors. The simulated results demonstrate that proposed circuit designed with NMOS transistors having 0.8 volt threshold voltage works like an ideal charge pump circuit near 1.0 volt range with enough current driving capability.

In this paper, a four-quadrant analog multiplier consisting of four neuron-MOS transistors and two load resistors is proposed. The proposed multiplier can be operated at only 1 V. Furthermore, the input range of the multiplier is equal to 100% of the supply voltage. The theoretical harmonic distortion caused by mobility degradation and device mismatchs is derived in detail. The performance of the proposed multiplier is characterized through HSPICE simulations with a standard 2.0 µm CMOS process with a double-poly layer. Simulations of the proposed multiplier demonstrate that the linearity error of 0.77% and a total harmonic distortion of 0.62% are obtained with full-scale input conditions. The maximum power consumption and 3 dB bandwidth are 9.56 µW and 107 MHz, respectively. The active area of the proposed multiplier is 210 µm 140 µm.

This paper presents a new technique for modeling High-Voltage lightly-doped-drain MOS (HV MOS) devices accurately with the BSIM3v3 SPICE model. Standard SPICE models do not model the voltage dependency of Rs and Rd in HV MOS devices; this causes large discrepancies between the simulated and measured I-V characteristics of HV MOS devices. We propose to assign physical meanings and values different from the original BSIM3v3 model to three of its parameters to represent the voltage dependency of Rs and Rd. With this method, we have succeeded in highly accurate parameter extraction, and the simulated I-V characteristics of HV MOS devices using the extracted parameters match the measured results well. The relationship between the proposed modeling technique and the physical mechanism of HV MOS devices is also discussed based on measurement and device simulation results. Since our method does not change any model equations of BSIM3v3, it can be applied to any SPICE simulator on which the BSIM3v3 model runs, so we can use SPICE simulation for accurate circuit design of complex circuits using HV MOS devices.

Ultra-low-power-consumption and high-speed DCFL circuits have been fabricated by using 0.2-µm Y-shaped gate E/D-heterojunction-FETs (HJFETs) with a high-aspect-ratio gate-structure, which has an advantage of reducing the gate-fringing capacitance (Cf) to about a half of that of a conventional low-aspect-ratio one. A fabricated 51-stage ring oscillator with the 0.2-µm Y-shaped gate n-AlGaAs/i-InGaAs E/D-HJFETs shows the lowest power-delay product of 0.21 fJ with an unloaded propagation delay of 34.9 ps at a supply voltage (VDD) of 0.4 V. We also analyze the DCFL switching characteristics by taking into account the intrinsic gate-to-source capacitance (Cgsint) and the Cf. The analysis results for the power-delay products agree well with our experimental results. Our analysis also indicates the DCFL circuit with the high-aspect-ratio Y-shaped gate E/D-HJFETs can reduce the power-delay products by 35% or more below 0.25-µm gate-length as compared to conventional ones with the low-aspect-ratio Y-shaped gate HJFETs. These results clarify that the Cf-reduction of the Y-shaped gate HJFETs is more effective in improving the power-delay products than reducing the gate-length.

In this paper we introduce a CMOS low voltage/low power (LV/LP) voltage controlled oscillator (VCO). It includes a simple V-I converter, a current controlled ring oscillator based on new differential delay cells, and a source-coupled differential pair to convert differential signal to single-ended signal. The V-I converter is implemented as a source follower type, exhibiting excellent linearity of transconductance with low power consumption. The new delay cell employs local positive feedback to increase its DC gain, achieving stable oscillation at low supply voltage. The simulation and measurement results are given to show the linearity between the input (control voltage) and the output (frequency) in the frequency range of 100 MHz to 400 MHz with 1. 2 V power supply. The VCO only consumes power of 2.25 mW at operating frequency of 400 MHz and 1.2 V supply.

This paper describes a newly developed FET Coupled Logic (FCL) circuit that operates at very high frequencies with very low supply voltages below 3.3 V. An FCL circuit consists of NMOS source-coupled transistor pairs for current switches, load resistors, emitter followers and current sources that are controlled by a band-gap reference bias generator. The characteristics and performance are discussed by comparing this circuit with other high-speed circuits. The optimal circuit parameters for FCL circuits are also discussed, and the fact is noted that a larger swing voltage enhances the circuit's performance. The simulated delay of a 0.25 µm FCL circuit is less than 15 ps for a 2.5 V power supply, and the simulated maximum toggle frequencies are over 5 GHz and 10 GHz at 2.5 V and 3.3 V power supply, respectively. The simulation results show that FCL circuits achieve the best performance among the current mode circuits, which include ECL circuits, NMOS source-coupled logic circuits. The delay of the FCL circuit is less than half that of an ECL circuit. The maximum toggle frequency of the FCL circuit is about triple that of NMOS source-coupled logic circuit. Because the FCL circuit uses low-cost CMOS-based BiCMOS technologies, its cost performance is superior to ECL circuits that require expensive base-emitter self-aligned processes and trench isolation processes. Using depletion-mode NMOS transistors for current switches can lower the minimum supply voltage for FCL circuits and it is below 1.5 V. The FCL circuit is a promising logic gate circuit for multi-Gbit/s tele/data communication LSIs.

A new low voltage high-speed CMOS composite transistor is presented. It lowers supply voltage down to |Vt|+2 Vds,sat and considerably extends input voltage operating range and achieves high speed operation. As an application example, it is used in the design of a high-speed four quadrant analog multiplier. Simulations results using MOSIS 2µm N-well process with a 3 V supply are given.

This paper proposesd a non-blocking multi-stage ATM switch based on a hierarchical-cell-resequencing (HCR) mechanism and high-speed WDM interconnection and reports on its feasibility study. In a multi-stage ATM switch, cell-based routing is effective to make the switch non-blocking, because all traffic is randomly distributed over intermediate switching stages. But due to the multi-path conditions, cells may arrive out of sequence at the output of the switching fabric. Therefore, resequencing must be performed either at each output of the final switching stage or at the output of each switching stage. The basic HCR switch performs cell resequencing in a hierarchical manner when switching cells from an input-lines to a output-line. As a result, the cell sequence in each output of the basic HCR switch is recovered. A multi-stage HCR switch is constructed by interconnecting the input-lines and output-lines of these basic HCR switches in a hierarchical manner. Therefore, the cell sequence in each final output of the switching fabric is conserved in a hierarchical manner. In this way, cell-based routing becomes possible and a multi-stage ATM switch with the HCR mechanism can achieve 100% throughput without any internal speed-up techniques. Because a large-capacity multi-stage HCR switch needs a huge number of high-speed signal interconnections, a breakthrough in compact optical interconnection technology is required. Therefore, this paper proposes a WDM interconnection system with an optical router arrayed waveguide filter (AWGF) that interconnects high-speed switch elements effectively and reports its feasibility study. In this architecture, each switch element is addressed by a unique wavelength. As a result, a switch in a previous stage can transmit a cell to any switch in the next stage by only selecting its cell transmission wavelength. To make this system feasible, we developed a wide-channel-spacing optical router AWGF and compact 10-Gbit/s optical transmitter and receiver modules with a compact high-power electroabsorption distributed feedback (EA-DFB) laser and a new bit decision circuit. Using these modules, we confirmed stable operation of the WDM interconnection. This switch architecture and WDM interconnection system should enable the development of high-speed ATM switching systems that can achieve throughput of over 1 Tbit/s.

Design and evaluation of a high-performance switch architecture for free-space photonic switching systems is described. The switch is constructed of 22 switching elements and employs special multistage interconnection patterns. The connection setup algorithm and the control procedure at the switching elements are based on a "rerouting algorithm." Performance analysis shows that the blocking probability of the switch is easily controlled by increasing the number of switching stages. Example implementations of this switch are shown in which birefringent plates, polarization controllers, etc. are used.

Design and evaluation of a high-performance switch architecture for free-space photonic switching systems is described. The switch is constructed of 22 switching elements and employs special multistage interconnection patterns. The connection setup algorithm and the control procedure at the switching elements are based on a "rerouting algorithm."" Performance analysis shows that the blocking probability of the switch is easily controlled by increasing the number of switching stages. Example implementations of this switch are shown in which birefringent plates, polarization controllers, etc. are used.

This paper proposesd a non-blocking multi-stage ATM switch based on a hierarchical-cell-resequencing (HCR) mechanism and high-speed WDM interconnection and reports on its feasibility study. In a multi-stage ATM switch, cell-based routing is effective to make the switch non-blocking, because all traffic is randomly distributed over intermediate switching stages. But due to the multi-path conditions, cells may arrive out of sequence at the output of the switching fabric. Therefore, resequencing must be performed either at each output of the final switching stage or at the output of each switching stage. The basic HCR switch performs cell resequencing in a hierarchical manner when switching cells from an input-lines to a output-line. As a result, the cell sequence in each output of the basic HCR switch is recovered. A multi-stage HCR switch is constructed by interconnecting the input-lines and output-lines of these basic HCR switches in a hierarchical manner. Therefore, the cell sequence in each final output of the switching fabric is conserved in a hierarchical manner. In this way, cell-based routing becomes possible and a multi-stage ATM switch with the HCR mechanism can achieve 100% throughput without any internal speed-up techniques. Because a large-capacity multi-stage HCR switch needs a huge number of high-speed signal interconnections, a breakthrough in compact optical interconnection technology is required. Therefore, this paper proposes a WDM interconnection system with an optical router arrayed waveguide filter (AWGF) that interconnects high-speed switch elements effectively and reports its feasibility study. In this architecture, each switch element is addressed by a unique wavelength. As a result, a switch in a previous stage can transmit a cell to any switch in the next stage by only selecting its cell transmission wavelength. To make this system feasible, we developed a wide-channel-spacing optical router AWGF and compact 10-Gbit/s optical transmitter and receiver modules with a compact high-power electroabsorption distributed feedback (EA-DFB) laser and a new bit decision circuit. Using these modules, we confirmed stable operation of the WDM interconnection. This switch architecture and WDM interconnection system should enable the development of high-speed ATM switching systems that can achieve throughput of over 1 Tbit/s.

A 1.5 V 8 mW BiCMOS video A/D converter has been developed by using a BiCMOS pumping comparator. Combining Bipolar high-speed and good-matching characteristics with CMOS switched capacitor techniques, this A/D converter is suitable for use in battery-operated multimedia terminals.

A high performance voltage down converter (VDC) is proposed in this paper. The proposed VDC can automatically control the driving current in seven phases to reduce the fluctuation of output voltage in VDC. By using above new flexible control technology of driving current, the fluctuation of output voltage can be suppressed to less than 10% and the average consuming current of VDC can be suppressed to 34 µA, even if the operation frequency is 200 MHz at the average driving current 100 mA. Therefore, the proposed VDC can operate with large driving current, low-power consumption and good response at the same time. Above all, this technology is very suitable for high perform ULSIs which require large load current, very low-power and high speed operation.